X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Farch%2Faarch64.h;h=aed10353ad83447ac349c6879ab05609e7fa783a;hb=8493b6651af3d2130d5f5f050905cd3d6e8a9c27;hp=ebb78c4fa80b4b659f85797dc0a0d84e83de4bba;hpb=da434ccbc3e0ed843700790cd16c1d4bb5882460;p=deliverable%2Fbinutils-gdb.git

diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h
index ebb78c4fa8..aed10353ad 100644
--- a/gdb/arch/aarch64.h
+++ b/gdb/arch/aarch64.h
@@ -1,6 +1,6 @@
 /* Common target-dependent functionality for AArch64.
 
-   Copyright (C) 2017 Free Software Foundation, Inc.
+   Copyright (C) 2017-2019 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -20,11 +20,18 @@
 #ifndef ARCH_AARCH64_H
 #define ARCH_AARCH64_H
 
-#include "tdesc.h"
+#include "gdbsupport/tdesc.h"
 
-target_desc *aarch64_create_target_description ();
+/* Create the aarch64 target description.  A non zero VQ value indicates both
+   the presence of SVE and the Vector Quotient - the number of 128bit chunks in
+   an SVE Z register.  HAS_PAUTH_P indicates the presence of the PAUTH
+   feature.  */
 
-/* Register numbers of various important registers.  */
+target_desc *aarch64_create_target_description (uint64_t vq, bool has_pauth_p);
+
+/* Register numbers of various important registers.
+   Note that on SVE, the Z registers reuse the V register numbers and the V
+   registers become pseudo registers.  */
 enum aarch64_regnum
 {
   AARCH64_X0_REGNUM,		/* First integer register.  */
@@ -35,8 +42,15 @@ enum aarch64_regnum
   AARCH64_CPSR_REGNUM,		/* Current Program Status Register.  */
   AARCH64_V0_REGNUM,		/* First fp/vec register.  */
   AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31,	/* Last fp/vec register.  */
+  AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM,	/* First SVE Z register.  */
+  AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM,  /* Last SVE Z register.  */
   AARCH64_FPSR_REGNUM,		/* Floating Point Status Register.  */
   AARCH64_FPCR_REGNUM,		/* Floating Point Control Register.  */
+  AARCH64_SVE_P0_REGNUM,	/* First SVE predicate register.  */
+  AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15,	/* Last SVE predicate
+							   register.  */
+  AARCH64_SVE_FFR_REGNUM,	/* SVE First Fault Register.  */
+  AARCH64_SVE_VG_REGNUM,	/* SVE Vector Granule.  */
 
   /* Other useful registers.  */
   AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7,
@@ -44,8 +58,48 @@ enum aarch64_regnum
   AARCH64_LAST_V_ARG_REGNUM = AARCH64_V0_REGNUM + 7
 };
 
+/* Pseudo register base numbers.  */
+#define AARCH64_Q0_REGNUM 0
+#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
+#define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
+#define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
+#define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
+#define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32)
+
+#define AARCH64_PAUTH_DMASK_REGNUM(pauth_reg_base) (pauth_reg_base)
+#define AARCH64_PAUTH_CMASK_REGNUM(pauth_reg_base) (pauth_reg_base + 1)
+#define AARCH64_PAUTH_REGS_SIZE (16)
+
 #define AARCH64_X_REGS_NUM 31
 #define AARCH64_V_REGS_NUM 32
+#define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM
+#define AARCH64_SVE_P_REGS_NUM 16
 #define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1
+#define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1
+
+
+/* There are a number of ways of expressing the current SVE vector size:
+
+   VL : Vector Length.
+	The number of bytes in an SVE Z register.
+   VQ : Vector Quotient.
+	The number of 128bit chunks in an SVE Z register.
+   VG : Vector Granule.
+	The number of 64bit chunks in an SVE Z register.  */
+
+#define sve_vg_from_vl(vl)	((vl) / 8)
+#define sve_vl_from_vg(vg)	((vg) * 8)
+#ifndef sve_vq_from_vl
+#define sve_vq_from_vl(vl)	((vl) / 0x10)
+#endif
+#ifndef sve_vl_from_vq
+#define sve_vl_from_vq(vq)	((vq) * 0x10)
+#endif
+#define sve_vq_from_vg(vg)	(sve_vq_from_vl (sve_vl_from_vg (vg)))
+#define sve_vg_from_vq(vq)	(sve_vg_from_vl (sve_vl_from_vq (vq)))
+
+
+/* Maximum supported VQ value.  Increase if required.  */
+#define AARCH64_MAX_SVE_VQ  16
 
 #endif /* ARCH_AARCH64_H */