X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Farm-tdep.c;h=2bdfa57c2ff018f849fabecacfe44fec996c0505;hb=b268007c68ec2d4ebd7e1fa239f0444ff59620e2;hp=27136e3dc56125e513f8829cf3efd1bd7cbf71d3;hpb=1e1b656356c1a0199bb2da9a63f32d37436b3804;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 27136e3dc5..2bdfa57c2f 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -1,6 +1,6 @@ /* Common target dependent code for GDB on ARM systems. - Copyright (C) 1988-2014 Free Software Foundation, Inc. + Copyright (C) 1988-2017 Free Software Foundation, Inc. This file is part of GDB. @@ -45,6 +45,8 @@ #include "user-regs.h" #include "observer.h" +#include "arch/arm.h" +#include "arch/arm-get-next-pcs.h" #include "arm-tdep.h" #include "gdb/sim-arm.h" @@ -56,14 +58,15 @@ #include "record.h" #include "record-full.h" +#include -#include "features/arm-with-m.c" -#include "features/arm-with-m-fpa-layout.c" -#include "features/arm-with-m-vfp-d16.c" -#include "features/arm-with-iwmmxt.c" -#include "features/arm-with-vfpv2.c" -#include "features/arm-with-vfpv3.c" -#include "features/arm-with-neon.c" +#include "features/arm/arm-with-m.c" +#include "features/arm/arm-with-m-fpa-layout.c" +#include "features/arm/arm-with-m-vfp-d16.c" +#include "features/arm/arm-with-iwmmxt.c" +#include "features/arm/arm-with-vfpv2.c" +#include "features/arm/arm-with-vfpv3.c" +#include "features/arm/arm-with-neon.c" static int arm_debug; @@ -141,13 +144,6 @@ static const char *const arm_mode_strings[] = static const char *arm_fallback_mode_string = "auto"; static const char *arm_force_mode_string = "auto"; -/* Internal override of the execution mode. -1 means no override, - 0 means override to ARM mode, 1 means override to Thumb mode. - The effect is the same as if arm_force_mode has been set by the - user (except the internal override has precedence over a user's - arm_force_mode override). */ -static int arm_override_mode = -1; - /* Number of different reg name sets (options). */ static int num_disassembly_options; @@ -235,7 +231,18 @@ static void arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf); -static int thumb_insn_size (unsigned short inst1); +static CORE_ADDR + arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self); + + +/* get_next_pcs operations. */ +static struct arm_get_next_pcs_ops arm_get_next_pcs_ops = { + arm_get_next_pcs_read_memory_unsigned_integer, + arm_get_next_pcs_syscall_next_pc, + arm_get_next_pcs_addr_bits_remove, + arm_get_next_pcs_is_thumb, + NULL, +}; struct arm_prologue_cache { @@ -267,12 +274,6 @@ static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch, #define DISPLACED_STEPPING_ARCH_VERSION 5 -/* Addresses for calling Thumb functions have the bit 0 set. - Here are some macros to test, set, or clear bit 0 of addresses. */ -#define IS_THUMB_ADDR(addr) ((addr) & 1) -#define MAKE_THUMB_ADDR(addr) ((addr) | 1) -#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) - /* Set to true if the 32-bit mode is in use. */ int arm_apcs_32 = 1; @@ -288,6 +289,19 @@ arm_psr_thumb_bit (struct gdbarch *gdbarch) return CPSR_T; } +/* Determine if the processor is currently executing in Thumb mode. */ + +int +arm_is_thumb (struct regcache *regcache) +{ + ULONGEST cpsr; + ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache)); + + cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM); + + return (cpsr & t_bit) != 0; +} + /* Determine if FRAME is executing in Thumb mode. */ int @@ -333,7 +347,8 @@ arm_find_mapping_symbol (CORE_ADDR memaddr, CORE_ADDR *start) 0 }; unsigned int idx; - data = objfile_data (sec->objfile, arm_objfile_data_key); + data = (struct arm_per_objfile *) objfile_data (sec->objfile, + arm_objfile_data_key); if (data != NULL) { map = data->section_maps[sec->the_bfd_section->index]; @@ -401,10 +416,6 @@ arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) if (IS_THUMB_ADDR (memaddr)) return 1; - /* Respect internal mode override if active. */ - if (arm_override_mode != -1) - return arm_override_mode; - /* If the user wants to override the symbol table, let him. */ if (strcmp (arm_force_mode_string, "arm") == 0) return 0; @@ -443,6 +454,62 @@ arm_pc_is_thumb (struct gdbarch *gdbarch, CORE_ADDR memaddr) return 0; } +/* Determine if the address specified equals any of these magic return + values, called EXC_RETURN, defined by the ARM v6-M and v7-M + architectures. + + From ARMv6-M Reference Manual B1.5.8 + Table B1-5 Exception return behavior + + EXC_RETURN Return To Return Stack + 0xFFFFFFF1 Handler mode Main + 0xFFFFFFF9 Thread mode Main + 0xFFFFFFFD Thread mode Process + + From ARMv7-M Reference Manual B1.5.8 + Table B1-8 EXC_RETURN definition of exception return behavior, no FP + + EXC_RETURN Return To Return Stack + 0xFFFFFFF1 Handler mode Main + 0xFFFFFFF9 Thread mode Main + 0xFFFFFFFD Thread mode Process + + Table B1-9 EXC_RETURN definition of exception return behavior, with + FP + + EXC_RETURN Return To Return Stack Frame Type + 0xFFFFFFE1 Handler mode Main Extended + 0xFFFFFFE9 Thread mode Main Extended + 0xFFFFFFED Thread mode Process Extended + 0xFFFFFFF1 Handler mode Main Basic + 0xFFFFFFF9 Thread mode Main Basic + 0xFFFFFFFD Thread mode Process Basic + + For more details see "B1.5.8 Exception return behavior" + in both ARMv6-M and ARMv7-M Architecture Reference Manuals. */ + +static int +arm_m_addr_is_magic (CORE_ADDR addr) +{ + switch (addr) + { + /* Values from Tables in B1.5.8 the EXC_RETURN definitions of + the exception return behavior. */ + case 0xffffffe1: + case 0xffffffe9: + case 0xffffffed: + case 0xfffffff1: + case 0xfffffff9: + case 0xfffffffd: + /* Address is magic. */ + return 1; + + default: + /* Address is not magic. */ + return 0; + } +} + /* Remove useless bits from addresses in a running program. */ static CORE_ADDR arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) @@ -450,7 +517,7 @@ arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val) /* On M-profile devices, do not strip the low bit from EXC_RETURN (the magic exception return address). */ if (gdbarch_tdep (gdbarch)->is_m - && (val & 0xfffffff0) == 0xfffffff0) + && arm_m_addr_is_magic (val)) return val; if (arm_apcs_32) @@ -484,15 +551,15 @@ skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) /* On soft-float targets, __truncdfsf2 is called to convert promoted arguments to their argument types in non-prototyped functions. */ - if (strncmp (name, "__truncdfsf2", strlen ("__truncdfsf2")) == 0) + if (startswith (name, "__truncdfsf2")) return 1; - if (strncmp (name, "__aeabi_d2f", strlen ("__aeabi_d2f")) == 0) + if (startswith (name, "__aeabi_d2f")) return 1; /* Internal functions related to thread-local storage. */ - if (strncmp (name, "__tls_get_addr", strlen ("__tls_get_addr")) == 0) + if (startswith (name, "__tls_get_addr")) return 1; - if (strncmp (name, "__aeabi_read_tp", strlen ("__aeabi_read_tp")) == 0) + if (startswith (name, "__aeabi_read_tp")) return 1; } else @@ -503,9 +570,9 @@ skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) implementation (this is hand-written ARM assembler in glibc). */ if (!is_thumb - && read_memory_unsigned_integer (pc, 4, byte_order_for_code) + && read_code_unsigned_integer (pc, 4, byte_order_for_code) == 0xe3e00a0f /* mov r0, #0xffff0fff */ - && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code) + && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code) == 0xe240f01f) /* sub pc, r0, #31 */ return 1; } @@ -513,15 +580,6 @@ skip_prologue_function (struct gdbarch *gdbarch, CORE_ADDR pc, int is_thumb) return 0; } -/* Support routines for instruction parsing. */ -#define submask(x) ((1L << ((x) + 1)) - 1) -#define bit(obj,st) (((obj) >> (st)) & 1) -#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) -#define sbits(obj,st,fn) \ - ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) -#define BranchDest(addr,instr) \ - ((CORE_ADDR) (((unsigned long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) - /* Extract the immediate from instruction movw/movt of encoding T. INSN1 is the first 16-bit of instruction, and INSN2 is the second 16-bit of instruction. */ @@ -561,128 +619,6 @@ thumb_expand_immediate (unsigned int imm) return (0x80 | (imm & 0x7f)) << (32 - count); } -/* Return 1 if the 16-bit Thumb instruction INST might change - control flow, 0 otherwise. */ - -static int -thumb_instruction_changes_pc (unsigned short inst) -{ - if ((inst & 0xff00) == 0xbd00) /* pop {rlist, pc} */ - return 1; - - if ((inst & 0xf000) == 0xd000) /* conditional branch */ - return 1; - - if ((inst & 0xf800) == 0xe000) /* unconditional branch */ - return 1; - - if ((inst & 0xff00) == 0x4700) /* bx REG, blx REG */ - return 1; - - if ((inst & 0xff87) == 0x4687) /* mov pc, REG */ - return 1; - - if ((inst & 0xf500) == 0xb100) /* CBNZ or CBZ. */ - return 1; - - return 0; -} - -/* Return 1 if the 32-bit Thumb instruction in INST1 and INST2 - might change control flow, 0 otherwise. */ - -static int -thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2) -{ - if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) - { - /* Branches and miscellaneous control instructions. */ - - if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000) - { - /* B, BL, BLX. */ - return 1; - } - else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00) - { - /* SUBS PC, LR, #imm8. */ - return 1; - } - else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380) - { - /* Conditional branch. */ - return 1; - } - - return 0; - } - - if ((inst1 & 0xfe50) == 0xe810) - { - /* Load multiple or RFE. */ - - if (bit (inst1, 7) && !bit (inst1, 8)) - { - /* LDMIA or POP */ - if (bit (inst2, 15)) - return 1; - } - else if (!bit (inst1, 7) && bit (inst1, 8)) - { - /* LDMDB */ - if (bit (inst2, 15)) - return 1; - } - else if (bit (inst1, 7) && bit (inst1, 8)) - { - /* RFEIA */ - return 1; - } - else if (!bit (inst1, 7) && !bit (inst1, 8)) - { - /* RFEDB */ - return 1; - } - - return 0; - } - - if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00) - { - /* MOV PC or MOVS PC. */ - return 1; - } - - if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000) - { - /* LDR PC. */ - if (bits (inst1, 0, 3) == 15) - return 1; - if (bit (inst1, 7)) - return 1; - if (bit (inst2, 11)) - return 1; - if ((inst2 & 0x0fc0) == 0x0000) - return 1; - - return 0; - } - - if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) - { - /* TBB. */ - return 1; - } - - if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010) - { - /* TBH. */ - return 1; - } - - return 0; -} - /* Return 1 if the 16-bit Thumb instruction INSN restores SP in epilogue, 0 otherwise. */ @@ -723,7 +659,7 @@ thumb_analyze_prologue (struct gdbarch *gdbarch, { unsigned short insn; - insn = read_memory_unsigned_integer (start, 2, byte_order_for_code); + insn = read_code_unsigned_integer (start, 2, byte_order_for_code); if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ { @@ -854,8 +790,8 @@ thumb_analyze_prologue (struct gdbarch *gdbarch, { unsigned short inst2; - inst2 = read_memory_unsigned_integer (start + 2, 2, - byte_order_for_code); + inst2 = read_code_unsigned_integer (start + 2, 2, + byte_order_for_code); if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800) { @@ -1198,25 +1134,27 @@ arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, if (is_thumb) { unsigned short insn1 - = read_memory_unsigned_integer (pc, 2, byte_order_for_code); + = read_code_unsigned_integer (pc, 2, byte_order_for_code); if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */ { *destreg = bits (insn1, 8, 10); *offset = 2; - address = bits (insn1, 0, 7); + address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); + address = read_memory_unsigned_integer (address, 4, + byte_order_for_code); } else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ { unsigned short insn2 - = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); + = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code); low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2); insn1 - = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code); + = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code); insn2 - = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code); + = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code); /* movt Rd, #const */ if ((insn1 & 0xfbc0) == 0xf2c0) @@ -1231,11 +1169,14 @@ arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, else { unsigned int insn - = read_memory_unsigned_integer (pc, 4, byte_order_for_code); + = read_code_unsigned_integer (pc, 4, byte_order_for_code); - if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */ + if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ { - address = bits (insn, 0, 11); + address = bits (insn, 0, 11) + pc + 8; + address = read_memory_unsigned_integer (address, 4, + byte_order_for_code); + *destreg = bits (insn, 12, 15); *offset = 4; } @@ -1244,7 +1185,7 @@ arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, low = EXTRACT_MOVW_MOVT_IMM_A (insn); insn - = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code); + = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code); if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */ { @@ -1306,20 +1247,17 @@ arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) return pc; stack_chk_guard = lookup_minimal_symbol_by_pc (addr); - /* If name of symbol doesn't start with '__stack_chk_guard', this - instruction sequence is not for stack protector. If symbol is - removed, we conservatively think this sequence is for stack protector. */ - if (stack_chk_guard.minsym - && strncmp (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), - "__stack_chk_guard", - strlen ("__stack_chk_guard")) != 0) + /* ADDR must correspond to a symbol whose name is __stack_chk_guard. + Otherwise, this sequence cannot be for stack protector. */ + if (stack_chk_guard.minsym == NULL + || !startswith (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard")) return pc; if (is_thumb) { unsigned int destreg; unsigned short insn - = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code); + = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code); /* Step 2: ldr Rd, [Rn, #immed], encoding T1. */ if ((insn & 0xf800) != 0x6800) @@ -1328,8 +1266,8 @@ arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) return pc; destreg = bits (insn, 0, 2); - insn = read_memory_unsigned_integer (pc + offset + 2, 2, - byte_order_for_code); + insn = read_code_unsigned_integer (pc + offset + 2, 2, + byte_order_for_code); /* Step 3: str Rd, [Rn, #immed], encoding T1. */ if ((insn & 0xf800) != 0x6000) return pc; @@ -1340,7 +1278,7 @@ arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) { unsigned int destreg; unsigned int insn - = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code); + = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code); /* Step 2: ldr Rd, [Rn, #immed], encoding A1. */ if ((insn & 0x0e500000) != 0x04100000) @@ -1349,7 +1287,7 @@ arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) return pc; destreg = bits (insn, 12, 15); /* Step 3: str Rd, [Rn, #immed], encoding A1. */ - insn = read_memory_unsigned_integer (pc + offset + 4, + insn = read_code_unsigned_integer (pc + offset + 4, 4, byte_order_for_code); if ((insn & 0x0e500000) != 0x04000000) return pc; @@ -1382,9 +1320,6 @@ arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) static CORE_ADDR arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) { - enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); - unsigned long inst; - CORE_ADDR skip_pc; CORE_ADDR func_addr, limit_pc; /* See if we can determine the end of the prologue via the symbol table. @@ -1394,7 +1329,7 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) { CORE_ADDR post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); - struct symtab *s = find_pc_symtab (func_addr); + struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); if (post_prologue_pc) post_prologue_pc @@ -1408,10 +1343,10 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) will have producer information for most binaries; if it is missing (e.g. for -gstabs), assuming the GNU tools. */ if (post_prologue_pc - && (s == NULL - || s->producer == NULL - || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0 - || strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) + && (cust == NULL + || COMPUNIT_PRODUCER (cust) == NULL + || startswith (COMPUNIT_PRODUCER (cust), "GNU ") + || startswith (COMPUNIT_PRODUCER (cust), "clang "))) return post_prologue_pc; if (post_prologue_pc != 0) @@ -1456,65 +1391,8 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) /* Check if this is Thumb code. */ if (arm_pc_is_thumb (gdbarch, pc)) return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); - - for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4) - { - inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code); - - /* "mov ip, sp" is no longer a required part of the prologue. */ - if (inst == 0xe1a0c00d) /* mov ip, sp */ - continue; - - if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ - continue; - - if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ - continue; - - /* Some prologues begin with "str lr, [sp, #-4]!". */ - if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ - continue; - - if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ - continue; - - if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ - continue; - - /* Any insns after this point may float into the code, if it makes - for better instruction scheduling, so we skip them only if we - find them, but still consider the function to be frame-ful. */ - - /* We may have either one sfmfd instruction here, or several stfe - insns, depending on the version of floating point code we - support. */ - if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, , [sp]! */ - continue; - - if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ - continue; - - if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ - continue; - - if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ - continue; - - if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */ - || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */ - || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ - continue; - - if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */ - || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */ - || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ - continue; - - /* Un-recognized instruction; stop scanning. */ - break; - } - - return skip_pc; /* End of prologue. */ + else + return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL); } /* *INDENT-OFF* */ @@ -1561,101 +1439,33 @@ thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc, function is. */ return; - prologue_end = min (prologue_end, prev_pc); + prologue_end = std::min (prologue_end, prev_pc); thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); } -/* Return 1 if THIS_INSTR might change control flow, 0 otherwise. */ +/* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 + otherwise. */ static int -arm_instruction_changes_pc (uint32_t this_instr) +arm_instruction_restores_sp (unsigned int insn) { - if (bits (this_instr, 28, 31) == INST_NV) - /* Unconditional instructions. */ - switch (bits (this_instr, 24, 27)) - { - case 0xa: - case 0xb: - /* Branch with Link and change to Thumb. */ - return 1; - case 0xc: - case 0xd: - case 0xe: - /* Coprocessor register transfer. */ - if (bits (this_instr, 12, 15) == 15) - error (_("Invalid update to pc in instruction")); - return 0; - default: - return 0; - } - else - switch (bits (this_instr, 25, 27)) - { - case 0x0: - if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0) - { - /* Multiplies and extra load/stores. */ - if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1) - /* Neither multiplies nor extension load/stores are allowed - to modify PC. */ - return 0; - - /* Otherwise, miscellaneous instructions. */ - - /* BX , BXJ , BLX */ - if (bits (this_instr, 4, 27) == 0x12fff1 - || bits (this_instr, 4, 27) == 0x12fff2 - || bits (this_instr, 4, 27) == 0x12fff3) - return 1; - - /* Other miscellaneous instructions are unpredictable if they - modify PC. */ - return 0; - } - /* Data processing instruction. Fall through. */ - - case 0x1: - if (bits (this_instr, 12, 15) == 15) - return 1; - else - return 0; - - case 0x2: - case 0x3: - /* Media instructions and architecturally undefined instructions. */ - if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1) - return 0; - - /* Stores. */ - if (bit (this_instr, 20) == 0) - return 0; - - /* Loads. */ - if (bits (this_instr, 12, 15) == ARM_PC_REGNUM) - return 1; - else - return 0; - - case 0x4: - /* Load/store multiple. */ - if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1) - return 1; - else - return 0; - - case 0x5: - /* Branch and branch with link. */ + if (bits (insn, 28, 31) != INST_NV) + { + if ((insn & 0x0df0f000) == 0x0080d000 + /* ADD SP (register or immediate). */ + || (insn & 0x0df0f000) == 0x0040d000 + /* SUB SP (register or immediate). */ + || (insn & 0x0ffffff0) == 0x01a0d000 + /* MOV SP. */ + || (insn & 0x0fff0000) == 0x08bd0000 + /* POP (LDMIA). */ + || (insn & 0x0fff0000) == 0x049d0000) + /* POP of a single register. */ return 1; + } - case 0x6: - case 0x7: - /* Coprocessor transfers or SWIs can not affect PC. */ - return 0; - - default: - internal_error (__FILE__, __LINE__, _("bad value in switch")); - } + return 0; } /* Analyze an ARM mode prologue starting at PROLOGUE_START and @@ -1673,14 +1483,12 @@ arm_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, struct arm_prologue_cache *cache) { - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); int regno; CORE_ADDR offset, current_pc; pv_t regs[ARM_FPS_REGNUM]; struct pv_area *stack; struct cleanup *back_to; - int framereg, framesize; CORE_ADDR unrecognized_pc = 0; /* Search the prologue looking for instructions that set up the @@ -1703,7 +1511,7 @@ arm_analyze_prologue (struct gdbarch *gdbarch, current_pc += 4) { unsigned int insn - = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code); + = read_code_unsigned_integer (current_pc, 4, byte_order_for_code); if (insn == 0xe1a0c00d) /* mov ip, sp */ { @@ -1856,6 +1664,11 @@ arm_analyze_prologue (struct gdbarch *gdbarch, else if (arm_instruction_changes_pc (insn)) /* Don't scan past anything that might change control flow. */ break; + else if (arm_instruction_restores_sp (insn)) + { + /* Don't scan past the epilogue. */ + break; + } else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) /* Ignore block loads from the stack, potentially copying @@ -1871,33 +1684,42 @@ arm_analyze_prologue (struct gdbarch *gdbarch, continue; else { - /* The optimizer might shove anything into the prologue, - so we just skip what we don't recognize. */ + /* The optimizer might shove anything into the prologue, if + we build up cache (cache != NULL) from scanning prologue, + we just skip what we don't recognize and scan further to + make cache as complete as possible. However, if we skip + prologue, we'll stop immediately on unrecognized + instruction. */ unrecognized_pc = current_pc; - continue; + if (cache != NULL) + continue; + else + break; } } if (unrecognized_pc == 0) unrecognized_pc = current_pc; - /* The frame size is just the distance from the frame register - to the original stack pointer. */ - if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) - { - /* Frame pointer is fp. */ - framereg = ARM_FP_REGNUM; - framesize = -regs[ARM_FP_REGNUM].k; - } - else - { - /* Try the stack pointer... this is a bit desperate. */ - framereg = ARM_SP_REGNUM; - framesize = -regs[ARM_SP_REGNUM].k; - } - if (cache) { + int framereg, framesize; + + /* The frame size is just the distance from the frame register + to the original stack pointer. */ + if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) + { + /* Frame pointer is fp. */ + framereg = ARM_FP_REGNUM; + framesize = -regs[ARM_FP_REGNUM].k; + } + else + { + /* Try the stack pointer... this is a bit desperate. */ + framereg = ARM_SP_REGNUM; + framesize = -regs[ARM_SP_REGNUM].k; + } + cache->framereg = framereg; cache->framesize = framesize; @@ -1920,14 +1742,9 @@ arm_scan_prologue (struct frame_info *this_frame, { struct gdbarch *gdbarch = get_frame_arch (this_frame); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - int regno; - CORE_ADDR prologue_start, prologue_end, current_pc; + CORE_ADDR prologue_start, prologue_end; CORE_ADDR prev_pc = get_frame_pc (this_frame); CORE_ADDR block_addr = get_frame_address_in_block (this_frame); - pv_t regs[ARM_FPS_REGNUM]; - struct pv_area *stack; - struct cleanup *back_to; - CORE_ADDR offset; /* Assume there is no frame until proven otherwise. */ cache->framereg = ARM_SP_REGNUM; @@ -1990,10 +1807,11 @@ arm_scan_prologue (struct frame_info *this_frame, the callee (or at the present moment if this is the innermost frame). The value stored there should be the address of the stmfd + 8. */ CORE_ADDR frame_loc; - LONGEST return_value; + ULONGEST return_value; frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM); - if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value)) + if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order, + &return_value)) return; else { @@ -2036,6 +1854,31 @@ arm_make_prologue_cache (struct frame_info *this_frame) return cache; } +/* Implementation of the stop_reason hook for arm_prologue frames. */ + +static enum unwind_stop_reason +arm_prologue_unwind_stop_reason (struct frame_info *this_frame, + void **this_cache) +{ + struct arm_prologue_cache *cache; + CORE_ADDR pc; + + if (*this_cache == NULL) + *this_cache = arm_make_prologue_cache (this_frame); + cache = (struct arm_prologue_cache *) *this_cache; + + /* This is meant to halt the backtrace at "_start". */ + pc = get_frame_pc (this_frame); + if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) + return UNWIND_OUTERMOST; + + /* If we've hit a wall, stop. */ + if (cache->prev_sp == 0) + return UNWIND_OUTERMOST; + + return UNWIND_NO_REASON; +} + /* Our frame ID for a normal frame is the current function's starting PC and the caller's SP when we were called. */ @@ -2050,20 +1893,12 @@ arm_prologue_this_id (struct frame_info *this_frame, if (*this_cache == NULL) *this_cache = arm_make_prologue_cache (this_frame); - cache = *this_cache; - - /* This is meant to halt the backtrace at "_start". */ - pc = get_frame_pc (this_frame); - if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc) - return; - - /* If we've hit a wall, stop. */ - if (cache->prev_sp == 0) - return; + cache = (struct arm_prologue_cache *) *this_cache; /* Use function start address as part of the frame ID. If we cannot identify the start address (due to missing symbol information), fall back to just using the current PC. */ + pc = get_frame_pc (this_frame); func = get_frame_func (this_frame); if (!func) func = pc; @@ -2082,7 +1917,7 @@ arm_prologue_prev_register (struct frame_info *this_frame, if (*this_cache == NULL) *this_cache = arm_make_prologue_cache (this_frame); - cache = *this_cache; + cache = (struct arm_prologue_cache *) *this_cache; /* If we are asked to unwind the PC, then we need to return the LR instead. The prologue may save PC, but it will point into this @@ -2132,7 +1967,7 @@ arm_prologue_prev_register (struct frame_info *this_frame, struct frame_unwind arm_prologue_unwind = { NORMAL_FRAME, - default_frame_unwind_stop_reason, + arm_prologue_unwind_stop_reason, arm_prologue_this_id, arm_prologue_prev_register, NULL, @@ -2162,7 +1997,7 @@ struct arm_exidx_data static void arm_exidx_data_free (struct objfile *objfile, void *arg) { - struct arm_exidx_data *data = arg; + struct arm_exidx_data *data = (struct arm_exidx_data *) arg; unsigned int i; for (i = 0; i < objfile->obfd->section_count; i++) @@ -2227,12 +2062,12 @@ arm_exidx_new_objfile (struct objfile *objfile) cleanups = make_cleanup (null_cleanup, NULL); /* Read contents of exception table and index. */ - exidx = bfd_get_section_by_name (objfile->obfd, ".ARM.exidx"); + exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind); if (exidx) { exidx_vma = bfd_section_vma (objfile->obfd, exidx); exidx_size = bfd_get_section_size (exidx); - exidx_data = xmalloc (exidx_size); + exidx_data = (gdb_byte *) xmalloc (exidx_size); make_cleanup (xfree, exidx_data); if (!bfd_get_section_contents (objfile->obfd, exidx, @@ -2248,7 +2083,7 @@ arm_exidx_new_objfile (struct objfile *objfile) { extab_vma = bfd_section_vma (objfile->obfd, extab); extab_size = bfd_get_section_size (extab); - extab_data = xmalloc (extab_size); + extab_data = (gdb_byte *) xmalloc (extab_size); make_cleanup (xfree, extab_data); if (!bfd_get_section_contents (objfile->obfd, extab, @@ -2385,8 +2220,9 @@ arm_exidx_new_objfile (struct objfile *objfile) extab section starting at ADDR. */ if (n_bytes || n_words) { - gdb_byte *p = entry = obstack_alloc (&objfile->objfile_obstack, - n_bytes + n_words * 4 + 1); + gdb_byte *p = entry + = (gdb_byte *) obstack_alloc (&objfile->objfile_obstack, + n_bytes + n_words * 4 + 1); while (n_bytes--) *p++ = (gdb_byte) ((word >> (8 * n_bytes)) & 0xff); @@ -2436,7 +2272,8 @@ arm_find_exidx_entry (CORE_ADDR memaddr, CORE_ADDR *start) struct arm_exidx_entry map_key = { memaddr - obj_section_addr (sec), 0 }; unsigned int idx; - data = objfile_data (sec->objfile, arm_exidx_data_key); + data = ((struct arm_exidx_data *) + objfile_data (sec->objfile, arm_exidx_data_key)); if (data != NULL) { map = data->section_maps[sec->the_bfd_section->index]; @@ -2823,19 +2660,19 @@ arm_exidx_unwind_sniffer (const struct frame_unwind *self, ensure this, so that e.g. pthread cancellation works. */ if (arm_frame_is_thumb (this_frame)) { - LONGEST insn; + ULONGEST insn; - if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2, - byte_order_for_code, &insn) + if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2, + 2, byte_order_for_code, &insn) && (insn & 0xff00) == 0xdf00 /* svc */) exc_valid = 1; } else { - LONGEST insn; + ULONGEST insn; - if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4, - byte_order_for_code, &insn) + if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4, + 4, byte_order_for_code, &insn) && (insn & 0x0f000000) == 0x0f000000 /* svc */) exc_valid = 1; } @@ -2879,25 +2716,127 @@ struct frame_unwind arm_exidx_unwind = { arm_exidx_unwind_sniffer }; -/* Recognize GCC's trampoline for thumb call-indirect. If we are in a - trampoline, return the target PC. Otherwise return 0. +static struct arm_prologue_cache * +arm_make_epilogue_frame_cache (struct frame_info *this_frame) +{ + struct arm_prologue_cache *cache; + int reg; - void call0a (char c, short s, int i, long l) {} + cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); + cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); - int main (void) - { - (*pointer_to_call0a) (c, s, i, l); - } + /* Still rely on the offset calculated from prologue. */ + arm_scan_prologue (this_frame, cache); - Instead of calling a stub library function _call_via_xx (xx is - the register name), GCC may inline the trampoline in the object - file as below (register r2 has the address of call0a). + /* Since we are in epilogue, the SP has been restored. */ + cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); - .global main - .type main, %function - ... - bl .L1 - ... + /* Calculate actual addresses of saved registers using offsets + determined by arm_scan_prologue. */ + for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) + if (trad_frame_addr_p (cache->saved_regs, reg)) + cache->saved_regs[reg].addr += cache->prev_sp; + + return cache; +} + +/* Implementation of function hook 'this_id' in + 'struct frame_uwnind' for epilogue unwinder. */ + +static void +arm_epilogue_frame_this_id (struct frame_info *this_frame, + void **this_cache, + struct frame_id *this_id) +{ + struct arm_prologue_cache *cache; + CORE_ADDR pc, func; + + if (*this_cache == NULL) + *this_cache = arm_make_epilogue_frame_cache (this_frame); + cache = (struct arm_prologue_cache *) *this_cache; + + /* Use function start address as part of the frame ID. If we cannot + identify the start address (due to missing symbol information), + fall back to just using the current PC. */ + pc = get_frame_pc (this_frame); + func = get_frame_func (this_frame); + if (func == 0) + func = pc; + + (*this_id) = frame_id_build (cache->prev_sp, pc); +} + +/* Implementation of function hook 'prev_register' in + 'struct frame_uwnind' for epilogue unwinder. */ + +static struct value * +arm_epilogue_frame_prev_register (struct frame_info *this_frame, + void **this_cache, int regnum) +{ + if (*this_cache == NULL) + *this_cache = arm_make_epilogue_frame_cache (this_frame); + + return arm_prologue_prev_register (this_frame, this_cache, regnum); +} + +static int arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, + CORE_ADDR pc); +static int thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, + CORE_ADDR pc); + +/* Implementation of function hook 'sniffer' in + 'struct frame_uwnind' for epilogue unwinder. */ + +static int +arm_epilogue_frame_sniffer (const struct frame_unwind *self, + struct frame_info *this_frame, + void **this_prologue_cache) +{ + if (frame_relative_level (this_frame) == 0) + { + struct gdbarch *gdbarch = get_frame_arch (this_frame); + CORE_ADDR pc = get_frame_pc (this_frame); + + if (arm_frame_is_thumb (this_frame)) + return thumb_stack_frame_destroyed_p (gdbarch, pc); + else + return arm_stack_frame_destroyed_p_1 (gdbarch, pc); + } + else + return 0; +} + +/* Frame unwinder from epilogue. */ + +static const struct frame_unwind arm_epilogue_frame_unwind = +{ + NORMAL_FRAME, + default_frame_unwind_stop_reason, + arm_epilogue_frame_this_id, + arm_epilogue_frame_prev_register, + NULL, + arm_epilogue_frame_sniffer, +}; + +/* Recognize GCC's trampoline for thumb call-indirect. If we are in a + trampoline, return the target PC. Otherwise return 0. + + void call0a (char c, short s, int i, long l) {} + + int main (void) + { + (*pointer_to_call0a) (c, s, i, l); + } + + Instead of calling a stub library function _call_via_xx (xx is + the register name), GCC may inline the trampoline in the object + file as below (register r2 has the address of call0a). + + .global main + .type main, %function + ... + bl .L1 + ... .size main, .-main .L1: @@ -2961,7 +2900,7 @@ arm_stub_this_id (struct frame_info *this_frame, if (*this_cache == NULL) *this_cache = arm_make_stub_cache (this_frame); - cache = *this_cache; + cache = (struct arm_prologue_cache *) *this_cache; *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame)); } @@ -3055,7 +2994,7 @@ arm_m_exception_this_id (struct frame_info *this_frame, if (*this_cache == NULL) *this_cache = arm_m_exception_cache (this_frame); - cache = *this_cache; + cache = (struct arm_prologue_cache *) *this_cache; /* Our frame ID for a stub frame is the current SP and LR. */ *this_id = frame_id_build (cache->prev_sp, @@ -3070,12 +3009,11 @@ arm_m_exception_prev_register (struct frame_info *this_frame, void **this_cache, int prev_regnum) { - struct gdbarch *gdbarch = get_frame_arch (this_frame); struct arm_prologue_cache *cache; if (*this_cache == NULL) *this_cache = arm_m_exception_cache (this_frame); - cache = *this_cache; + cache = (struct arm_prologue_cache *) *this_cache; /* The value was already reconstructed into PREV_SP. */ if (prev_regnum == ARM_SP_REGNUM) @@ -3099,14 +3037,8 @@ arm_m_exception_unwind_sniffer (const struct frame_unwind *self, /* No need to check is_m; this sniffer is only registered for M-profile architectures. */ - /* Exception frames return to one of these magic PCs. Other values - are not defined as of v7-M. See details in "B1.5.8 Exception - return behavior" in "ARMv7-M Architecture Reference Manual". */ - if (this_pc == 0xfffffff1 || this_pc == 0xfffffff9 - || this_pc == 0xfffffffd) - return 1; - - return 0; + /* Check if exception frame returns to a magic PC value. */ + return arm_m_addr_is_magic (this_pc); } /* Frame unwinder for M-profile exceptions. */ @@ -3128,7 +3060,7 @@ arm_normal_frame_base (struct frame_info *this_frame, void **this_cache) if (*this_cache == NULL) *this_cache = arm_make_prologue_cache (this_frame); - cache = *this_cache; + cache = (struct arm_prologue_cache *) *this_cache; return cache->prev_sp - cache->framesize; } @@ -3225,11 +3157,10 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, } } -/* Return true if we are in the function's epilogue, i.e. after the - instruction that destroyed the function's stack frame. */ +/* Implement the stack_frame_destroyed_p gdbarch method. */ static int -thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) +thumb_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) { enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned int insn, insn2; @@ -3273,7 +3204,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) found_return = 1; else if (thumb_instruction_restores_sp (insn)) { - if ((insn & 0xfe00) == 0xbd00) /* pop */ + if ((insn & 0xff00) == 0xbd00) /* pop */ found_return = 1; } else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ @@ -3336,20 +3267,14 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) return found_stack_adjust; } -/* Return true if we are in the function's epilogue, i.e. after the - instruction that destroyed the function's stack frame. */ - static int -arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) +arm_stack_frame_destroyed_p_1 (struct gdbarch *gdbarch, CORE_ADDR pc) { enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned int insn; - int found_return, found_stack_adjust; + int found_return; CORE_ADDR func_start, func_end; - if (arm_pc_is_thumb (gdbarch, pc)) - return thumb_in_function_epilogue_p (gdbarch, pc); - if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) return 0; @@ -3384,33 +3309,23 @@ arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) if (pc < func_start + 4) return 0; - found_stack_adjust = 0; insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); - if (bits (insn, 28, 31) != INST_NV) - { - if ((insn & 0x0df0f000) == 0x0080d000) - /* ADD SP (register or immediate). */ - found_stack_adjust = 1; - else if ((insn & 0x0df0f000) == 0x0040d000) - /* SUB SP (register or immediate). */ - found_stack_adjust = 1; - else if ((insn & 0x0ffffff0) == 0x01a0d000) - /* MOV SP. */ - found_stack_adjust = 1; - else if ((insn & 0x0fff0000) == 0x08bd0000) - /* POP (LDMIA). */ - found_stack_adjust = 1; - else if ((insn & 0x0fff0000) == 0x049d0000) - /* POP of a single register. */ - found_stack_adjust = 1; - } - - if (found_stack_adjust) + if (arm_instruction_restores_sp (insn)) return 1; return 0; } +/* Implement the stack_frame_destroyed_p gdbarch method. */ + +static int +arm_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) +{ + if (arm_pc_is_thumb (gdbarch, pc)) + return thumb_stack_frame_destroyed_p (gdbarch, pc); + else + return arm_stack_frame_destroyed_p_1 (gdbarch, pc); +} /* When arguments must be pushed onto the stack, they go on in reverse order. The code below implements a FILO (stack) to do this. */ @@ -3419,15 +3334,15 @@ struct stack_item { int len; struct stack_item *prev; - void *data; + gdb_byte *data; }; static struct stack_item * -push_stack_item (struct stack_item *prev, const void *contents, int len) +push_stack_item (struct stack_item *prev, const gdb_byte *contents, int len) { struct stack_item *si; - si = xmalloc (sizeof (struct stack_item)); - si->data = xmalloc (len); + si = XNEW (struct stack_item); + si->data = (gdb_byte *) xmalloc (len); si->len = len; si->prev = prev; memcpy (si->data, contents, len); @@ -3474,8 +3389,18 @@ arm_type_align (struct type *t) return TYPE_LENGTH (t); case TYPE_CODE_ARRAY: + if (TYPE_VECTOR (t)) + { + /* Use the natural alignment for vector types (the same for + scalar type), but the maximum alignment is 64-bit. */ + if (TYPE_LENGTH (t) > 8) + return 8; + else + return TYPE_LENGTH (t); + } + else + return arm_type_align (TYPE_TARGET_TYPE (t)); case TYPE_CODE_COMPLEX: - /* TODO: What about vector types? */ return arm_type_align (TYPE_TARGET_TYPE (t)); case TYPE_CODE_STRUCT: @@ -3622,21 +3547,44 @@ arm_vfp_cprc_sub_candidate (struct type *t, case TYPE_CODE_ARRAY: { - int count; - unsigned unitlen; - count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), base_type); - if (count == -1) - return -1; - if (TYPE_LENGTH (t) == 0) + if (TYPE_VECTOR (t)) { - gdb_assert (count == 0); - return 0; + /* A 64-bit or 128-bit containerized vector type are VFP + CPRCs. */ + switch (TYPE_LENGTH (t)) + { + case 8: + if (*base_type == VFP_CPRC_UNKNOWN) + *base_type = VFP_CPRC_VEC64; + return 1; + case 16: + if (*base_type == VFP_CPRC_UNKNOWN) + *base_type = VFP_CPRC_VEC128; + return 1; + default: + return -1; + } + } + else + { + int count; + unsigned unitlen; + + count = arm_vfp_cprc_sub_candidate (TYPE_TARGET_TYPE (t), + base_type); + if (count == -1) + return -1; + if (TYPE_LENGTH (t) == 0) + { + gdb_assert (count == 0); + return 0; + } + else if (count == 0) + return -1; + unitlen = arm_vfp_cprc_unit_length (*base_type); + gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); + return TYPE_LENGTH (t) / unitlen; } - else if (count == 0) - return -1; - unitlen = arm_vfp_cprc_unit_length (*base_type); - gdb_assert ((TYPE_LENGTH (t) % unitlen) == 0); - return TYPE_LENGTH (t) / unitlen; } break; @@ -3647,8 +3595,11 @@ arm_vfp_cprc_sub_candidate (struct type *t, int i; for (i = 0; i < TYPE_NFIELDS (t); i++) { - int sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), - base_type); + int sub_count = 0; + + if (!field_is_static (&TYPE_FIELD (t, i))) + sub_count = arm_vfp_cprc_sub_candidate (TYPE_FIELD_TYPE (t, i), + base_type); if (sub_count == -1) return -1; count += sub_count; @@ -3907,7 +3858,7 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, CORE_ADDR regval = extract_unsigned_integer (val, len, byte_order); if (arm_pc_is_thumb (gdbarch, regval)) { - bfd_byte *copy = alloca (len); + bfd_byte *copy = (bfd_byte *) alloca (len); store_unsigned_integer (copy, len, byte_order, MAKE_THUMB_ADDR (regval)); val = copy; @@ -3920,13 +3871,13 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, while (len > 0) { int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE; + CORE_ADDR regval + = extract_unsigned_integer (val, partial_len, byte_order); if (may_use_core_reg && argreg <= ARM_LAST_ARG_REGNUM) { /* The argument is being passed in a general purpose register. */ - CORE_ADDR regval - = extract_unsigned_integer (val, partial_len, byte_order); if (byte_order == BFD_ENDIAN_BIG) regval <<= (INT_REGISTER_SIZE - partial_len) * 8; if (arm_debug) @@ -3940,11 +3891,16 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function, } else { + gdb_byte buf[INT_REGISTER_SIZE]; + + memset (buf, 0, sizeof (buf)); + store_unsigned_integer (buf, partial_len, byte_order, regval); + /* Push the arguments onto the stack. */ if (arm_debug) fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n", argnum, nstack); - si = push_stack_item (si, val, INT_REGISTER_SIZE); + si = push_stack_item (si, buf, INT_REGISTER_SIZE); nstack += INT_REGISTER_SIZE; } @@ -4147,1188 +4103,137 @@ arm_register_type (struct gdbarch *gdbarch, int regnum) else if (regnum == ARM_PC_REGNUM) return builtin_type (gdbarch)->builtin_func_ptr; else if (regnum >= ARRAY_SIZE (arm_register_names)) - /* These registers are only supported on targets which supply - an XML description. */ - return builtin_type (gdbarch)->builtin_int0; - else - return builtin_type (gdbarch)->builtin_uint32; -} - -/* Map a DWARF register REGNUM onto the appropriate GDB register - number. */ - -static int -arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) -{ - /* Core integer regs. */ - if (reg >= 0 && reg <= 15) - return reg; - - /* Legacy FPA encoding. These were once used in a way which - overlapped with VFP register numbering, so their use is - discouraged, but GDB doesn't support the ARM toolchain - which used them for VFP. */ - if (reg >= 16 && reg <= 23) - return ARM_F0_REGNUM + reg - 16; - - /* New assignments for the FPA registers. */ - if (reg >= 96 && reg <= 103) - return ARM_F0_REGNUM + reg - 96; - - /* WMMX register assignments. */ - if (reg >= 104 && reg <= 111) - return ARM_WCGR0_REGNUM + reg - 104; - - if (reg >= 112 && reg <= 127) - return ARM_WR0_REGNUM + reg - 112; - - if (reg >= 192 && reg <= 199) - return ARM_WC0_REGNUM + reg - 192; - - /* VFP v2 registers. A double precision value is actually - in d1 rather than s2, but the ABI only defines numbering - for the single precision registers. This will "just work" - in GDB for little endian targets (we'll read eight bytes, - starting in s0 and then progressing to s1), but will be - reversed on big endian targets with VFP. This won't - be a problem for the new Neon quad registers; you're supposed - to use DW_OP_piece for those. */ - if (reg >= 64 && reg <= 95) - { - char name_buf[4]; - - xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); - return user_reg_map_name_to_regnum (gdbarch, name_buf, - strlen (name_buf)); - } - - /* VFP v3 / Neon registers. This range is also used for VFP v2 - registers, except that it now describes d0 instead of s0. */ - if (reg >= 256 && reg <= 287) - { - char name_buf[4]; - - xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); - return user_reg_map_name_to_regnum (gdbarch, name_buf, - strlen (name_buf)); - } - - return -1; -} - -/* Map GDB internal REGNUM onto the Arm simulator register numbers. */ -static int -arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) -{ - int reg = regnum; - gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); - - if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) - return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; - - if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) - return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; - - if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) - return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; - - if (reg < NUM_GREGS) - return SIM_ARM_R0_REGNUM + reg; - reg -= NUM_GREGS; - - if (reg < NUM_FREGS) - return SIM_ARM_FP0_REGNUM + reg; - reg -= NUM_FREGS; - - if (reg < NUM_SREGS) - return SIM_ARM_FPS_REGNUM + reg; - reg -= NUM_SREGS; - - internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); -} - -/* NOTE: cagney/2001-08-20: Both convert_from_extended() and - convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. - It is thought that this is is the floating-point register format on - little-endian systems. */ - -static void -convert_from_extended (const struct floatformat *fmt, const void *ptr, - void *dbl, int endianess) -{ - DOUBLEST d; - - if (endianess == BFD_ENDIAN_BIG) - floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); - else - floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, - ptr, &d); - floatformat_from_doublest (fmt, &d, dbl); -} - -static void -convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, - int endianess) -{ - DOUBLEST d; - - floatformat_to_doublest (fmt, ptr, &d); - if (endianess == BFD_ENDIAN_BIG) - floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); - else - floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, - &d, dbl); -} - -static int -condition_true (unsigned long cond, unsigned long status_reg) -{ - if (cond == INST_AL || cond == INST_NV) - return 1; - - switch (cond) - { - case INST_EQ: - return ((status_reg & FLAG_Z) != 0); - case INST_NE: - return ((status_reg & FLAG_Z) == 0); - case INST_CS: - return ((status_reg & FLAG_C) != 0); - case INST_CC: - return ((status_reg & FLAG_C) == 0); - case INST_MI: - return ((status_reg & FLAG_N) != 0); - case INST_PL: - return ((status_reg & FLAG_N) == 0); - case INST_VS: - return ((status_reg & FLAG_V) != 0); - case INST_VC: - return ((status_reg & FLAG_V) == 0); - case INST_HI: - return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); - case INST_LS: - return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); - case INST_GE: - return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); - case INST_LT: - return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); - case INST_GT: - return (((status_reg & FLAG_Z) == 0) - && (((status_reg & FLAG_N) == 0) - == ((status_reg & FLAG_V) == 0))); - case INST_LE: - return (((status_reg & FLAG_Z) != 0) - || (((status_reg & FLAG_N) == 0) - != ((status_reg & FLAG_V) == 0))); - } - return 1; -} - -static unsigned long -shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, - unsigned long pc_val, unsigned long status_reg) -{ - unsigned long res, shift; - int rm = bits (inst, 0, 3); - unsigned long shifttype = bits (inst, 5, 6); - - if (bit (inst, 4)) - { - int rs = bits (inst, 8, 11); - shift = (rs == 15 ? pc_val + 8 - : get_frame_register_unsigned (frame, rs)) & 0xFF; - } - else - shift = bits (inst, 7, 11); - - res = (rm == ARM_PC_REGNUM - ? (pc_val + (bit (inst, 4) ? 12 : 8)) - : get_frame_register_unsigned (frame, rm)); - - switch (shifttype) - { - case 0: /* LSL */ - res = shift >= 32 ? 0 : res << shift; - break; - - case 1: /* LSR */ - res = shift >= 32 ? 0 : res >> shift; - break; - - case 2: /* ASR */ - if (shift >= 32) - shift = 31; - res = ((res & 0x80000000L) - ? ~((~res) >> shift) : res >> shift); - break; - - case 3: /* ROR/RRX */ - shift &= 31; - if (shift == 0) - res = (res >> 1) | (carry ? 0x80000000L : 0); - else - res = (res >> shift) | (res << (32 - shift)); - break; - } - - return res & 0xffffffff; -} - -/* Return number of 1-bits in VAL. */ - -static int -bitcount (unsigned long val) -{ - int nbits; - for (nbits = 0; val != 0; nbits++) - val &= val - 1; /* Delete rightmost 1-bit in val. */ - return nbits; -} - -/* Return the size in bytes of the complete Thumb instruction whose - first halfword is INST1. */ - -static int -thumb_insn_size (unsigned short inst1) -{ - if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0) - return 4; - else - return 2; -} - -static int -thumb_advance_itstate (unsigned int itstate) -{ - /* Preserve IT[7:5], the first three bits of the condition. Shift - the upcoming condition flags left by one bit. */ - itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f); - - /* If we have finished the IT block, clear the state. */ - if ((itstate & 0x0f) == 0) - itstate = 0; - - return itstate; -} - -/* Find the next PC after the current instruction executes. In some - cases we can not statically determine the answer (see the IT state - handling in this function); in that case, a breakpoint may be - inserted in addition to the returned PC, which will be used to set - another breakpoint by our caller. */ - -static CORE_ADDR -thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc) -{ - struct gdbarch *gdbarch = get_frame_arch (frame); - struct address_space *aspace = get_frame_address_space (frame); - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); - unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ - unsigned short inst1; - CORE_ADDR nextpc = pc + 2; /* Default is next instruction. */ - unsigned long offset; - ULONGEST status, itstate; - - nextpc = MAKE_THUMB_ADDR (nextpc); - pc_val = MAKE_THUMB_ADDR (pc_val); - - inst1 = read_memory_unsigned_integer (pc, 2, byte_order_for_code); - - /* Thumb-2 conditional execution support. There are eight bits in - the CPSR which describe conditional execution state. Once - reconstructed (they're in a funny order), the low five bits - describe the low bit of the condition for each instruction and - how many instructions remain. The high three bits describe the - base condition. One of the low four bits will be set if an IT - block is active. These bits read as zero on earlier - processors. */ - status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); - itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3); - - /* If-Then handling. On GNU/Linux, where this routine is used, we - use an undefined instruction as a breakpoint. Unlike BKPT, IT - can disable execution of the undefined instruction. So we might - miss the breakpoint if we set it on a skipped conditional - instruction. Because conditional instructions can change the - flags, affecting the execution of further instructions, we may - need to set two breakpoints. */ - - if (gdbarch_tdep (gdbarch)->thumb2_breakpoint != NULL) - { - if ((inst1 & 0xff00) == 0xbf00 && (inst1 & 0x000f) != 0) - { - /* An IT instruction. Because this instruction does not - modify the flags, we can accurately predict the next - executed instruction. */ - itstate = inst1 & 0x00ff; - pc += thumb_insn_size (inst1); - - while (itstate != 0 && ! condition_true (itstate >> 4, status)) - { - inst1 = read_memory_unsigned_integer (pc, 2, - byte_order_for_code); - pc += thumb_insn_size (inst1); - itstate = thumb_advance_itstate (itstate); - } - - return MAKE_THUMB_ADDR (pc); - } - else if (itstate != 0) - { - /* We are in a conditional block. Check the condition. */ - if (! condition_true (itstate >> 4, status)) - { - /* Advance to the next executed instruction. */ - pc += thumb_insn_size (inst1); - itstate = thumb_advance_itstate (itstate); - - while (itstate != 0 && ! condition_true (itstate >> 4, status)) - { - inst1 = read_memory_unsigned_integer (pc, 2, - byte_order_for_code); - pc += thumb_insn_size (inst1); - itstate = thumb_advance_itstate (itstate); - } - - return MAKE_THUMB_ADDR (pc); - } - else if ((itstate & 0x0f) == 0x08) - { - /* This is the last instruction of the conditional - block, and it is executed. We can handle it normally - because the following instruction is not conditional, - and we must handle it normally because it is - permitted to branch. Fall through. */ - } - else - { - int cond_negated; - - /* There are conditional instructions after this one. - If this instruction modifies the flags, then we can - not predict what the next executed instruction will - be. Fortunately, this instruction is architecturally - forbidden to branch; we know it will fall through. - Start by skipping past it. */ - pc += thumb_insn_size (inst1); - itstate = thumb_advance_itstate (itstate); - - /* Set a breakpoint on the following instruction. */ - gdb_assert ((itstate & 0x0f) != 0); - arm_insert_single_step_breakpoint (gdbarch, aspace, - MAKE_THUMB_ADDR (pc)); - cond_negated = (itstate >> 4) & 1; - - /* Skip all following instructions with the same - condition. If there is a later instruction in the IT - block with the opposite condition, set the other - breakpoint there. If not, then set a breakpoint on - the instruction after the IT block. */ - do - { - inst1 = read_memory_unsigned_integer (pc, 2, - byte_order_for_code); - pc += thumb_insn_size (inst1); - itstate = thumb_advance_itstate (itstate); - } - while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated); - - return MAKE_THUMB_ADDR (pc); - } - } - } - else if (itstate & 0x0f) - { - /* We are in a conditional block. Check the condition. */ - int cond = itstate >> 4; - - if (! condition_true (cond, status)) - /* Advance to the next instruction. All the 32-bit - instructions share a common prefix. */ - return MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1)); - - /* Otherwise, handle the instruction normally. */ - } - - if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ - { - CORE_ADDR sp; - - /* Fetch the saved PC from the stack. It's stored above - all of the other registers. */ - offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE; - sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); - nextpc = read_memory_unsigned_integer (sp + offset, 4, byte_order); - } - else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ - { - unsigned long cond = bits (inst1, 8, 11); - if (cond == 0x0f) /* 0x0f = SWI */ - { - struct gdbarch_tdep *tdep; - tdep = gdbarch_tdep (gdbarch); - - if (tdep->syscall_next_pc != NULL) - nextpc = tdep->syscall_next_pc (frame); - - } - else if (cond != 0x0f && condition_true (cond, status)) - nextpc = pc_val + (sbits (inst1, 0, 7) << 1); - } - else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ - { - nextpc = pc_val + (sbits (inst1, 0, 10) << 1); - } - else if (thumb_insn_size (inst1) == 4) /* 32-bit instruction */ - { - unsigned short inst2; - inst2 = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code); - - /* Default to the next instruction. */ - nextpc = pc + 4; - nextpc = MAKE_THUMB_ADDR (nextpc); - - if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000) - { - /* Branches and miscellaneous control instructions. */ - - if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000) - { - /* B, BL, BLX. */ - int j1, j2, imm1, imm2; - - imm1 = sbits (inst1, 0, 10); - imm2 = bits (inst2, 0, 10); - j1 = bit (inst2, 13); - j2 = bit (inst2, 11); - - offset = ((imm1 << 12) + (imm2 << 1)); - offset ^= ((!j2) << 22) | ((!j1) << 23); - - nextpc = pc_val + offset; - /* For BLX make sure to clear the low bits. */ - if (bit (inst2, 12) == 0) - nextpc = nextpc & 0xfffffffc; - } - else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00) - { - /* SUBS PC, LR, #imm8. */ - nextpc = get_frame_register_unsigned (frame, ARM_LR_REGNUM); - nextpc -= inst2 & 0x00ff; - } - else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380) - { - /* Conditional branch. */ - if (condition_true (bits (inst1, 6, 9), status)) - { - int sign, j1, j2, imm1, imm2; - - sign = sbits (inst1, 10, 10); - imm1 = bits (inst1, 0, 5); - imm2 = bits (inst2, 0, 10); - j1 = bit (inst2, 13); - j2 = bit (inst2, 11); - - offset = (sign << 20) + (j2 << 19) + (j1 << 18); - offset += (imm1 << 12) + (imm2 << 1); - - nextpc = pc_val + offset; - } - } - } - else if ((inst1 & 0xfe50) == 0xe810) - { - /* Load multiple or RFE. */ - int rn, offset, load_pc = 1; - - rn = bits (inst1, 0, 3); - if (bit (inst1, 7) && !bit (inst1, 8)) - { - /* LDMIA or POP */ - if (!bit (inst2, 15)) - load_pc = 0; - offset = bitcount (inst2) * 4 - 4; - } - else if (!bit (inst1, 7) && bit (inst1, 8)) - { - /* LDMDB */ - if (!bit (inst2, 15)) - load_pc = 0; - offset = -4; - } - else if (bit (inst1, 7) && bit (inst1, 8)) - { - /* RFEIA */ - offset = 0; - } - else if (!bit (inst1, 7) && !bit (inst1, 8)) - { - /* RFEDB */ - offset = -8; - } - else - load_pc = 0; - - if (load_pc) - { - CORE_ADDR addr = get_frame_register_unsigned (frame, rn); - nextpc = get_frame_memory_unsigned (frame, addr + offset, 4); - } - } - else if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00) - { - /* MOV PC or MOVS PC. */ - nextpc = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); - nextpc = MAKE_THUMB_ADDR (nextpc); - } - else if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000) - { - /* LDR PC. */ - CORE_ADDR base; - int rn, load_pc = 1; - - rn = bits (inst1, 0, 3); - base = get_frame_register_unsigned (frame, rn); - if (rn == ARM_PC_REGNUM) - { - base = (base + 4) & ~(CORE_ADDR) 0x3; - if (bit (inst1, 7)) - base += bits (inst2, 0, 11); - else - base -= bits (inst2, 0, 11); - } - else if (bit (inst1, 7)) - base += bits (inst2, 0, 11); - else if (bit (inst2, 11)) - { - if (bit (inst2, 10)) - { - if (bit (inst2, 9)) - base += bits (inst2, 0, 7); - else - base -= bits (inst2, 0, 7); - } - } - else if ((inst2 & 0x0fc0) == 0x0000) - { - int shift = bits (inst2, 4, 5), rm = bits (inst2, 0, 3); - base += get_frame_register_unsigned (frame, rm) << shift; - } - else - /* Reserved. */ - load_pc = 0; - - if (load_pc) - nextpc = get_frame_memory_unsigned (frame, base, 4); - } - else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000) - { - /* TBB. */ - CORE_ADDR tbl_reg, table, offset, length; - - tbl_reg = bits (inst1, 0, 3); - if (tbl_reg == 0x0f) - table = pc + 4; /* Regcache copy of PC isn't right yet. */ - else - table = get_frame_register_unsigned (frame, tbl_reg); - - offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3)); - length = 2 * get_frame_memory_unsigned (frame, table + offset, 1); - nextpc = pc_val + length; - } - else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010) - { - /* TBH. */ - CORE_ADDR tbl_reg, table, offset, length; - - tbl_reg = bits (inst1, 0, 3); - if (tbl_reg == 0x0f) - table = pc + 4; /* Regcache copy of PC isn't right yet. */ - else - table = get_frame_register_unsigned (frame, tbl_reg); - - offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3)); - length = 2 * get_frame_memory_unsigned (frame, table + offset, 2); - nextpc = pc_val + length; - } - } - else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */ - { - if (bits (inst1, 3, 6) == 0x0f) - nextpc = UNMAKE_THUMB_ADDR (pc_val); - else - nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); - } - else if ((inst1 & 0xff87) == 0x4687) /* mov pc, REG */ - { - if (bits (inst1, 3, 6) == 0x0f) - nextpc = pc_val; - else - nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6)); - - nextpc = MAKE_THUMB_ADDR (nextpc); - } - else if ((inst1 & 0xf500) == 0xb100) - { - /* CBNZ or CBZ. */ - int imm = (bit (inst1, 9) << 6) + (bits (inst1, 3, 7) << 1); - ULONGEST reg = get_frame_register_unsigned (frame, bits (inst1, 0, 2)); - - if (bit (inst1, 11) && reg != 0) - nextpc = pc_val + imm; - else if (!bit (inst1, 11) && reg == 0) - nextpc = pc_val + imm; - } - return nextpc; -} - -/* Get the raw next address. PC is the current program counter, in - FRAME, which is assumed to be executing in ARM mode. - - The value returned has the execution state of the next instruction - encoded in it. Use IS_THUMB_ADDR () to see whether the instruction is - in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory - address. */ - -static CORE_ADDR -arm_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc) -{ - struct gdbarch *gdbarch = get_frame_arch (frame); - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); - unsigned long pc_val; - unsigned long this_instr; - unsigned long status; - CORE_ADDR nextpc; - - pc_val = (unsigned long) pc; - this_instr = read_memory_unsigned_integer (pc, 4, byte_order_for_code); - - status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); - nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ - - if (bits (this_instr, 28, 31) == INST_NV) - switch (bits (this_instr, 24, 27)) - { - case 0xa: - case 0xb: - { - /* Branch with Link and change to Thumb. */ - nextpc = BranchDest (pc, this_instr); - nextpc |= bit (this_instr, 24) << 1; - nextpc = MAKE_THUMB_ADDR (nextpc); - break; - } - case 0xc: - case 0xd: - case 0xe: - /* Coprocessor register transfer. */ - if (bits (this_instr, 12, 15) == 15) - error (_("Invalid update to pc in instruction")); - break; - } - else if (condition_true (bits (this_instr, 28, 31), status)) - { - switch (bits (this_instr, 24, 27)) - { - case 0x0: - case 0x1: /* data processing */ - case 0x2: - case 0x3: - { - unsigned long operand1, operand2, result = 0; - unsigned long rn; - int c; - - if (bits (this_instr, 12, 15) != 15) - break; - - if (bits (this_instr, 22, 25) == 0 - && bits (this_instr, 4, 7) == 9) /* multiply */ - error (_("Invalid update to pc in instruction")); - - /* BX , BLX */ - if (bits (this_instr, 4, 27) == 0x12fff1 - || bits (this_instr, 4, 27) == 0x12fff3) - { - rn = bits (this_instr, 0, 3); - nextpc = ((rn == ARM_PC_REGNUM) - ? (pc_val + 8) - : get_frame_register_unsigned (frame, rn)); - - return nextpc; - } - - /* Multiply into PC. */ - c = (status & FLAG_C) ? 1 : 0; - rn = bits (this_instr, 16, 19); - operand1 = ((rn == ARM_PC_REGNUM) - ? (pc_val + 8) - : get_frame_register_unsigned (frame, rn)); - - if (bit (this_instr, 25)) - { - unsigned long immval = bits (this_instr, 0, 7); - unsigned long rotate = 2 * bits (this_instr, 8, 11); - operand2 = ((immval >> rotate) | (immval << (32 - rotate))) - & 0xffffffff; - } - else /* operand 2 is a shifted register. */ - operand2 = shifted_reg_val (frame, this_instr, c, - pc_val, status); - - switch (bits (this_instr, 21, 24)) - { - case 0x0: /*and */ - result = operand1 & operand2; - break; - - case 0x1: /*eor */ - result = operand1 ^ operand2; - break; - - case 0x2: /*sub */ - result = operand1 - operand2; - break; - - case 0x3: /*rsb */ - result = operand2 - operand1; - break; - - case 0x4: /*add */ - result = operand1 + operand2; - break; - - case 0x5: /*adc */ - result = operand1 + operand2 + c; - break; - - case 0x6: /*sbc */ - result = operand1 - operand2 + c; - break; - - case 0x7: /*rsc */ - result = operand2 - operand1 + c; - break; - - case 0x8: - case 0x9: - case 0xa: - case 0xb: /* tst, teq, cmp, cmn */ - result = (unsigned long) nextpc; - break; - - case 0xc: /*orr */ - result = operand1 | operand2; - break; - - case 0xd: /*mov */ - /* Always step into a function. */ - result = operand2; - break; - - case 0xe: /*bic */ - result = operand1 & ~operand2; - break; - - case 0xf: /*mvn */ - result = ~operand2; - break; - } - - /* In 26-bit APCS the bottom two bits of the result are - ignored, and we always end up in ARM state. */ - if (!arm_apcs_32) - nextpc = arm_addr_bits_remove (gdbarch, result); - else - nextpc = result; - - break; - } - - case 0x4: - case 0x5: /* data transfer */ - case 0x6: - case 0x7: - if (bit (this_instr, 20)) - { - /* load */ - if (bits (this_instr, 12, 15) == 15) - { - /* rd == pc */ - unsigned long rn; - unsigned long base; - - if (bit (this_instr, 22)) - error (_("Invalid update to pc in instruction")); - - /* byte write to PC */ - rn = bits (this_instr, 16, 19); - base = ((rn == ARM_PC_REGNUM) - ? (pc_val + 8) - : get_frame_register_unsigned (frame, rn)); - - if (bit (this_instr, 24)) - { - /* pre-indexed */ - int c = (status & FLAG_C) ? 1 : 0; - unsigned long offset = - (bit (this_instr, 25) - ? shifted_reg_val (frame, this_instr, c, pc_val, status) - : bits (this_instr, 0, 11)); - - if (bit (this_instr, 23)) - base += offset; - else - base -= offset; - } - nextpc = - (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) base, - 4, byte_order); - } - } - break; - - case 0x8: - case 0x9: /* block transfer */ - if (bit (this_instr, 20)) - { - /* LDM */ - if (bit (this_instr, 15)) - { - /* loading pc */ - int offset = 0; - unsigned long rn_val - = get_frame_register_unsigned (frame, - bits (this_instr, 16, 19)); - - if (bit (this_instr, 23)) - { - /* up */ - unsigned long reglist = bits (this_instr, 0, 14); - offset = bitcount (reglist) * 4; - if (bit (this_instr, 24)) /* pre */ - offset += 4; - } - else if (bit (this_instr, 24)) - offset = -4; - - nextpc = - (CORE_ADDR) read_memory_unsigned_integer ((CORE_ADDR) - (rn_val + offset), - 4, byte_order); - } - } - break; - - case 0xb: /* branch & link */ - case 0xa: /* branch */ - { - nextpc = BranchDest (pc, this_instr); - break; - } - - case 0xc: - case 0xd: - case 0xe: /* coproc ops */ - break; - case 0xf: /* SWI */ - { - struct gdbarch_tdep *tdep; - tdep = gdbarch_tdep (gdbarch); - - if (tdep->syscall_next_pc != NULL) - nextpc = tdep->syscall_next_pc (frame); - - } - break; - - default: - fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n")); - return (pc); - } - } - - return nextpc; -} - -/* Determine next PC after current instruction executes. Will call either - arm_get_next_pc_raw or thumb_get_next_pc_raw. Error out if infinite - loop is detected. */ - -CORE_ADDR -arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc) -{ - CORE_ADDR nextpc; - - if (arm_frame_is_thumb (frame)) - nextpc = thumb_get_next_pc_raw (frame, pc); - else - nextpc = arm_get_next_pc_raw (frame, pc); - - return nextpc; -} - -/* Like insert_single_step_breakpoint, but make sure we use a breakpoint - of the appropriate mode (as encoded in the PC value), even if this - differs from what would be expected according to the symbol tables. */ - -void -arm_insert_single_step_breakpoint (struct gdbarch *gdbarch, - struct address_space *aspace, - CORE_ADDR pc) -{ - struct cleanup *old_chain - = make_cleanup_restore_integer (&arm_override_mode); - - arm_override_mode = IS_THUMB_ADDR (pc); - pc = gdbarch_addr_bits_remove (gdbarch, pc); - - insert_single_step_breakpoint (gdbarch, aspace, pc); - - do_cleanups (old_chain); -} - -/* Checks for an atomic sequence of instructions beginning with a LDREX{,B,H,D} - instruction and ending with a STREX{,B,H,D} instruction. If such a sequence - is found, attempt to step through it. A breakpoint is placed at the end of - the sequence. */ - -static int -thumb_deal_with_atomic_sequence_raw (struct frame_info *frame) -{ - struct gdbarch *gdbarch = get_frame_arch (frame); - struct address_space *aspace = get_frame_address_space (frame); - enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); - CORE_ADDR pc = get_frame_pc (frame); - CORE_ADDR breaks[2] = {-1, -1}; - CORE_ADDR loc = pc; - unsigned short insn1, insn2; - int insn_count; - int index; - int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ - const int atomic_sequence_length = 16; /* Instruction sequence length. */ - ULONGEST status, itstate; - - /* We currently do not support atomic sequences within an IT block. */ - status = get_frame_register_unsigned (frame, ARM_PS_REGNUM); - itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3); - if (itstate & 0x0f) - return 0; - - /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */ - insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code); - loc += 2; - if (thumb_insn_size (insn1) != 4) - return 0; - - insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code); - loc += 2; - if (!((insn1 & 0xfff0) == 0xe850 - || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040))) - return 0; - - /* Assume that no atomic sequence is longer than "atomic_sequence_length" - instructions. */ - for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) - { - insn1 = read_memory_unsigned_integer (loc, 2, byte_order_for_code); - loc += 2; - - if (thumb_insn_size (insn1) != 4) - { - /* Assume that there is at most one conditional branch in the - atomic sequence. If a conditional branch is found, put a - breakpoint in its destination address. */ - if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f) - { - if (last_breakpoint > 0) - return 0; /* More than one conditional branch found, - fallback to the standard code. */ + /* These registers are only supported on targets which supply + an XML description. */ + return builtin_type (gdbarch)->builtin_int0; + else + return builtin_type (gdbarch)->builtin_uint32; +} - breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1); - last_breakpoint++; - } +/* Map a DWARF register REGNUM onto the appropriate GDB register + number. */ - /* We do not support atomic sequences that use any *other* - instructions but conditional branches to change the PC. - Fall back to standard code to avoid losing control of - execution. */ - else if (thumb_instruction_changes_pc (insn1)) - return 0; - } - else - { - insn2 = read_memory_unsigned_integer (loc, 2, byte_order_for_code); - loc += 2; +static int +arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) +{ + /* Core integer regs. */ + if (reg >= 0 && reg <= 15) + return reg; - /* Assume that there is at most one conditional branch in the - atomic sequence. If a conditional branch is found, put a - breakpoint in its destination address. */ - if ((insn1 & 0xf800) == 0xf000 - && (insn2 & 0xd000) == 0x8000 - && (insn1 & 0x0380) != 0x0380) - { - int sign, j1, j2, imm1, imm2; - unsigned int offset; + /* Legacy FPA encoding. These were once used in a way which + overlapped with VFP register numbering, so their use is + discouraged, but GDB doesn't support the ARM toolchain + which used them for VFP. */ + if (reg >= 16 && reg <= 23) + return ARM_F0_REGNUM + reg - 16; - sign = sbits (insn1, 10, 10); - imm1 = bits (insn1, 0, 5); - imm2 = bits (insn2, 0, 10); - j1 = bit (insn2, 13); - j2 = bit (insn2, 11); + /* New assignments for the FPA registers. */ + if (reg >= 96 && reg <= 103) + return ARM_F0_REGNUM + reg - 96; - offset = (sign << 20) + (j2 << 19) + (j1 << 18); - offset += (imm1 << 12) + (imm2 << 1); + /* WMMX register assignments. */ + if (reg >= 104 && reg <= 111) + return ARM_WCGR0_REGNUM + reg - 104; - if (last_breakpoint > 0) - return 0; /* More than one conditional branch found, - fallback to the standard code. */ + if (reg >= 112 && reg <= 127) + return ARM_WR0_REGNUM + reg - 112; - breaks[1] = loc + offset; - last_breakpoint++; - } + if (reg >= 192 && reg <= 199) + return ARM_WC0_REGNUM + reg - 192; - /* We do not support atomic sequences that use any *other* - instructions but conditional branches to change the PC. - Fall back to standard code to avoid losing control of - execution. */ - else if (thumb2_instruction_changes_pc (insn1, insn2)) - return 0; + /* VFP v2 registers. A double precision value is actually + in d1 rather than s2, but the ABI only defines numbering + for the single precision registers. This will "just work" + in GDB for little endian targets (we'll read eight bytes, + starting in s0 and then progressing to s1), but will be + reversed on big endian targets with VFP. This won't + be a problem for the new Neon quad registers; you're supposed + to use DW_OP_piece for those. */ + if (reg >= 64 && reg <= 95) + { + char name_buf[4]; - /* If we find a strex{,b,h,d}, we're done. */ - if ((insn1 & 0xfff0) == 0xe840 - || ((insn1 & 0xfff0) == 0xe8c0 && (insn2 & 0x00c0) == 0x0040)) - break; - } + xsnprintf (name_buf, sizeof (name_buf), "s%d", reg - 64); + return user_reg_map_name_to_regnum (gdbarch, name_buf, + strlen (name_buf)); } - /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */ - if (insn_count == atomic_sequence_length) - return 0; - - /* Insert a breakpoint right after the end of the atomic sequence. */ - breaks[0] = loc; - - /* Check for duplicated breakpoints. Check also for a breakpoint - placed (branch instruction's destination) anywhere in sequence. */ - if (last_breakpoint - && (breaks[1] == breaks[0] - || (breaks[1] >= pc && breaks[1] < loc))) - last_breakpoint = 0; + /* VFP v3 / Neon registers. This range is also used for VFP v2 + registers, except that it now describes d0 instead of s0. */ + if (reg >= 256 && reg <= 287) + { + char name_buf[4]; - /* Effectively inserts the breakpoints. */ - for (index = 0; index <= last_breakpoint; index++) - arm_insert_single_step_breakpoint (gdbarch, aspace, - MAKE_THUMB_ADDR (breaks[index])); + xsnprintf (name_buf, sizeof (name_buf), "d%d", reg - 256); + return user_reg_map_name_to_regnum (gdbarch, name_buf, + strlen (name_buf)); + } - return 1; + return -1; } +/* Map GDB internal REGNUM onto the Arm simulator register numbers. */ static int -arm_deal_with_atomic_sequence_raw (struct frame_info *frame) +arm_register_sim_regno (struct gdbarch *gdbarch, int regnum) { - struct gdbarch *gdbarch = get_frame_arch (frame); - struct address_space *aspace = get_frame_address_space (frame); - enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); - CORE_ADDR pc = get_frame_pc (frame); - CORE_ADDR breaks[2] = {-1, -1}; - CORE_ADDR loc = pc; - unsigned int insn; - int insn_count; - int index; - int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ - const int atomic_sequence_length = 16; /* Instruction sequence length. */ - - /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. - Note that we do not currently support conditionally executed atomic - instructions. */ - insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code); - loc += 4; - if ((insn & 0xff9000f0) != 0xe1900090) - return 0; - - /* Assume that no atomic sequence is longer than "atomic_sequence_length" - instructions. */ - for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) - { - insn = read_memory_unsigned_integer (loc, 4, byte_order_for_code); - loc += 4; - - /* Assume that there is at most one conditional branch in the atomic - sequence. If a conditional branch is found, put a breakpoint in - its destination address. */ - if (bits (insn, 24, 27) == 0xa) - { - if (last_breakpoint > 0) - return 0; /* More than one conditional branch found, fallback - to the standard single-step code. */ - - breaks[1] = BranchDest (loc - 4, insn); - last_breakpoint++; - } + int reg = regnum; + gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); - /* We do not support atomic sequences that use any *other* instructions - but conditional branches to change the PC. Fall back to standard - code to avoid losing control of execution. */ - else if (arm_instruction_changes_pc (insn)) - return 0; + if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM) + return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM; - /* If we find a strex{,b,h,d}, we're done. */ - if ((insn & 0xff9000f0) == 0xe1800090) - break; - } + if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM) + return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM; - /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */ - if (insn_count == atomic_sequence_length) - return 0; + if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM) + return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM; - /* Insert a breakpoint right after the end of the atomic sequence. */ - breaks[0] = loc; + if (reg < NUM_GREGS) + return SIM_ARM_R0_REGNUM + reg; + reg -= NUM_GREGS; - /* Check for duplicated breakpoints. Check also for a breakpoint - placed (branch instruction's destination) anywhere in sequence. */ - if (last_breakpoint - && (breaks[1] == breaks[0] - || (breaks[1] >= pc && breaks[1] < loc))) - last_breakpoint = 0; + if (reg < NUM_FREGS) + return SIM_ARM_FP0_REGNUM + reg; + reg -= NUM_FREGS; - /* Effectively inserts the breakpoints. */ - for (index = 0; index <= last_breakpoint; index++) - arm_insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); + if (reg < NUM_SREGS) + return SIM_ARM_FPS_REGNUM + reg; + reg -= NUM_SREGS; - return 1; + internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum); } -int -arm_deal_with_atomic_sequence (struct frame_info *frame) +/* NOTE: cagney/2001-08-20: Both convert_from_extended() and + convert_to_extended() use floatformat_arm_ext_littlebyte_bigword. + It is thought that this is is the floating-point register format on + little-endian systems. */ + +static void +convert_from_extended (const struct floatformat *fmt, const void *ptr, + void *dbl, int endianess) { - if (arm_frame_is_thumb (frame)) - return thumb_deal_with_atomic_sequence_raw (frame); + DOUBLEST d; + + if (endianess == BFD_ENDIAN_BIG) + floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d); else - return arm_deal_with_atomic_sequence_raw (frame); + floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword, + ptr, &d); + floatformat_from_doublest (fmt, &d, dbl); } -/* single_step() is called just before we want to resume the inferior, - if we want to single-step it but there is no hardware or kernel - single-step support. We find the target of the coming instruction - and breakpoint it. */ - -int -arm_software_single_step (struct frame_info *frame) +static void +convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, + int endianess) { - struct gdbarch *gdbarch = get_frame_arch (frame); - struct address_space *aspace = get_frame_address_space (frame); - CORE_ADDR next_pc; - - if (arm_deal_with_atomic_sequence (frame)) - return 1; - - next_pc = arm_get_next_pc (frame, get_frame_pc (frame)); - arm_insert_single_step_breakpoint (gdbarch, aspace, next_pc); + DOUBLEST d; - return 1; + floatformat_to_doublest (fmt, ptr, &d); + if (endianess == BFD_ENDIAN_BIG) + floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl); + else + floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword, + &d, dbl); } /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand @@ -5342,10 +4247,10 @@ extend_buffer_earlier (gdb_byte *buf, CORE_ADDR endaddr, gdb_byte *new_buf; int bytes_to_read = new_len - old_len; - new_buf = xmalloc (new_len); + new_buf = (gdb_byte *) xmalloc (new_len); memcpy (new_buf + bytes_to_read, buf, old_len); xfree (buf); - if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0) + if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0) { xfree (new_buf); return NULL; @@ -5403,13 +4308,13 @@ arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) footwork to distinguish a real IT instruction from the second half of a 32-bit instruction, but there is no need for that if there's no candidate. */ - buf_len = min (bpaddr - boundary, MAX_IT_BLOCK_PREFIX); + buf_len = std::min (bpaddr - boundary, (CORE_ADDR) MAX_IT_BLOCK_PREFIX); if (buf_len == 0) /* No room for an IT instruction. */ return bpaddr; - buf = xmalloc (buf_len); - if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0) + buf = (gdb_byte *) xmalloc (buf_len); + if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0) return bpaddr; any = 0; for (i = 0; i < buf_len; i += 2) @@ -5421,6 +4326,7 @@ arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) break; } } + if (any == 0) { xfree (buf); @@ -5523,13 +4429,12 @@ arm_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) Generally ARM displaced stepping works as follows: 1. When an instruction is to be single-stepped, it is first decoded by - arm_process_displaced_insn (called from arm_displaced_step_copy_insn). - Depending on the type of instruction, it is then copied to a scratch - location, possibly in a modified form. The copy_* set of functions - performs such modification, as necessary. A breakpoint is placed after - the modified instruction in the scratch space to return control to GDB. - Note in particular that instructions which modify the PC will no longer - do so after modification. + arm_process_displaced_insn. Depending on the type of instruction, it is + then copied to a scratch location, possibly in a modified form. The + copy_* set of functions performs such modification, as necessary. A + breakpoint is placed after the modified instruction in the scratch space + to return control to GDB. Note in particular that instructions which + modify the PC will no longer do so after modification. 2. The instruction is single-stepped, by setting the PC to the scratch location address, and resuming. Control returns to GDB when the @@ -5785,7 +4690,7 @@ thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1, /* Copy 16-bit Thumb(Thumb and 16-bit Thumb-2) instruction without any modification. */ static int -thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, unsigned int insn, +thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn, const char *iname, struct displaced_step_closure *dsc) { @@ -6183,7 +5088,7 @@ thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1, /* Copy B Thumb instructions. */ static int -thumb_copy_b (struct gdbarch *gdbarch, unsigned short insn, +thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn, struct displaced_step_closure *dsc) { unsigned int cond = 0; @@ -6429,7 +5334,7 @@ install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs, Preparation: tmp1, tmp2, tmp3 <- r0, r1, r2; r0, r1, r2 <- rd, rn, rm - Insn: r0, r1, r2 [, ] + Insn: r0, [r1,] r2 [, ] Cleanup: rd <- r0; r0, r1, r2 <- tmp1, tmp2, tmp3 */ @@ -6476,22 +5381,21 @@ thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn, struct regcache *regs, struct displaced_step_closure *dsc) { - unsigned rn, rm, rd; + unsigned rm, rd; - rd = bits (insn, 3, 6); - rn = (bit (insn, 7) << 3) | bits (insn, 0, 2); - rm = 2; + rm = bits (insn, 3, 6); + rd = (bit (insn, 7) << 3) | bits (insn, 0, 2); - if (rd != ARM_PC_REGNUM && rn != ARM_PC_REGNUM) + if (rd != ARM_PC_REGNUM && rm != ARM_PC_REGNUM) return thumb_copy_unmodified_16bit (gdbarch, insn, "ALU reg", dsc); if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, "displaced: copying reg %s insn %.4x\n", - "ALU", (unsigned short) insn); + fprintf_unfiltered (gdb_stdlog, "displaced: copying ALU reg insn %.4x\n", + (unsigned short) insn); - dsc->modinsn[0] = ((insn & 0xff00) | 0x08); + dsc->modinsn[0] = ((insn & 0xff00) | 0x10); - install_alu_reg (gdbarch, regs, dsc, rd, rn, rm); + install_alu_reg (gdbarch, regs, dsc, rd, rd, rm); return 0; } @@ -6637,7 +5541,7 @@ cleanup_store (struct gdbarch *gdbarch, struct regcache *regs, transfers, which have a different encoding to byte/word transfers. */ static int -arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged, +arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged, struct regcache *regs, struct displaced_step_closure *dsc) { unsigned int op1 = bits (insn, 20, 24); @@ -6656,7 +5560,7 @@ arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unpriveleged, if (debug_displaced) fprintf_unfiltered (gdb_stdlog, "displaced: copying %sextra load/store " - "insn %.8lx\n", unpriveleged ? "unpriveleged " : "", + "insn %.8lx\n", unprivileged ? "unprivileged " : "", (unsigned long) insn); opcode = ((op2 << 2) | (op1 & 0x1) | ((op1 & 0x4) >> 1)) - 4; @@ -7206,8 +6110,8 @@ arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn, contiguous chunk r0...rX before doing the transfer, then shuffling registers into the correct places in the cleanup routine. */ unsigned int regmask = insn & 0xffff; - unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1; - unsigned int to = 0, from = 0, i, new_rn; + unsigned int num_in_list = bitcount (regmask), new_regmask; + unsigned int i; for (i = 0; i < num_in_list; i++) dsc->tmp[i] = displaced_read_reg (regs, dsc, i); @@ -7308,8 +6212,8 @@ thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, else { unsigned int regmask = dsc->u.block.regmask; - unsigned int num_in_list = bitcount (regmask), new_regmask, bit = 1; - unsigned int to = 0, from = 0, i, new_rn; + unsigned int num_in_list = bitcount (regmask), new_regmask; + unsigned int i; for (i = 0; i < num_in_list; i++) dsc->tmp[i] = displaced_read_reg (regs, dsc, i); @@ -7342,6 +6246,77 @@ thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2, return 0; } +/* Wrapper over read_memory_unsigned_integer for use in arm_get_next_pcs. + This is used to avoid a dependency on BFD's bfd_endian enum. */ + +ULONGEST +arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, + int byte_order) +{ + return read_memory_unsigned_integer (memaddr, len, + (enum bfd_endian) byte_order); +} + +/* Wrapper over gdbarch_addr_bits_remove for use in arm_get_next_pcs. */ + +CORE_ADDR +arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, + CORE_ADDR val) +{ + return gdbarch_addr_bits_remove (get_regcache_arch (self->regcache), val); +} + +/* Wrapper over syscall_next_pc for use in get_next_pcs. */ + +static CORE_ADDR +arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) +{ + return 0; +} + +/* Wrapper over arm_is_thumb for use in arm_get_next_pcs. */ + +int +arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) +{ + return arm_is_thumb (self->regcache); +} + +/* single_step() is called just before we want to resume the inferior, + if we want to single-step it but there is no hardware or kernel + single-step support. We find the target of the coming instructions + and breakpoint them. */ + +VEC (CORE_ADDR) * +arm_software_single_step (struct regcache *regcache) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct arm_get_next_pcs next_pcs_ctx; + CORE_ADDR pc; + int i; + VEC (CORE_ADDR) *next_pcs = NULL; + struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs); + + arm_get_next_pcs_ctor (&next_pcs_ctx, + &arm_get_next_pcs_ops, + gdbarch_byte_order (gdbarch), + gdbarch_byte_order_for_code (gdbarch), + 0, + regcache); + + next_pcs = arm_get_next_pcs (&next_pcs_ctx); + + for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++) + { + pc = gdbarch_addr_bits_remove (gdbarch, pc); + VEC_replace (CORE_ADDR, next_pcs, i, pc); + } + + discard_cleanups (old_chain); + + return next_pcs; +} + /* Cleanup/copy SVC (SWI) instructions. These two functions are overridden for Linux, where some SVC instructions must be treated specially. */ @@ -7614,7 +6589,6 @@ arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn, { unsigned int op2 = bits (insn, 4, 6); unsigned int op = bits (insn, 21, 22); - unsigned int op1 = bits (insn, 16, 19); switch (op2) { @@ -7695,7 +6669,7 @@ arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, else if ((op1 & 0x10) == 0x10 && op2 == 0x9) return arm_copy_unmodified (gdbarch, insn, "synch", dsc); else if (op2 == 0xb || (op2 & 0xd) == 0xd) - /* 2nd arg means "unpriveleged". */ + /* 2nd arg means "unprivileged". */ return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, dsc); } @@ -7711,7 +6685,6 @@ arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn, { int a = bit (insn, 25), b = bit (insn, 4); uint32_t op1 = bits (insn, 20, 24); - int rn_f = bits (insn, 16, 19) == 0xf; if ((!a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02) || (a && (op1 & 0x05) == 0x00 && (op1 & 0x17) != 0x02 && !b)) @@ -7799,7 +6772,7 @@ arm_decode_media (struct gdbarch *gdbarch, uint32_t insn, } static int -arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn, +arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc) { @@ -7900,13 +6873,12 @@ thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1, } static int -arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to, +arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc) { unsigned int op1 = bits (insn, 20, 25); int op = bit (insn, 4); unsigned int coproc = bits (insn, 8, 11); - unsigned int rn = bits (insn, 16, 19); if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa) return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc); @@ -7951,11 +6923,9 @@ thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1, struct displaced_step_closure *dsc) { unsigned int coproc = bits (insn2, 8, 11); - unsigned int op1 = bits (insn1, 4, 9); unsigned int bit_5_8 = bits (insn1, 5, 8); unsigned int bit_9 = bit (insn1, 9); unsigned int bit_4 = bit (insn1, 4); - unsigned int rn = bits (insn1, 0, 3); if (bit_9 == 0) { @@ -8074,14 +7044,13 @@ thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1, } static int -thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, unsigned short insn1, +thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, struct displaced_step_closure *dsc) { unsigned int rt = bits (insn1, 8, 10); unsigned int pc; int imm8 = (bits (insn1, 0, 7) << 2); - CORE_ADDR from = dsc->insn_addr; /* LDR Rd, #imm8 @@ -8224,7 +7193,7 @@ cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs, } static int -thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1, +thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1, struct regcache *regs, struct displaced_step_closure *dsc) { @@ -8270,8 +7239,8 @@ thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, unsigned short insn1, else { unsigned int num_in_list = bitcount (dsc->u.block.regmask); - unsigned int new_regmask, bit = 1; - unsigned int to = 0, from = 0, i, new_rn; + unsigned int i; + unsigned int new_regmask; for (i = 0; i < num_in_list + 1; i++) dsc->tmp[i] = displaced_read_reg (regs, dsc, i); @@ -8408,7 +7377,6 @@ decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch, int rt = bits (insn2, 12, 15); int rn = bits (insn1, 0, 3); int op1 = bits (insn1, 7, 8); - int err = 0; switch (bits (insn1, 5, 6)) { @@ -8610,7 +7578,7 @@ thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1, static void thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, - CORE_ADDR to, struct regcache *regs, + struct regcache *regs, struct displaced_step_closure *dsc) { enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); @@ -8651,7 +7619,7 @@ arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, dsc->wrote_to_pc = 0; if (!displaced_in_arm_mode (regs)) - return thumb_process_displaced_insn (gdbarch, from, to, regs, dsc); + return thumb_process_displaced_insn (gdbarch, from, regs, dsc); dsc->is_thumb = 0; dsc->insn_size = 4; @@ -8682,7 +7650,7 @@ arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, break; case 0xc: case 0xd: case 0xe: case 0xf: - err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc); + err = arm_decode_svc_copro (gdbarch, insn, regs, dsc); break; } @@ -8747,22 +7715,6 @@ arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, paddress (gdbarch, from), paddress (gdbarch, to)); } -/* Entry point for copying an instruction into scratch space for displaced - stepping. */ - -struct displaced_step_closure * -arm_displaced_step_copy_insn (struct gdbarch *gdbarch, - CORE_ADDR from, CORE_ADDR to, - struct regcache *regs) -{ - struct displaced_step_closure *dsc - = xmalloc (sizeof (struct displaced_step_closure)); - arm_process_displaced_insn (gdbarch, from, to, regs, dsc); - arm_displaced_init_closure (gdbarch, from, to, dsc); - - return dsc; -} - /* Entry point for cleaning things up after a displaced instruction has been single-stepped. */ @@ -8787,7 +7739,7 @@ arm_displaced_step_fixup (struct gdbarch *gdbarch, static int gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) { - struct gdbarch *gdbarch = info->application_data; + struct gdbarch *gdbarch = (struct gdbarch *) info->application_data; if (arm_pc_is_thumb (gdbarch, memaddr)) { @@ -8865,16 +7817,10 @@ static const gdb_byte arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT; static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT; static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT; -/* Determine the type and size of breakpoint to insert at PCPTR. Uses - the program counter value to determine whether a 16-bit or 32-bit - breakpoint should be used. It returns a pointer to a string of - bytes that encode a breakpoint instruction, stores the length of - the string to *lenptr, and adjusts the program counter (if - necessary) to point to the actual memory location where the - breakpoint should be inserted. */ +/* Implement the breakpoint_kind_from_pc gdbarch method. */ -static const unsigned char * -arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) +static int +arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); @@ -8888,38 +7834,98 @@ arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) if (tdep->thumb2_breakpoint != NULL) { gdb_byte buf[2]; + if (target_read_memory (*pcptr, buf, 2) == 0) { unsigned short inst1; + inst1 = extract_unsigned_integer (buf, 2, byte_order_for_code); if (thumb_insn_size (inst1) == 4) - { - *lenptr = tdep->thumb2_breakpoint_size; - return tdep->thumb2_breakpoint; - } + return ARM_BP_KIND_THUMB2; } } - *lenptr = tdep->thumb_breakpoint_size; - return tdep->thumb_breakpoint; + return ARM_BP_KIND_THUMB; } else + return ARM_BP_KIND_ARM; + +} + +/* Implement the sw_breakpoint_from_kind gdbarch method. */ + +static const gdb_byte * +arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + switch (kind) { - *lenptr = tdep->arm_breakpoint_size; + case ARM_BP_KIND_ARM: + *size = tdep->arm_breakpoint_size; return tdep->arm_breakpoint; + case ARM_BP_KIND_THUMB: + *size = tdep->thumb_breakpoint_size; + return tdep->thumb_breakpoint; + case ARM_BP_KIND_THUMB2: + *size = tdep->thumb2_breakpoint_size; + return tdep->thumb2_breakpoint; + default: + gdb_assert_not_reached ("unexpected arm breakpoint kind"); } } -static void -arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, - int *kindptr) +/* Implement the breakpoint_kind_from_current_state gdbarch method. */ + +static int +arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, + struct regcache *regcache, + CORE_ADDR *pcptr) { - arm_breakpoint_from_pc (gdbarch, pcptr, kindptr); + gdb_byte buf[4]; + + /* Check the memory pointed by PC is readable. */ + if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0) + { + struct arm_get_next_pcs next_pcs_ctx; + CORE_ADDR pc; + int i; + VEC (CORE_ADDR) *next_pcs = NULL; + struct cleanup *old_chain + = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs); + + arm_get_next_pcs_ctor (&next_pcs_ctx, + &arm_get_next_pcs_ops, + gdbarch_byte_order (gdbarch), + gdbarch_byte_order_for_code (gdbarch), + 0, + regcache); + + next_pcs = arm_get_next_pcs (&next_pcs_ctx); + + /* If MEMADDR is the next instruction of current pc, do the + software single step computation, and get the thumb mode by + the destination address. */ + for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++) + { + if (UNMAKE_THUMB_ADDR (pc) == *pcptr) + { + do_cleanups (old_chain); + + if (IS_THUMB_ADDR (pc)) + { + *pcptr = MAKE_THUMB_ADDR (*pcptr); + return arm_breakpoint_kind_from_pc (gdbarch, pcptr); + } + else + return ARM_BP_KIND_ARM; + } + } + + do_cleanups (old_chain); + } - if (arm_pc_is_thumb (gdbarch, *pcptr) && *kindptr == 4) - /* The documented magic value for a 32-bit Thumb-2 breakpoint, so - that this is not confused with a 32-bit ARM breakpoint. */ - *kindptr = 3; + return arm_breakpoint_kind_from_pc (gdbarch, pcptr); } /* Extract from an array REGBUF containing the (raw) register state a @@ -9023,99 +8029,113 @@ arm_extract_return_value (struct type *type, struct regcache *regs, static int arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) { - int nRc; enum type_code code; - CHECK_TYPEDEF (type); - - /* In the ARM ABI, "integer" like aggregate types are returned in - registers. For an aggregate type to be integer like, its size - must be less than or equal to INT_REGISTER_SIZE and the - offset of each addressable subfield must be zero. Note that bit - fields are not addressable, and all addressable subfields of - unions always start at offset zero. + type = check_typedef (type); - This function is based on the behaviour of GCC 2.95.1. - See: gcc/arm.c: arm_return_in_memory() for details. - - Note: All versions of GCC before GCC 2.95.2 do not set up the - parameters correctly for a function returning the following - structure: struct { float f;}; This should be returned in memory, - not a register. Richard Earnshaw sent me a patch, but I do not - know of any way to detect if a function like the above has been - compiled with the correct calling convention. */ + /* Simple, non-aggregate types (ie not including vectors and + complex) are always returned in a register (or registers). */ + code = TYPE_CODE (type); + if (TYPE_CODE_STRUCT != code && TYPE_CODE_UNION != code + && TYPE_CODE_ARRAY != code && TYPE_CODE_COMPLEX != code) + return 0; - /* All aggregate types that won't fit in a register must be returned - in memory. */ - if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) + if (TYPE_CODE_ARRAY == code && TYPE_VECTOR (type)) { - return 1; + /* Vector values should be returned using ARM registers if they + are not over 16 bytes. */ + return (TYPE_LENGTH (type) > 16); } - /* The AAPCS says all aggregates not larger than a word are returned - in a register. */ if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS) - return 0; - - /* The only aggregate types that can be returned in a register are - structs and unions. Arrays must be returned in memory. */ - code = TYPE_CODE (type); - if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) { + /* The AAPCS says all aggregates not larger than a word are returned + in a register. */ + if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE) + return 0; + return 1; } + else + { + int nRc; + + /* All aggregate types that won't fit in a register must be returned + in memory. */ + if (TYPE_LENGTH (type) > INT_REGISTER_SIZE) + return 1; - /* Assume all other aggregate types can be returned in a register. - Run a check for structures, unions and arrays. */ - nRc = 0; + /* In the ARM ABI, "integer" like aggregate types are returned in + registers. For an aggregate type to be integer like, its size + must be less than or equal to INT_REGISTER_SIZE and the + offset of each addressable subfield must be zero. Note that bit + fields are not addressable, and all addressable subfields of + unions always start at offset zero. - if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) - { - int i; - /* Need to check if this struct/union is "integer" like. For - this to be true, its size must be less than or equal to - INT_REGISTER_SIZE and the offset of each addressable - subfield must be zero. Note that bit fields are not - addressable, and unions always start at offset zero. If any - of the subfields is a floating point type, the struct/union - cannot be an integer type. */ - - /* For each field in the object, check: - 1) Is it FP? --> yes, nRc = 1; - 2) Is it addressable (bitpos != 0) and - not packed (bitsize == 0)? - --> yes, nRc = 1 - */ - - for (i = 0; i < TYPE_NFIELDS (type); i++) - { - enum type_code field_type_code; - field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, - i))); - - /* Is it a floating point type field? */ - if (field_type_code == TYPE_CODE_FLT) - { - nRc = 1; - break; - } + This function is based on the behaviour of GCC 2.95.1. + See: gcc/arm.c: arm_return_in_memory() for details. + + Note: All versions of GCC before GCC 2.95.2 do not set up the + parameters correctly for a function returning the following + structure: struct { float f;}; This should be returned in memory, + not a register. Richard Earnshaw sent me a patch, but I do not + know of any way to detect if a function like the above has been + compiled with the correct calling convention. */ + + /* Assume all other aggregate types can be returned in a register. + Run a check for structures, unions and arrays. */ + nRc = 0; - /* If bitpos != 0, then we have to care about it. */ - if (TYPE_FIELD_BITPOS (type, i) != 0) + if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) + { + int i; + /* Need to check if this struct/union is "integer" like. For + this to be true, its size must be less than or equal to + INT_REGISTER_SIZE and the offset of each addressable + subfield must be zero. Note that bit fields are not + addressable, and unions always start at offset zero. If any + of the subfields is a floating point type, the struct/union + cannot be an integer type. */ + + /* For each field in the object, check: + 1) Is it FP? --> yes, nRc = 1; + 2) Is it addressable (bitpos != 0) and + not packed (bitsize == 0)? + --> yes, nRc = 1 + */ + + for (i = 0; i < TYPE_NFIELDS (type); i++) { - /* Bitfields are not addressable. If the field bitsize is - zero, then the field is not packed. Hence it cannot be - a bitfield or any other packed type. */ - if (TYPE_FIELD_BITSIZE (type, i) == 0) + enum type_code field_type_code; + + field_type_code + = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, + i))); + + /* Is it a floating point type field? */ + if (field_type_code == TYPE_CODE_FLT) { nRc = 1; break; } + + /* If bitpos != 0, then we have to care about it. */ + if (TYPE_FIELD_BITPOS (type, i) != 0) + { + /* Bitfields are not addressable. If the field bitsize is + zero, then the field is not packed. Hence it cannot be + a bitfield or any other packed type. */ + if (TYPE_FIELD_BITSIZE (type, i) == 0) + { + nRc = 1; + break; + } + } } } - } - return nRc; + return nRc; + } } /* Write into appropriate registers a function return value of type @@ -9270,12 +8290,11 @@ arm_return_value (struct gdbarch *gdbarch, struct value *function, || arm_return_in_memory (gdbarch, valtype)) return RETURN_VALUE_STRUCT_CONVENTION; } - - /* AAPCS returns complex types longer than a register in memory. */ - if (tdep->arm_abi != ARM_ABI_APCS - && TYPE_CODE (valtype) == TYPE_CODE_COMPLEX - && TYPE_LENGTH (valtype) > INT_REGISTER_SIZE) - return RETURN_VALUE_STRUCT_CONVENTION; + else if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX) + { + if (arm_return_in_memory (gdbarch, valtype)) + return RETURN_VALUE_STRUCT_CONVENTION; + } if (writebuf) arm_store_return_value (valtype, regcache, writebuf); @@ -9333,8 +8352,8 @@ arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) _call_via_xx, where x is the register name. The possible names are r0-r9, sl, fp, ip, sp, and lr. ARM RealView has similar functions, named __ARM_call_via_r[0-7]. */ - if (strncmp (name, "_call_via_", 10) == 0 - || strncmp (name, "__ARM_call_via_", strlen ("__ARM_call_via_")) == 0) + if (startswith (name, "_call_via_") + || startswith (name, "__ARM_call_via_")) { /* Use the name suffix to determine which register contains the target PC. */ @@ -9356,11 +8375,9 @@ arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) namelen = strlen (name); if (name[0] == '_' && name[1] == '_' && ((namelen > 2 + strlen ("_from_thumb") - && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb", - strlen ("_from_thumb")) == 0) + && startswith (name + namelen - strlen ("_from_thumb"), "_from_thumb")) || (namelen > 2 + strlen ("_from_arm") - && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm", - strlen ("_from_arm")) == 0))) + && startswith (name + namelen - strlen ("_from_arm"), "_from_arm")))) { char *target_name; int target_len = namelen - 2; @@ -9373,7 +8390,7 @@ arm_skip_stub (struct frame_info *frame, CORE_ADDR pc) else target_len -= strlen ("_from_arm"); - target_name = alloca (target_len + 1); + target_name = (char *) alloca (target_len + 1); memcpy (target_name, name + 2, target_len); target_name[target_len] = '\0'; @@ -9423,12 +8440,12 @@ static void set_fp_model_sfunc (char *args, int from_tty, struct cmd_list_element *c) { - enum arm_float_model fp_model; + int fp_model; for (fp_model = ARM_FLOAT_AUTO; fp_model != ARM_FLOAT_LAST; fp_model++) if (strcmp (current_fp_model, fp_model_strings[fp_model]) == 0) { - arm_fp_model = fp_model; + arm_fp_model = (enum arm_float_model) fp_model; break; } @@ -9460,12 +8477,12 @@ static void arm_set_abi (char *args, int from_tty, struct cmd_list_element *c) { - enum arm_abi_kind arm_abi; + int arm_abi; for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++) if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0) { - arm_abi_global = arm_abi; + arm_abi_global = (enum arm_abi_kind) arm_abi; break; } @@ -9506,8 +8523,6 @@ static void arm_show_force_mode (struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value) { - struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); - fprintf_filtered (file, _("The current execution mode assumed " "(even when symbols are available) is \"%s\".\n"), @@ -9602,7 +8617,9 @@ coff_sym_is_thumb (int val) static void arm_elf_make_msymbol_special(asymbol *sym, struct minimal_symbol *msym) { - if (ARM_SYM_BRANCH_TYPE (&((elf_symbol_type *)sym)->internal_elf_sym) + elf_symbol_type *elfsym = (elf_symbol_type *) sym; + + if (ARM_GET_SYM_BRANCH_TYPE (elfsym->internal_elf_sym.st_target_internal) == ST_BRANCH_TO_THUMB) MSYMBOL_SET_SPECIAL (msym); } @@ -9617,7 +8634,7 @@ arm_coff_make_msymbol_special(int val, struct minimal_symbol *msym) static void arm_objfile_data_free (struct objfile *objfile, void *arg) { - struct arm_per_objfile *data = arg; + struct arm_per_objfile *data = (struct arm_per_objfile *) arg; unsigned int i; for (i = 0; i < objfile->obfd->section_count; i++) @@ -9637,7 +8654,8 @@ arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile, if (name[1] != 'a' && name[1] != 't' && name[1] != 'd') return; - data = objfile_data (objfile, arm_objfile_data_key); + data = (struct arm_per_objfile *) objfile_data (objfile, + arm_objfile_data_key); if (data == NULL) { data = OBSTACK_ZALLOC (&objfile->objfile_obstack, @@ -9841,7 +8859,7 @@ arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, static struct value * value_of_arm_user_reg (struct frame_info *frame, const void *baton) { - const int *reg_p = baton; + const int *reg_p = (const int *) baton; return value_of_register (*reg_p, frame); } @@ -9923,6 +8941,22 @@ arm_register_g_packet_guesses (struct gdbarch *gdbarch) /* Otherwise we don't have a useful guess. */ } +/* Implement the code_of_frame_writable gdbarch method. */ + +static int +arm_code_of_frame_writable (struct gdbarch *gdbarch, struct frame_info *frame) +{ + if (gdbarch_tdep (gdbarch)->is_m + && get_frame_type (frame) == SIGTRAMP_FRAME) + { + /* M-profile exception frames return to some magic PCs, where + isn't writable at all. */ + return 0; + } + else + return 1; +} + /* Initialize the current architecture based on INFO. If possible, re-use an architecture from ARCHES, which is a list of @@ -9941,7 +8975,8 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) enum arm_float_model fp_model = arm_fp_model; struct tdesc_arch_data *tdesc_data = NULL; int i, is_m = 0; - int have_vfp_registers = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0; + int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0; + int have_wmmx_registers = 0; int have_neon = 0; int have_fpa_registers = 1; const struct target_desc *tdesc = info.target_desc; @@ -9955,11 +8990,6 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) switch (bfd_get_flavour (info.abfd)) { - case bfd_target_aout_flavour: - /* Assume it's an old APCS-style ABI. */ - arm_abi = ARM_ABI_APCS; - break; - case bfd_target_coff_flavour: /* Assume it's an old APCS-style ABI. */ /* XXX WinCE? */ @@ -9977,7 +9007,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) anyway, so assume APCS. */ arm_abi = ARM_ABI_APCS; } - else if (ei_osabi == ELFOSABI_NONE) + else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU) { int eabi_ver = EF_ARM_EABI_VERSION (e_flags); int attr_arch, attr_profile; @@ -10003,27 +9033,34 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) OBJ_ATTR_PROC, Tag_ABI_VFP_args)) { - case 0: + case AEABI_VFP_args_base: /* "The user intended FP parameter/result passing to conform to AAPCS, base variant". */ fp_model = ARM_FLOAT_SOFT_VFP; break; - case 1: + case AEABI_VFP_args_vfp: /* "The user intended FP parameter/result passing to conform to AAPCS, VFP variant". */ fp_model = ARM_FLOAT_VFP; break; - case 2: + case AEABI_VFP_args_toolchain: /* "The user intended FP parameter/result passing to conform to tool chain-specific conventions" - we don't know any such conventions, so leave it as "auto". */ break; + case AEABI_VFP_args_compatible: + /* "Code is compatible with both the base + and VFP variants; the user did not permit + non-variadic functions to pass FP + parameters/results" - leave it as + "auto". */ + break; default: /* Attribute value not mentioned in the - October 2008 ABI, so leave it as + November 2012 ABI, so leave it as "auto". */ break; } @@ -10198,6 +9235,8 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdesc_data_cleanup (tdesc_data); return NULL; } + + have_wmmx_registers = 1; } /* If we have a VFP unit, check whether the single precision registers @@ -10240,7 +9279,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) if (tdesc_unnumbered_register (feature, "s0") == 0) have_vfp_pseudos = 1; - have_vfp_registers = 1; + vfp_register_count = i; /* If we have VFP, also check for NEON. The architecture allows NEON without VFP (integer vector operations only), but GDB @@ -10300,7 +9339,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) return best_arch->gdbarch; } - tdep = xcalloc (1, sizeof (struct gdbarch_tdep)); + tdep = XCNEW (struct gdbarch_tdep); gdbarch = gdbarch_alloc (&info, tdep); /* Record additional information about the architecture we are defining. @@ -10309,7 +9348,11 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->fp_model = fp_model; tdep->is_m = is_m; tdep->have_fpa_registers = have_fpa_registers; - tdep->have_vfp_registers = have_vfp_registers; + tdep->have_wmmx_registers = have_wmmx_registers; + gdb_assert (vfp_register_count == 0 + || vfp_register_count == 16 + || vfp_register_count == 32); + tdep->vfp_register_count = vfp_register_count; tdep->have_vfp_pseudos = have_vfp_pseudos; tdep->have_neon_pseudos = have_neon_pseudos; tdep->have_neon = have_neon; @@ -10359,6 +9402,9 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call); set_gdbarch_frame_align (gdbarch, arm_frame_align); + if (is_m) + set_gdbarch_code_of_frame_writable (gdbarch, arm_code_of_frame_writable); + set_gdbarch_write_pc (gdbarch, arm_write_pc); /* Frame handling. */ @@ -10374,8 +9420,8 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* Advance PC across function entry code. */ set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue); - /* Detect whether PC is in function epilogue. */ - set_gdbarch_in_function_epilogue_p (gdbarch, arm_in_function_epilogue_p); + /* Detect whether PC is at a point where the stack has been destroyed. */ + set_gdbarch_stack_frame_destroyed_p (gdbarch, arm_stack_frame_destroyed_p); /* Skip trampolines. */ set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub); @@ -10384,9 +9430,10 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_inner_than (gdbarch, core_addr_lessthan); /* Breakpoint manipulation. */ - set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc); - set_gdbarch_remote_breakpoint_from_pc (gdbarch, - arm_remote_breakpoint_from_pc); + set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind); + set_gdbarch_breakpoint_kind_from_current_state (gdbarch, + arm_breakpoint_kind_from_current_state); /* Information about registers, etc. */ set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM); @@ -10436,6 +9483,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind); dwarf2_append_unwinders (gdbarch); frame_unwind_append_unwinder (gdbarch, &arm_exidx_unwind); + frame_unwind_append_unwinder (gdbarch, &arm_epilogue_frame_unwind); frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind); /* Now we have tuned the configuration, set a few final things, @@ -10527,12 +9575,11 @@ _initialize_arm_tdep (void) { struct ui_file *stb; long length; - struct cmd_list_element *new_set, *new_show; const char *setname; const char *setdesc; const char *const *regnames; - int numregs, i, j; - static char *helptext; + int i; + static std::string helptext; char regdesc[1024], *rdptr = regdesc; size_t rest = sizeof (regdesc); @@ -10577,11 +9624,11 @@ _initialize_arm_tdep (void) /* Initialize the array that will be passed to add_setshow_enum_cmd(). */ - valid_disassembly_styles - = xmalloc ((num_disassembly_options + 1) * sizeof (char *)); + valid_disassembly_styles = XNEWVEC (const char *, + num_disassembly_options + 1); for (i = 0; i < num_disassembly_options; i++) { - numregs = get_arm_regnames (i, &setname, &setdesc, ®names); + get_arm_regnames (i, &setname, &setdesc, ®names); valid_disassembly_styles[i] = setname; length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc); rdptr += length; @@ -10603,14 +9650,14 @@ _initialize_arm_tdep (void) _("The valid values are:\n"), regdesc, _("The default is \"std\".")); - helptext = ui_file_xstrdup (stb, NULL); + helptext = ui_file_as_string (stb); ui_file_delete (stb); add_setshow_enum_cmd("disassembler", no_class, valid_disassembly_styles, &disassembly_style, _("Set the disassembly style."), _("Show the disassembly style."), - helptext, + helptext.c_str (), set_disassembly_style_sfunc, NULL, /* FIXME: i18n: The disassembly style is \"%s\". */ @@ -10676,6 +9723,8 @@ vfp - VFP co-processor."), #define THUMB2_INSN_SIZE_BYTES 4 +/* Position of the bit within a 32-bit ARM instruction + that defines whether the instruction is a load or store. */ #define INSN_S_L_BIT_NUM 20 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ @@ -10789,12 +9838,9 @@ arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf, uint32_t reg_src1 = 0, reg_src2 = 0; uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; - uint32_t opcode1 = 0; arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); - opcode1 = bits (arm_insn_r->arm_insn, 20, 24); - if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode) { @@ -10957,7 +10003,6 @@ arm_record_extension_space (insn_decode_record *arm_insn_r) uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0; uint32_t record_buf[8], record_buf_mem[8]; uint32_t reg_src1 = 0; - uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0; struct regcache *reg_cache = arm_insn_r->regcache; ULONGEST u_regval = 0; @@ -11043,11 +10088,6 @@ arm_record_extension_space (insn_decode_record *arm_insn_r) { /* SPSR is going to be changed. */ /* We need to get SPSR value, which is yet to be done. */ - printf_unfiltered (_("Process record does not support " - "instruction 0x%0x at address %s.\n"), - arm_insn_r->arm_insn, - paddress (arm_insn_r->gdbarch, - arm_insn_r->this_addr)); return -1; } } @@ -11088,10 +10128,6 @@ arm_record_extension_space (insn_decode_record *arm_insn_r) arm_insn_r->reg_rec_count = 2; /* Save SPSR also;how? */ - printf_unfiltered (_("Process record does not support " - "instruction 0x%0x at address %s.\n"), - arm_insn_r->arm_insn, - paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); return -1; } else if(8 == bits (arm_insn_r->arm_insn, 4, 7) @@ -11137,11 +10173,6 @@ arm_record_extension_space (insn_decode_record *arm_insn_r) { /* SPSR is going to be changed. */ /* we need to get SPSR value, which is yet to be done */ - printf_unfiltered (_("Process record does not support " - "instruction 0x%0x at address %s.\n"), - arm_insn_r->arm_insn, - paddress (arm_insn_r->gdbarch, - arm_insn_r->this_addr)); return -1; } } @@ -11218,10 +10249,7 @@ arm_record_extension_space (insn_decode_record *arm_insn_r) /* To be done for ARMv5 and later; as of now we return -1. */ if (-1 == ret) - printf_unfiltered (_("Process record does not support instruction x%0x " - "at address %s.\n"),arm_insn_r->arm_insn, - paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); - + return ret; REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); @@ -11238,8 +10266,7 @@ arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) uint32_t record_buf[8], record_buf_mem[8]; ULONGEST u_regval[2] = {0}; - uint32_t reg_src1 = 0, reg_src2 = 0, reg_dest = 0; - uint32_t immed_high = 0, immed_low = 0, offset_8 = 0, tgt_mem_addr = 0; + uint32_t reg_src1 = 0, reg_dest = 0; uint32_t opcode1 = 0; arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); @@ -11308,10 +10335,6 @@ arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) { /* SPSR is going to be changed. */ /* How to read SPSR value? */ - printf_unfiltered (_("Process record does not support instruction " - "0x%0x at address %s.\n"), - arm_insn_r->arm_insn, - paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); return -1; } } @@ -11367,10 +10390,6 @@ arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) arm_insn_r->reg_rec_count = 2; /* Save SPSR also; how? */ - printf_unfiltered (_("Process record does not support instruction " - "0x%0x at address %s.\n"),arm_insn_r->arm_insn, - paddress (arm_insn_r->gdbarch, - arm_insn_r->this_addr)); return -1; } else if (11 == arm_insn_r->decode @@ -11473,110 +10492,172 @@ arm_record_data_proc_imm (insn_decode_record *arm_insn_r) return 0; } -/* Handling opcode 010 insns. */ +static int +arm_record_media (insn_decode_record *arm_insn_r) +{ + uint32_t record_buf[8]; + + switch (bits (arm_insn_r->arm_insn, 22, 24)) + { + case 0: + /* Parallel addition and subtraction, signed */ + case 1: + /* Parallel addition and subtraction, unsigned */ + case 2: + case 3: + /* Packing, unpacking, saturation and reversal */ + { + int rd = bits (arm_insn_r->arm_insn, 12, 15); + + record_buf[arm_insn_r->reg_rec_count++] = rd; + } + break; + + case 4: + case 5: + /* Signed multiplies */ + { + int rd = bits (arm_insn_r->arm_insn, 16, 19); + unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 22); + + record_buf[arm_insn_r->reg_rec_count++] = rd; + if (op1 == 0x0) + record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; + else if (op1 == 0x4) + record_buf[arm_insn_r->reg_rec_count++] + = bits (arm_insn_r->arm_insn, 12, 15); + } + break; + + case 6: + { + if (bit (arm_insn_r->arm_insn, 21) + && bits (arm_insn_r->arm_insn, 5, 6) == 0x2) + { + /* SBFX */ + record_buf[arm_insn_r->reg_rec_count++] + = bits (arm_insn_r->arm_insn, 12, 15); + } + else if (bits (arm_insn_r->arm_insn, 20, 21) == 0x0 + && bits (arm_insn_r->arm_insn, 5, 7) == 0x0) + { + /* USAD8 and USADA8 */ + record_buf[arm_insn_r->reg_rec_count++] + = bits (arm_insn_r->arm_insn, 16, 19); + } + } + break; + + case 7: + { + if (bits (arm_insn_r->arm_insn, 20, 21) == 0x3 + && bits (arm_insn_r->arm_insn, 5, 7) == 0x7) + { + /* Permanently UNDEFINED */ + return -1; + } + else + { + /* BFC, BFI and UBFX */ + record_buf[arm_insn_r->reg_rec_count++] + = bits (arm_insn_r->arm_insn, 12, 15); + } + } + break; + + default: + return -1; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + + return 0; +} + +/* Handle ARM mode instructions with opcode 010. */ static int arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r) { struct regcache *reg_cache = arm_insn_r->regcache; - uint32_t reg_src1 = 0 , reg_dest = 0; - uint32_t offset_12 = 0, tgt_mem_addr = 0; + uint32_t reg_base , reg_dest; + uint32_t offset_12, tgt_mem_addr; uint32_t record_buf[8], record_buf_mem[8]; + unsigned char wback; + ULONGEST u_regval; - ULONGEST u_regval = 0; + /* Calculate wback. */ + wback = (bit (arm_insn_r->arm_insn, 24) == 0) + || (bit (arm_insn_r->arm_insn, 21) == 1); - arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); - arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); + arm_insn_r->reg_rec_count = 0; + reg_base = bits (arm_insn_r->arm_insn, 16, 19); if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) { + /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT + and LDRT. */ + reg_dest = bits (arm_insn_r->arm_insn, 12, 15); - /* LDR insn has a capability to do branching, if - MOV LR, PC is precedded by LDR insn having Rn as R15 - in that case, it emulates branch and link insn, and hence we - need to save CSPR and PC as well. */ - if (ARM_PC_REGNUM != reg_dest) - { - record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); - arm_insn_r->reg_rec_count = 1; - } - else - { - record_buf[0] = reg_dest; - record_buf[1] = ARM_PS_REGNUM; - arm_insn_r->reg_rec_count = 2; - } + record_buf[arm_insn_r->reg_rec_count++] = reg_dest; + + /* The LDR instruction is capable of doing branching. If MOV LR, PC + preceeds a LDR instruction having R15 as reg_base, it + emulates a branch and link instruction, and hence we need to save + CPSR and PC as well. */ + if (ARM_PC_REGNUM == reg_dest) + record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; + + /* If wback is true, also save the base register, which is going to be + written to. */ + if (wback) + record_buf[arm_insn_r->reg_rec_count++] = reg_base; } else { - /* Store, immediate offset, immediate pre-indexed, - immediate post-indexed. */ - reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); + /* STR (immediate), STRB (immediate), STRBT and STRT. */ + offset_12 = bits (arm_insn_r->arm_insn, 0, 11); - regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); - /* U == 1 */ + regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); + + /* Handle bit U. */ if (bit (arm_insn_r->arm_insn, 23)) - { - tgt_mem_addr = u_regval + offset_12; - } + { + /* U == 1: Add the offset. */ + tgt_mem_addr = (uint32_t) u_regval + offset_12; + } else - { - tgt_mem_addr = u_regval - offset_12; - } + { + /* U == 0: subtract the offset. */ + tgt_mem_addr = (uint32_t) u_regval - offset_12; + } + + /* Bit 22 tells us whether the store instruction writes 1 byte or 4 + bytes. */ + if (bit (arm_insn_r->arm_insn, 22)) + { + /* STRB and STRBT: 1 byte. */ + record_buf_mem[0] = 1; + } + else + { + /* STR and STRT: 4 bytes. */ + record_buf_mem[0] = 4; + } + + /* Handle bit P. */ + if (bit (arm_insn_r->arm_insn, 24)) + record_buf_mem[1] = tgt_mem_addr; + else + record_buf_mem[1] = (uint32_t) u_regval; - switch (arm_insn_r->opcode) - { - /* STR. */ - case 8: - case 12: - /* STR. */ - case 9: - case 13: - /* STRT. */ - case 1: - case 5: - /* STR. */ - case 4: - case 0: - record_buf_mem[0] = 4; - break; - - /* STRB. */ - case 10: - case 14: - /* STRB. */ - case 11: - case 15: - /* STRBT. */ - case 3: - case 7: - /* STRB. */ - case 2: - case 6: - record_buf_mem[0] = 1; - break; - - default: - gdb_assert_not_reached ("no decoding pattern found"); - break; - } - record_buf_mem[1] = tgt_mem_addr; arm_insn_r->mem_rec_count = 1; - if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode - || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode - || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode - || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode - || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode - || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode - ) - { - /* We are handling pre-indexed mode; post-indexed mode; - where Rn is going to be changed. */ - record_buf[0] = reg_src1; - arm_insn_r->reg_rec_count = 1; - } + /* If wback is true, also save the base register, which is going to be + written to. */ + if (wback) + record_buf[arm_insn_r->reg_rec_count++] = reg_base; } REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); @@ -11599,6 +10680,9 @@ arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) LONGEST s_word; ULONGEST u_regval[2]; + if (bit (arm_insn_r->arm_insn, 4)) + return arm_record_media (arm_insn_r); + arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); @@ -11843,137 +10927,415 @@ arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) } REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); - MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); + return 0; +} + +/* Handle ARM mode instructions with opcode 100. */ + +static int +arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) +{ + struct regcache *reg_cache = arm_insn_r->regcache; + uint32_t register_count = 0, register_bits; + uint32_t reg_base, addr_mode; + uint32_t record_buf[24], record_buf_mem[48]; + uint32_t wback; + ULONGEST u_regval; + + /* Fetch the list of registers. */ + register_bits = bits (arm_insn_r->arm_insn, 0, 15); + arm_insn_r->reg_rec_count = 0; + + /* Fetch the base register that contains the address we are loading data + to. */ + reg_base = bits (arm_insn_r->arm_insn, 16, 19); + + /* Calculate wback. */ + wback = (bit (arm_insn_r->arm_insn, 21) == 1); + + if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) + { + /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ + + /* Find out which registers are going to be loaded from memory. */ + while (register_bits) + { + if (register_bits & 0x00000001) + record_buf[arm_insn_r->reg_rec_count++] = register_count; + register_bits = register_bits >> 1; + register_count++; + } + + + /* If wback is true, also save the base register, which is going to be + written to. */ + if (wback) + record_buf[arm_insn_r->reg_rec_count++] = reg_base; + + /* Save the CPSR register. */ + record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; + } + else + { + /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ + + addr_mode = bits (arm_insn_r->arm_insn, 23, 24); + + regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); + + /* Find out how many registers are going to be stored to memory. */ + while (register_bits) + { + if (register_bits & 0x00000001) + register_count++; + register_bits = register_bits >> 1; + } + + switch (addr_mode) + { + /* STMDA (STMED): Decrement after. */ + case 0: + record_buf_mem[1] = (uint32_t) u_regval + - register_count * INT_REGISTER_SIZE + 4; + break; + /* STM (STMIA, STMEA): Increment after. */ + case 1: + record_buf_mem[1] = (uint32_t) u_regval; + break; + /* STMDB (STMFD): Decrement before. */ + case 2: + record_buf_mem[1] = (uint32_t) u_regval + - register_count * INT_REGISTER_SIZE; + break; + /* STMIB (STMFA): Increment before. */ + case 3: + record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE; + break; + default: + gdb_assert_not_reached ("no decoding pattern found"); + break; + } + + record_buf_mem[0] = register_count * INT_REGISTER_SIZE; + arm_insn_r->mem_rec_count = 1; + + /* If wback is true, also save the base register, which is going to be + written to. */ + if (wback) + record_buf[arm_insn_r->reg_rec_count++] = reg_base; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); + return 0; +} + +/* Handling opcode 101 insns. */ + +static int +arm_record_b_bl (insn_decode_record *arm_insn_r) +{ + uint32_t record_buf[8]; + + /* Handle B, BL, BLX(1) insns. */ + /* B simply branches so we do nothing here. */ + /* Note: BLX(1) doesnt fall here but instead it falls into + extension space. */ + if (bit (arm_insn_r->arm_insn, 24)) + { + record_buf[0] = ARM_LR_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + + return 0; +} + +static int +arm_record_unsupported_insn (insn_decode_record *arm_insn_r) +{ + printf_unfiltered (_("Process record does not support instruction " + "0x%0x at address %s.\n"),arm_insn_r->arm_insn, + paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); + + return -1; +} + +/* Record handler for vector data transfer instructions. */ + +static int +arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) +{ + uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; + uint32_t record_buf[4]; + + reg_t = bits (arm_insn_r->arm_insn, 12, 15); + reg_v = bits (arm_insn_r->arm_insn, 21, 23); + bits_a = bits (arm_insn_r->arm_insn, 21, 23); + bit_l = bit (arm_insn_r->arm_insn, 20); + bit_c = bit (arm_insn_r->arm_insn, 8); + + /* Handle VMOV instruction. */ + if (bit_l && bit_c) + { + record_buf[0] = reg_t; + arm_insn_r->reg_rec_count = 1; + } + else if (bit_l && !bit_c) + { + /* Handle VMOV instruction. */ + if (bits_a == 0x00) + { + record_buf[0] = reg_t; + arm_insn_r->reg_rec_count = 1; + } + /* Handle VMRS instruction. */ + else if (bits_a == 0x07) + { + if (reg_t == 15) + reg_t = ARM_PS_REGNUM; + + record_buf[0] = reg_t; + arm_insn_r->reg_rec_count = 1; + } + } + else if (!bit_l && !bit_c) + { + /* Handle VMOV instruction. */ + if (bits_a == 0x00) + { + record_buf[0] = ARM_D0_REGNUM + reg_v; + + arm_insn_r->reg_rec_count = 1; + } + /* Handle VMSR instruction. */ + else if (bits_a == 0x07) + { + record_buf[0] = ARM_FPSCR_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + } + else if (!bit_l && bit_c) + { + /* Handle VMOV instruction. */ + if (!(bits_a & 0x04)) + { + record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) + + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + /* Handle VDUP instruction. */ + else + { + if (bit (arm_insn_r->arm_insn, 21)) + { + reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); + record_buf[0] = reg_v + ARM_D0_REGNUM; + record_buf[1] = reg_v + ARM_D0_REGNUM + 1; + arm_insn_r->reg_rec_count = 2; + } + else + { + reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); + record_buf[0] = reg_v + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + } + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); return 0; } -/* Handling opcode 100 insns. */ +/* Record handler for extension register load/store instructions. */ static int -arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) +arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) { - struct regcache *reg_cache = arm_insn_r->regcache; + uint32_t opcode, single_reg; + uint8_t op_vldm_vstm; + uint32_t record_buf[8], record_buf_mem[128]; + ULONGEST u_regval = 0; - uint32_t register_list[16] = {0}, register_count = 0, register_bits = 0; - uint32_t reg_src1 = 0, addr_mode = 0, no_of_regs = 0; - uint32_t start_address = 0, index = 0; - uint32_t record_buf[24], record_buf_mem[48]; + struct regcache *reg_cache = arm_insn_r->regcache; - ULONGEST u_regval[2] = {0}; + opcode = bits (arm_insn_r->arm_insn, 20, 24); + single_reg = !bit (arm_insn_r->arm_insn, 8); + op_vldm_vstm = opcode & 0x1b; - /* This mode is exclusively for load and store multiple. */ - /* Handle incremenrt after/before and decrment after.before mode; - Rn is changing depending on W bit, but as of now we store Rn too - without optimization. */ + /* Handle VMOV instructions. */ + if ((opcode & 0x1e) == 0x04) + { + if (bit (arm_insn_r->arm_insn, 20)) /* to_arm_registers bit 20? */ + { + record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); + record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); + arm_insn_r->reg_rec_count = 2; + } + else + { + uint8_t reg_m = bits (arm_insn_r->arm_insn, 0, 3); + uint8_t bit_m = bit (arm_insn_r->arm_insn, 5); - if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) + if (single_reg) + { + /* The first S register number m is REG_M:M (M is bit 5), + the corresponding D register number is REG_M:M / 2, which + is REG_M. */ + record_buf[arm_insn_r->reg_rec_count++] = ARM_D0_REGNUM + reg_m; + /* The second S register number is REG_M:M + 1, the + corresponding D register number is (REG_M:M + 1) / 2. + IOW, if bit M is 1, the first and second S registers + are mapped to different D registers, otherwise, they are + in the same D register. */ + if (bit_m) + { + record_buf[arm_insn_r->reg_rec_count++] + = ARM_D0_REGNUM + reg_m + 1; + } + } + else + { + record_buf[0] = ((bit_m << 4) + reg_m + ARM_D0_REGNUM); + arm_insn_r->reg_rec_count = 1; + } + } + } + /* Handle VSTM and VPUSH instructions. */ + else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a + || op_vldm_vstm == 0x12) { - /* LDM (1,2,3) where LDM (3) changes CPSR too. */ + uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; + uint32_t memory_index = 0; - if (bit (arm_insn_r->arm_insn, 20) && !bit (arm_insn_r->arm_insn, 22)) - { - register_bits = bits (arm_insn_r->arm_insn, 0, 15); - no_of_regs = 15; - } + reg_rn = bits (arm_insn_r->arm_insn, 16, 19); + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); + imm_off32 = imm_off8 << 2; + memory_count = imm_off8; + + if (bit (arm_insn_r->arm_insn, 23)) + start_address = u_regval; else - { - register_bits = bits (arm_insn_r->arm_insn, 0, 14); - no_of_regs = 14; - } - /* Get Rn. */ - reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); - while (register_bits) - { - if (register_bits & 0x00000001) - record_buf[index++] = register_count; - register_bits = register_bits >> 1; - register_count++; - } + start_address = u_regval - imm_off32; - /* Extra space for Base Register and CPSR; wihtout optimization. */ - record_buf[index++] = reg_src1; - record_buf[index++] = ARM_PS_REGNUM; - arm_insn_r->reg_rec_count = index; + if (bit (arm_insn_r->arm_insn, 21)) + { + record_buf[0] = reg_rn; + arm_insn_r->reg_rec_count = 1; + } + + while (memory_count > 0) + { + if (single_reg) + { + record_buf_mem[memory_index] = 4; + record_buf_mem[memory_index + 1] = start_address; + start_address = start_address + 4; + memory_index = memory_index + 2; + } + else + { + record_buf_mem[memory_index] = 4; + record_buf_mem[memory_index + 1] = start_address; + record_buf_mem[memory_index + 2] = 4; + record_buf_mem[memory_index + 3] = start_address + 4; + start_address = start_address + 8; + memory_index = memory_index + 4; + } + memory_count--; + } + arm_insn_r->mem_rec_count = (memory_index >> 1); } - else + /* Handle VLDM instructions. */ + else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b + || op_vldm_vstm == 0x13) { - /* It handles both STM(1) and STM(2). */ - addr_mode = bits (arm_insn_r->arm_insn, 23, 24); + uint32_t reg_count, reg_vd; + uint32_t reg_index = 0; + uint32_t bit_d = bit (arm_insn_r->arm_insn, 22); - register_bits = bits (arm_insn_r->arm_insn, 0, 15); - /* Get Rn. */ - reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); - regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); - while (register_bits) - { - if (register_bits & 0x00000001) - register_count++; - register_bits = register_bits >> 1; - } + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + reg_count = bits (arm_insn_r->arm_insn, 0, 7); - switch (addr_mode) - { - /* Decrement after. */ - case 0: - start_address = (u_regval[0]) - (register_count * 4) + 4; - arm_insn_r->mem_rec_count = register_count; - while (register_count) - { - record_buf_mem[(register_count * 2) - 1] = start_address; - record_buf_mem[(register_count * 2) - 2] = 4; - start_address = start_address + 4; - register_count--; - } - break; - - /* Increment after. */ - case 1: - start_address = u_regval[0]; - arm_insn_r->mem_rec_count = register_count; - while (register_count) - { - record_buf_mem[(register_count * 2) - 1] = start_address; - record_buf_mem[(register_count * 2) - 2] = 4; - start_address = start_address + 4; - register_count--; - } - break; - - /* Decrement before. */ - case 2: - - start_address = (u_regval[0]) - (register_count * 4); - arm_insn_r->mem_rec_count = register_count; - while (register_count) - { - record_buf_mem[(register_count * 2) - 1] = start_address; - record_buf_mem[(register_count * 2) - 2] = 4; - start_address = start_address + 4; - register_count--; - } - break; - - /* Increment before. */ - case 3: - start_address = u_regval[0] + 4; - arm_insn_r->mem_rec_count = register_count; - while (register_count) - { - record_buf_mem[(register_count * 2) - 1] = start_address; - record_buf_mem[(register_count * 2) - 2] = 4; - start_address = start_address + 4; - register_count--; - } - break; - - default: - gdb_assert_not_reached ("no decoding pattern found"); - break; - } + /* REG_VD is the first D register number. If the instruction + loads memory to S registers (SINGLE_REG is TRUE), the register + number is (REG_VD << 1 | bit D), so the corresponding D + register number is (REG_VD << 1 | bit D) / 2 = REG_VD. */ + if (!single_reg) + reg_vd = reg_vd | (bit_d << 4); - /* Base register also changes; based on condition and W bit. */ - /* We save it anyway without optimization. */ - record_buf[0] = reg_src1; + if (bit (arm_insn_r->arm_insn, 21) /* write back */) + record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); + + /* If the instruction loads memory to D register, REG_COUNT should + be divided by 2, according to the ARM Architecture Reference + Manual. If the instruction loads memory to S register, divide by + 2 as well because two S registers are mapped to D register. */ + reg_count = reg_count / 2; + if (single_reg && bit_d) + { + /* Increase the register count if S register list starts from + an odd number (bit d is one). */ + reg_count++; + } + + while (reg_count > 0) + { + record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; + reg_count--; + } + arm_insn_r->reg_rec_count = reg_index; + } + /* VSTR Vector store register. */ + else if ((opcode & 0x13) == 0x10) + { + uint32_t start_address, reg_rn, imm_off32, imm_off8; + uint32_t memory_index = 0; + + reg_rn = bits (arm_insn_r->arm_insn, 16, 19); + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); + imm_off32 = imm_off8 << 2; + + if (bit (arm_insn_r->arm_insn, 23)) + start_address = u_regval + imm_off32; + else + start_address = u_regval - imm_off32; + + if (single_reg) + { + record_buf_mem[memory_index] = 4; + record_buf_mem[memory_index + 1] = start_address; + arm_insn_r->mem_rec_count = 1; + } + else + { + record_buf_mem[memory_index] = 4; + record_buf_mem[memory_index + 1] = start_address; + record_buf_mem[memory_index + 2] = 4; + record_buf_mem[memory_index + 3] = start_address + 4; + arm_insn_r->mem_rec_count = 2; + } + } + /* VLDR Vector load register. */ + else if ((opcode & 0x13) == 0x11) + { + uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + + if (!single_reg) + { + reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); + record_buf[0] = ARM_D0_REGNUM + reg_vd; + } + else + { + reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); + /* Record register D rather than pseudo register S. */ + record_buf[0] = ARM_D0_REGNUM + reg_vd / 2; + } arm_insn_r->reg_rec_count = 1; } @@ -11982,38 +11344,215 @@ arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) return 0; } -/* Handling opcode 101 insns. */ +/* Record handler for arm/thumb mode VFP data processing instructions. */ static int -arm_record_b_bl (insn_decode_record *arm_insn_r) +arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) { - uint32_t record_buf[8]; + uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; + uint32_t record_buf[4]; + enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; + enum insn_types curr_insn_type = INSN_INV; - /* Handle B, BL, BLX(1) insns. */ - /* B simply branches so we do nothing here. */ - /* Note: BLX(1) doesnt fall here but instead it falls into - extension space. */ - if (bit (arm_insn_r->arm_insn, 24)) - { - record_buf[0] = ARM_LR_REGNUM; - arm_insn_r->reg_rec_count = 1; - } + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + opc1 = bits (arm_insn_r->arm_insn, 20, 23); + opc2 = bits (arm_insn_r->arm_insn, 16, 19); + opc3 = bits (arm_insn_r->arm_insn, 6, 7); + dp_op_sz = bit (arm_insn_r->arm_insn, 8); + bit_d = bit (arm_insn_r->arm_insn, 22); + opc1 = opc1 & 0x04; - REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + /* Handle VMLA, VMLS. */ + if (opc1 == 0x00) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VNMLA, VNMLS, VNMUL. */ + else if (opc1 == 0x01) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VMUL. */ + else if (opc1 == 0x02 && !(opc3 & 0x01)) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VADD, VSUB. */ + else if (opc1 == 0x03) + { + if (!bit (arm_insn_r->arm_insn, 9)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VDIV. */ + else if (opc1 == 0x0b) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle all other vfp data processing instructions. */ + else if (opc1 == 0x0b) + { + /* Handle VMOV. */ + if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) + { + if (bit (arm_insn_r->arm_insn, 4)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VNEG and VABS. */ + else if ((opc2 == 0x01 && opc3 == 0x01) + || (opc2 == 0x00 && opc3 == 0x03)) + { + if (!bit (arm_insn_r->arm_insn, 11)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VSQRT. */ + else if (opc2 == 0x01 && opc3 == 0x03) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VCVT. */ + else if (opc2 == 0x07 && opc3 == 0x03) + { + if (!dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + else if (opc3 & 0x01) + { + /* Handle VCVT. */ + if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) + { + if (!bit (arm_insn_r->arm_insn, 18)) + curr_insn_type = INSN_T2; + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VCVT. */ + else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VCVTB, VCVTT. */ + else if ((opc2 & 0x0e) == 0x02) + curr_insn_type = INSN_T2; + /* Handle VCMP, VCMPE. */ + else if ((opc2 & 0x0e) == 0x04) + curr_insn_type = INSN_T3; + } + } - return 0; -} + switch (curr_insn_type) + { + case INSN_T0: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; + arm_insn_r->reg_rec_count = 2; + break; -/* Handling opcode 110 insns. */ + case INSN_T1: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; -static int -arm_record_unsupported_insn (insn_decode_record *arm_insn_r) -{ - printf_unfiltered (_("Process record does not support instruction " - "0x%0x at address %s.\n"),arm_insn_r->arm_insn, - paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr)); + case INSN_T2: + reg_vd = (reg_vd << 1) | bit_d; + record_buf[0] = reg_vd + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; - return -1; + case INSN_T3: + record_buf[0] = ARM_FPSCR_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + default: + gdb_assert_not_reached ("no decoding pattern found"); + break; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + return 0; } /* Handling opcode 110 insns. */ @@ -12021,7 +11560,7 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) static int arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) { - uint32_t op, op1, op1_sbit, op1_ebit, coproc; + uint32_t op1, op1_ebit, coproc; coproc = bits (arm_insn_r->arm_insn, 8, 11); op1 = bits (arm_insn_r->arm_insn, 20, 25); @@ -12031,11 +11570,11 @@ arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) { /* Handle extension register ld/st instructions. */ if (!(op1 & 0x20)) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_exreg_ld_st_insn (arm_insn_r); /* 64-bit transfers between arm core and extension registers. */ if ((op1 & 0x3e) == 0x04) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_exreg_ld_st_insn (arm_insn_r); } else { @@ -12078,7 +11617,6 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) uint32_t op, op1_sbit, op1_ebit, coproc; struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); struct regcache *reg_cache = arm_insn_r->regcache; - ULONGEST u_regval = 0; arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); coproc = bits (arm_insn_r->arm_insn, 8, 11); @@ -12113,11 +11651,11 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) { /* VFP data-processing instructions. */ if (!op1_sbit && !op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_vfp_data_proc_insn (arm_insn_r); /* Advanced SIMD, VFP instructions. */ if (!op1_sbit && op) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_vdata_transfer_insn (arm_insn_r); } else { @@ -12250,10 +11788,10 @@ thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r) } else { - /* Format 8; special data processing insns. */ - reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); - record_buf[0] = ARM_PS_REGNUM; - record_buf[1] = reg_src1; + /* Format 8; special data processing insns. */ + record_buf[0] = ARM_PS_REGNUM; + record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3 + | bits (thumb_insn_r->arm_insn, 0, 2)); thumb_insn_r->reg_rec_count = 2; } } @@ -12382,7 +11920,7 @@ thumb_record_misc (insn_decode_record *thumb_insn_r) uint32_t opcode = 0, opcode1 = 0, opcode2 = 0; uint32_t register_bits = 0, register_count = 0; - uint32_t register_list[8] = {0}, index = 0, start_address = 0; + uint32_t index = 0, start_address = 0; uint32_t record_buf[24], record_buf_mem[48]; uint32_t reg_src1; @@ -12484,7 +12022,7 @@ thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r) uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ uint32_t reg_src1 = 0; uint32_t opcode1 = 0, opcode2 = 0, register_bits = 0, register_count = 0; - uint32_t register_list[8] = {0}, index = 0, start_address = 0; + uint32_t index = 0, start_address = 0; uint32_t record_buf[24], record_buf_mem[48]; ULONGEST u_regval = 0; @@ -12696,7 +12234,6 @@ thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r) uint32_t address, offset_addr; uint32_t record_buf[8], record_buf_mem[8]; uint32_t op1, op2, op3; - LONGEST s_word; ULONGEST u_regval[2]; @@ -13011,7 +12548,6 @@ thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) static int thumb2_record_ld_word (insn_decode_record *thumb2_insn_r) { - uint32_t opcode1 = 0, opcode2 = 0; uint32_t record_buf[8]; record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15); @@ -13031,7 +12567,6 @@ thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) { uint32_t opcode1 = 0, opcode2 = 0; uint32_t record_buf[8]; - uint32_t reg_src1 = 0; opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22); opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7); @@ -13080,7 +12615,7 @@ thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) struct regcache *reg_cache = thumb2_insn_r->regcache; uint32_t l_bit, a_bit, b_bits; uint32_t record_buf[128], record_buf_mem[128]; - uint32_t reg_rn, reg_vd, address, f_esize, f_elem; + uint32_t reg_rn, reg_vd, address, f_elem; uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; uint8_t f_ebytes; @@ -13091,7 +12626,6 @@ thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); - f_esize = 8 * f_ebytes; f_elem = 8 / f_ebytes; if (!l_bit) @@ -13379,7 +12913,7 @@ extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size) return 1; insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0], insn_size, - gdbarch_byte_order (insn_record->gdbarch)); + gdbarch_byte_order_for_code (insn_record->gdbarch)); return 0; } @@ -13390,11 +12924,12 @@ typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*); static int decode_insn (insn_decode_record *arm_record, record_type_t record_type, - uint32_t insn_size) + uint32_t insn_size) { - /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */ - static const sti_arm_hdl_fp_t const arm_handle_insn[8] = + /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm + instruction. */ + static const sti_arm_hdl_fp_t arm_handle_insn[8] = { arm_record_data_proc_misc_ld_str, /* 000. */ arm_record_data_proc_imm, /* 001. */ @@ -13406,8 +12941,9 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type, arm_record_coproc_data_proc /* 111. */ }; - /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */ - static const sti_arm_hdl_fp_t const thumb_handle_insn[8] = + /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb + instruction. */ + static const sti_arm_hdl_fp_t thumb_handle_insn[8] = { \ thumb_record_shift_add_sub, /* 000. */ thumb_record_add_sub_cmp_mov, /* 001. */ @@ -13425,24 +12961,32 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type, if (extract_arm_insn (arm_record, insn_size)) { if (record_debug) - { - printf_unfiltered (_("Process record: error reading memory at " - "addr %s len = %d.\n"), - paddress (arm_record->gdbarch, arm_record->this_addr), insn_size); - } + { + printf_unfiltered (_("Process record: error reading memory at " + "addr %s len = %d.\n"), + paddress (arm_record->gdbarch, + arm_record->this_addr), insn_size); + } return -1; } else if (ARM_RECORD == record_type) { arm_record->cond = bits (arm_record->arm_insn, 28, 31); insn_id = bits (arm_record->arm_insn, 25, 27); - ret = arm_record_extension_space (arm_record); - /* If this insn has fallen into extension space - then we need not decode it anymore. */ - if (ret != -1 && !INSN_RECORDED(arm_record)) - { - ret = arm_handle_insn[insn_id] (arm_record); - } + + if (arm_record->cond == 0xf) + ret = arm_record_extension_space (arm_record); + else + { + /* If this insn has fallen into extension space + then we need not decode it anymore. */ + ret = arm_handle_insn[insn_id] (arm_record); + } + if (ret != ARM_RECORD_SUCCESS) + { + arm_record_unsupported_insn (arm_record); + ret = -1; + } } else if (THUMB_RECORD == record_type) { @@ -13450,6 +12994,11 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type, arm_record->cond = -1; insn_id = bits (arm_record->arm_insn, 13, 15); ret = thumb_handle_insn[insn_id] (arm_record); + if (ret != ARM_RECORD_SUCCESS) + { + arm_record_unsupported_insn (arm_record); + ret = -1; + } } else if (THUMB2_RECORD == record_type) { @@ -13458,15 +13007,15 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type, /* Swap first half of 32bit thumb instruction with second half. */ arm_record->arm_insn - = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); + = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16); - insn_id = thumb2_record_decode_insn_handler (arm_record); + ret = thumb2_record_decode_insn_handler (arm_record); - if (insn_id != ARM_RECORD_SUCCESS) - { - arm_record_unsupported_insn (arm_record); - ret = -1; - } + if (ret != ARM_RECORD_SUCCESS) + { + arm_record_unsupported_insn (arm_record); + ret = -1; + } } else { @@ -13488,16 +13037,15 @@ deallocate_reg_mem (insn_decode_record *record) } -/* Parse the current instruction and record the values of the registers and +/* Parse the current instruction and record the values of the registers and memory that will be changed in current instruction to record_arch_list". Return -1 if something is wrong. */ int -arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, - CORE_ADDR insn_addr) +arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, + CORE_ADDR insn_addr) { - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); uint32_t no_of_rec = 0; uint32_t ret = 0; /* return value: -1:record failure ; 0:success */ ULONGEST t_bit = 0, insn_id = 0; @@ -13515,19 +13063,19 @@ arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, if (record_debug > 1) { fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record " - "addr = %s\n", + "addr = %s\n", paddress (gdbarch, arm_record.this_addr)); } if (extract_arm_insn (&arm_record, 2)) { if (record_debug) - { - printf_unfiltered (_("Process record: error reading memory at " - "addr %s len = %d.\n"), - paddress (arm_record.gdbarch, - arm_record.this_addr), 2); - } + { + printf_unfiltered (_("Process record: error reading memory at " + "addr %s len = %d.\n"), + paddress (arm_record.gdbarch, + arm_record.this_addr), 2); + } return -1; } @@ -13547,15 +13095,15 @@ arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, insn_id = bits (arm_record.arm_insn, 11, 15); /* is it thumb2 insn? */ if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id)) - { - ret = decode_insn (&arm_record, THUMB2_RECORD, - THUMB2_INSN_SIZE_BYTES); - } + { + ret = decode_insn (&arm_record, THUMB2_RECORD, + THUMB2_INSN_SIZE_BYTES); + } else - { - /* We are decoding thumb insn. */ - ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES); - } + { + /* We are decoding thumb insn. */ + ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES); + } } if (0 == ret) @@ -13563,28 +13111,28 @@ arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, /* Record registers. */ record_full_arch_list_add_reg (arm_record.regcache, ARM_PC_REGNUM); if (arm_record.arm_regs) - { - for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) - { - if (record_full_arch_list_add_reg + { + for (no_of_rec = 0; no_of_rec < arm_record.reg_rec_count; no_of_rec++) + { + if (record_full_arch_list_add_reg (arm_record.regcache , arm_record.arm_regs[no_of_rec])) - ret = -1; - } - } + ret = -1; + } + } /* Record memories. */ if (arm_record.arm_mems) - { - for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) - { - if (record_full_arch_list_add_mem - ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, + { + for (no_of_rec = 0; no_of_rec < arm_record.mem_rec_count; no_of_rec++) + { + if (record_full_arch_list_add_mem + ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, arm_record.arm_mems[no_of_rec].len)) - ret = -1; - } - } + ret = -1; + } + } if (record_full_arch_list_add_end ()) - ret = -1; + ret = -1; } @@ -13592,4 +13140,3 @@ arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, return ret; } -