X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fd10v-tdep.c;h=3aab494e846948350fafd42fc1aff70cee62fc9b;hb=00d2865b835b1bba05334dcbb20201b6d99534d6;hp=7f6060337c86c54e7cebe4a6b53e7e5b73eb489a;hpb=7a292a7adf506b866905b06b3024c0fd411c4583;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/d10v-tdep.c b/gdb/d10v-tdep.c index 7f6060337c..3aab494e84 100644 --- a/gdb/d10v-tdep.c +++ b/gdb/d10v-tdep.c @@ -1,21 +1,22 @@ /* Target-dependent code for Mitsubishi D10V, for GDB. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc. -This file is part of GDB. + This file is part of GDB. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Contributed by Martin Hunt, hunt@cygnus.com */ @@ -29,21 +30,88 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "gdb_string.h" #include "value.h" #include "inferior.h" -#include "dis-asm.h" +#include "dis-asm.h" #include "symfile.h" #include "objfiles.h" +#include "language.h" +#include "arch-utils.h" -void d10v_frame_find_saved_regs PARAMS ((struct frame_info *fi, - struct frame_saved_regs *fsr)); +#include "floatformat.h" +#include "sim-d10v.h" + +#undef XMALLOC +#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE))) + +struct frame_extra_info + { + CORE_ADDR return_pc; + int frameless; + int size; + }; + +struct gdbarch_tdep + { + int a0_regnum; + int nr_dmap_regs; + unsigned long (*dmap_register) (int nr); + unsigned long (*imap_register) (int nr); + int (*register_sim_regno) (int nr); + }; + +/* These are the addresses the D10V-EVA board maps data and + instruction memory to. */ + +#define DMEM_START 0x2000000 +#define IMEM_START 0x1000000 +#define STACK_START 0x0007ffe + +/* d10v register names. */ + +enum + { + R0_REGNUM = 0, + LR_REGNUM = 13, + PSW_REGNUM = 16, + NR_IMAP_REGS = 2, + NR_A_REGS = 2 + }; +#define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) +#define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) + +/* d10v calling convention. */ + +#define ARG1_REGNUM R0_REGNUM +#define ARGN_REGNUM 3 +#define RET1_REGNUM R0_REGNUM + +/* Local functions */ + +extern void _initialize_d10v_tdep (void); + +static void d10v_eva_prepare_to_trace (void); + +static void d10v_eva_get_trace_data (void); + +static int prologue_find_regs (unsigned short op, struct frame_info *fi, + CORE_ADDR addr); + +extern void d10v_frame_init_saved_regs (struct frame_info *); + +static void do_d10v_pop_frame (struct frame_info *fi); int d10v_frame_chain_valid (chain, frame) CORE_ADDR chain; - struct frame_info *frame; /* not used here */ + struct frame_info *frame; /* not used here */ { return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START); } +static CORE_ADDR +d10v_stack_align (CORE_ADDR len) +{ + return (len + 1) & ~1; +} /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc @@ -61,51 +129,427 @@ d10v_use_struct_convention (gcc_p, type) } +unsigned char * +d10v_breakpoint_from_pc (pcptr, lenptr) + CORE_ADDR *pcptr; + int *lenptr; +{ + static unsigned char breakpoint[] = + {0x2f, 0x90, 0x5e, 0x00}; + *lenptr = sizeof (breakpoint); + return breakpoint; +} + +/* Map the REG_NR onto an ascii name. Return NULL or an empty string + when the reg_nr isn't valid. */ + +enum ts2_regnums + { + TS2_IMAP0_REGNUM = 32, + TS2_DMAP_REGNUM = 34, + TS2_NR_DMAP_REGS = 1, + TS2_A0_REGNUM = 35 + }; + +static char * +d10v_ts2_register_name (int reg_nr) +{ + static char *register_names[] = + { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", + "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", + "imap0", "imap1", "dmap", "a0", "a1" + }; + if (reg_nr < 0) + return NULL; + if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) + return NULL; + return register_names[reg_nr]; +} + +enum ts3_regnums + { + TS3_IMAP0_REGNUM = 36, + TS3_DMAP0_REGNUM = 38, + TS3_NR_DMAP_REGS = 4, + TS3_A0_REGNUM = 32 + }; + +static char * +d10v_ts3_register_name (int reg_nr) +{ + static char *register_names[] = + { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", + "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", + "a0", "a1", + "spi", "spu", + "imap0", "imap1", + "dmap0", "dmap1", "dmap2", "dmap3" + }; + if (reg_nr < 0) + return NULL; + if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) + return NULL; + return register_names[reg_nr]; +} + +/* Access the DMAP/IMAP registers in a target independant way. */ + +static unsigned long +d10v_ts2_dmap_register (int reg_nr) +{ + switch (reg_nr) + { + case 0: + case 1: + return 0x2000; + case 2: + return read_register (TS2_DMAP_REGNUM); + default: + return 0; + } +} + +static unsigned long +d10v_ts3_dmap_register (int reg_nr) +{ + return read_register (TS3_DMAP0_REGNUM + reg_nr); +} + +static unsigned long +d10v_dmap_register (int reg_nr) +{ + return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); +} + +static unsigned long +d10v_ts2_imap_register (int reg_nr) +{ + return read_register (TS2_IMAP0_REGNUM + reg_nr); +} + +static unsigned long +d10v_ts3_imap_register (int reg_nr) +{ + return read_register (TS3_IMAP0_REGNUM + reg_nr); +} + +static unsigned long +d10v_imap_register (int reg_nr) +{ + return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); +} + +/* MAP GDB's internal register numbering (determined by the layout fo + the REGISTER_BYTE array) onto the simulator's register + numbering. */ + +static int +d10v_ts2_register_sim_regno (int nr) +{ + if (nr >= TS2_IMAP0_REGNUM + && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) + return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; + if (nr == TS2_DMAP_REGNUM) + return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; + if (nr >= TS2_A0_REGNUM + && nr < TS2_A0_REGNUM + NR_A_REGS) + return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; + return nr; +} + +static int +d10v_ts3_register_sim_regno (int nr) +{ + if (nr >= TS3_IMAP0_REGNUM + && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) + return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; + if (nr >= TS3_DMAP0_REGNUM + && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) + return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; + if (nr >= TS3_A0_REGNUM + && nr < TS3_A0_REGNUM + NR_A_REGS) + return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; + return nr; +} + +int +d10v_register_sim_regno (int nr) +{ + return gdbarch_tdep (current_gdbarch)->register_sim_regno (nr); +} + +/* Index within `registers' of the first byte of the space for + register REG_NR. */ + +int +d10v_register_byte (reg_nr) + int reg_nr; +{ + if (reg_nr < A0_REGNUM) + return (reg_nr * 2); + else if (reg_nr < (A0_REGNUM + NR_A_REGS)) + return (A0_REGNUM * 2 + + (reg_nr - A0_REGNUM) * 8); + else + return (A0_REGNUM * 2 + + NR_A_REGS * 8 + + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); +} + +/* Number of bytes of storage in the actual machine representation for + register REG_NR. */ + +int +d10v_register_raw_size (reg_nr) + int reg_nr; +{ + if (reg_nr < A0_REGNUM) + return 2; + else if (reg_nr < (A0_REGNUM + NR_A_REGS)) + return 8; + else + return 2; +} + +/* Number of bytes of storage in the program's representation + for register N. */ + +int +d10v_register_virtual_size (reg_nr) + int reg_nr; +{ + return TYPE_LENGTH (REGISTER_VIRTUAL_TYPE (reg_nr)); +} + +/* Return the GDB type object for the "standard" data type + of data in register N. */ + +struct type * +d10v_register_virtual_type (reg_nr) + int reg_nr; +{ + if (reg_nr >= A0_REGNUM + && reg_nr < (A0_REGNUM + NR_A_REGS)) + return builtin_type_int64; + else if (reg_nr == PC_REGNUM + || reg_nr == SP_REGNUM) + return builtin_type_int32; + else + return builtin_type_int16; +} + +/* convert $pc and $sp to/from virtual addresses */ +int +d10v_register_convertible (nr) + int nr; +{ + return ((nr) == PC_REGNUM || (nr) == SP_REGNUM); +} + +void +d10v_register_convert_to_virtual (regnum, type, from, to) + int regnum; + struct type *type; + char *from; + char *to; +{ + ULONGEST x = extract_unsigned_integer (from, REGISTER_RAW_SIZE (regnum)); + if (regnum == PC_REGNUM) + x = (x << 2) | IMEM_START; + else + x |= DMEM_START; + store_unsigned_integer (to, TYPE_LENGTH (type), x); +} + +void +d10v_register_convert_to_raw (type, regnum, from, to) + struct type *type; + int regnum; + char *from; + char *to; +{ + ULONGEST x = extract_unsigned_integer (from, TYPE_LENGTH (type)); + x &= 0x3ffff; + if (regnum == PC_REGNUM) + x >>= 2; + store_unsigned_integer (to, 2, x); +} + + +CORE_ADDR +d10v_make_daddr (x) + CORE_ADDR x; +{ + return ((x) | DMEM_START); +} + +CORE_ADDR +d10v_make_iaddr (x) + CORE_ADDR x; +{ + return (((x) << 2) | IMEM_START); +} + +int +d10v_daddr_p (x) + CORE_ADDR x; +{ + return (((x) & 0x3000000) == DMEM_START); +} + +int +d10v_iaddr_p (x) + CORE_ADDR x; +{ + return (((x) & 0x3000000) == IMEM_START); +} + + +CORE_ADDR +d10v_convert_iaddr_to_raw (x) + CORE_ADDR x; +{ + return (((x) >> 2) & 0xffff); +} + +CORE_ADDR +d10v_convert_daddr_to_raw (x) + CORE_ADDR x; +{ + return ((x) & 0xffff); +} + +/* Store the address of the place in which to copy the structure the + subroutine will return. This is called from call_function. + + We store structs through a pointer passed in the first Argument + register. */ + +void +d10v_store_struct_return (addr, sp) + CORE_ADDR addr; + CORE_ADDR sp; +{ + write_register (ARG1_REGNUM, (addr)); +} + +/* Write into appropriate registers a function return value + of type TYPE, given in virtual format. + + Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ + +void +d10v_store_return_value (type, valbuf) + struct type *type; + char *valbuf; +{ + write_register_bytes (REGISTER_BYTE (RET1_REGNUM), + valbuf, + TYPE_LENGTH (type)); +} + +/* Extract from an array REGBUF containing the (raw) register state + the address in which a function should return its structure value, + as a CORE_ADDR (or an expression that can be used as one). */ + +CORE_ADDR +d10v_extract_struct_value_address (regbuf) + char *regbuf; +{ + return (extract_address ((regbuf) + REGISTER_BYTE (ARG1_REGNUM), + REGISTER_RAW_SIZE (ARG1_REGNUM)) + | DMEM_START); +} + +CORE_ADDR +d10v_frame_saved_pc (frame) + struct frame_info *frame; +{ + return ((frame)->extra_info->return_pc); +} + +CORE_ADDR +d10v_frame_args_address (fi) + struct frame_info *fi; +{ + return (fi)->frame; +} + +CORE_ADDR +d10v_frame_locals_address (fi) + struct frame_info *fi; +{ + return (fi)->frame; +} + +/* Immediately after a function call, return the saved pc. We can't + use frame->return_pc beause that is determined by reading R13 off + the stack and that may not be written yet. */ + +CORE_ADDR +d10v_saved_pc_after_call (frame) + struct frame_info *frame; +{ + return ((read_register (LR_REGNUM) << 2) + | IMEM_START); +} + /* Discard from the stack the innermost frame, restoring all saved registers. */ void -d10v_pop_frame (frame) - struct frame_info *frame; +d10v_pop_frame () +{ + generic_pop_current_frame (do_d10v_pop_frame); +} + +static void +do_d10v_pop_frame (fi) + struct frame_info *fi; { CORE_ADDR fp; int regnum; - struct frame_saved_regs fsr; char raw_buffer[8]; - fp = FRAME_FP (frame); + fp = FRAME_FP (fi); /* fill out fsr with the address of where each */ /* register was stored in the frame */ - get_frame_saved_regs (frame, &fsr); - + d10v_frame_init_saved_regs (fi); + /* now update the current registers with the old values */ - for (regnum = A0_REGNUM; regnum < A0_REGNUM+2 ; regnum++) + for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) { - if (fsr.regs[regnum]) + if (fi->saved_regs[regnum]) { - read_memory (fsr.regs[regnum], raw_buffer, REGISTER_RAW_SIZE(regnum)); - write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE(regnum)); + read_memory (fi->saved_regs[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); + write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE (regnum)); } } for (regnum = 0; regnum < SP_REGNUM; regnum++) { - if (fsr.regs[regnum]) + if (fi->saved_regs[regnum]) { - write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], REGISTER_RAW_SIZE(regnum))); + write_register (regnum, read_memory_unsigned_integer (fi->saved_regs[regnum], REGISTER_RAW_SIZE (regnum))); } } - if (fsr.regs[PSW_REGNUM]) + if (fi->saved_regs[PSW_REGNUM]) { - write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], REGISTER_RAW_SIZE(PSW_REGNUM))); + write_register (PSW_REGNUM, read_memory_unsigned_integer (fi->saved_regs[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); } write_register (PC_REGNUM, read_register (LR_REGNUM)); - write_register (SP_REGNUM, fp + frame->size); + write_register (SP_REGNUM, fp + fi->extra_info->size); target_store_registers (-1); flush_cached_frames (); } -static int +static int check_prologue (op) unsigned short op; { @@ -134,8 +578,8 @@ check_prologue (op) return 1; /* st2w rn, @sp */ - if ((op & 0x7E3F) == 0x3A1E) - return 1; + if ((op & 0x7E3F) == 0x3A1E) + return 1; return 0; } @@ -154,22 +598,22 @@ d10v_skip_prologue (pc) if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) { sal = find_pc_line (func_addr, 0); - if ( sal.end && sal.end < func_end) + if (sal.end && sal.end < func_end) return sal.end; } - - if (target_read_memory (pc, (char *)&op, 4)) + + if (target_read_memory (pc, (char *) &op, 4)) return pc; /* Can't access it -- assume no prologue. */ while (1) { - op = (unsigned long)read_memory_integer (pc, 4); + op = (unsigned long) read_memory_integer (pc, 4); if ((op & 0xC0000000) == 0xC0000000) { /* long instruction */ - if ( ((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ - ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ - ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ + if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ + ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ + ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ break; } else @@ -179,15 +623,15 @@ d10v_skip_prologue (pc) { op2 = (op & 0x3FFF8000) >> 15; op1 = op & 0x7FFF; - } - else + } + else { op1 = (op & 0x3FFF8000) >> 15; op2 = op & 0x7FFF; } - if (check_prologue(op1)) + if (check_prologue (op1)) { - if (!check_prologue(op2)) + if (!check_prologue (op2)) { /* if the previous opcode was really part of the prologue */ /* and not just a NOP, then we want to break after both instructions */ @@ -207,39 +651,41 @@ d10v_skip_prologue (pc) /* Given a GDB frame, determine the address of the calling function's frame. This will be used to create a new GDB frame struct, and then INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. -*/ + */ CORE_ADDR -d10v_frame_chain (frame) - struct frame_info *frame; +d10v_frame_chain (fi) + struct frame_info *fi; { - struct frame_saved_regs fsr; - - d10v_frame_find_saved_regs (frame, &fsr); + d10v_frame_init_saved_regs (fi); - if (frame->return_pc == IMEM_START || inside_entry_file(frame->return_pc)) - return (CORE_ADDR)0; + if (fi->extra_info->return_pc == IMEM_START + || inside_entry_file (fi->extra_info->return_pc)) + return (CORE_ADDR) 0; - if (!fsr.regs[FP_REGNUM]) + if (!fi->saved_regs[FP_REGNUM]) { - if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START) - return (CORE_ADDR)0; - - return fsr.regs[SP_REGNUM]; + if (!fi->saved_regs[SP_REGNUM] + || fi->saved_regs[SP_REGNUM] == STACK_START) + return (CORE_ADDR) 0; + + return fi->saved_regs[SP_REGNUM]; } - if (!read_memory_unsigned_integer(fsr.regs[FP_REGNUM], REGISTER_RAW_SIZE(FP_REGNUM))) - return (CORE_ADDR)0; + if (!read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], + REGISTER_RAW_SIZE (FP_REGNUM))) + return (CORE_ADDR) 0; - return D10V_MAKE_DADDR (read_memory_unsigned_integer (fsr.regs[FP_REGNUM], REGISTER_RAW_SIZE (FP_REGNUM))); -} + return D10V_MAKE_DADDR (read_memory_unsigned_integer (fi->saved_regs[FP_REGNUM], + REGISTER_RAW_SIZE (FP_REGNUM))); +} static int next_addr, uses_frame; -static int -prologue_find_regs (op, fsr, addr) +static int +prologue_find_regs (op, fi, addr) unsigned short op; - struct frame_saved_regs *fsr; + struct frame_info *fi; CORE_ADDR addr; { int n; @@ -249,7 +695,7 @@ prologue_find_regs (op, fsr, addr) { n = (op & 0x1E0) >> 5; next_addr -= 2; - fsr->regs[n] = next_addr; + fi->saved_regs[n] = next_addr; return 1; } @@ -258,8 +704,8 @@ prologue_find_regs (op, fsr, addr) { n = (op & 0x1E0) >> 5; next_addr -= 4; - fsr->regs[n] = next_addr; - fsr->regs[n+1] = next_addr+2; + fi->saved_regs[n] = next_addr; + fi->saved_regs[n + 1] = next_addr + 2; return 1; } @@ -288,7 +734,7 @@ prologue_find_regs (op, fsr, addr) if ((op & 0x7E1F) == 0x681E) { n = (op & 0x1E0) >> 5; - fsr->regs[n] = next_addr; + fi->saved_regs[n] = next_addr; return 1; } @@ -296,23 +742,23 @@ prologue_find_regs (op, fsr, addr) if ((op & 0x7E3F) == 0x3A1E) { n = (op & 0x1E0) >> 5; - fsr->regs[n] = next_addr; - fsr->regs[n+1] = next_addr+2; + fi->saved_regs[n] = next_addr; + fi->saved_regs[n + 1] = next_addr + 2; return 1; } return 0; } -/* Put here the code to store, into a struct frame_saved_regs, the - addresses of the saved registers of frame described by FRAME_INFO. - This includes special registers such as pc and fp saved in special - ways in the stack frame. sp is even more special: the address we - return for it IS the sp for the next frame. */ +/* Put here the code to store, into fi->saved_regs, the addresses of + the saved registers of frame described by FRAME_INFO. This + includes special registers such as pc and fp saved in special ways + in the stack frame. sp is even more special: the address we return + for it IS the sp for the next frame. */ + void -d10v_frame_find_saved_regs (fi, fsr) +d10v_frame_init_saved_regs (fi) struct frame_info *fi; - struct frame_saved_regs *fsr; { CORE_ADDR fp, pc; unsigned long op; @@ -320,7 +766,7 @@ d10v_frame_find_saved_regs (fi, fsr) int i; fp = fi->frame; - memset (fsr, 0, sizeof (*fsr)); + memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); next_addr = 0; pc = get_pc_function_start (fi->pc); @@ -328,7 +774,7 @@ d10v_frame_find_saved_regs (fi, fsr) uses_frame = 0; while (1) { - op = (unsigned long)read_memory_integer (pc, 4); + op = (unsigned long) read_memory_integer (pc, 4); if ((op & 0xC0000000) == 0xC0000000) { /* long instruction */ @@ -343,15 +789,15 @@ d10v_frame_find_saved_regs (fi, fsr) /* st rn, @(offset,sp) */ short offset = op & 0xFFFF; short n = (op >> 20) & 0xF; - fsr->regs[n] = next_addr + offset; + fi->saved_regs[n] = next_addr + offset; } else if ((op & 0x3F1F0000) == 0x350F0000) { /* st2w rn, @(offset,sp) */ short offset = op & 0xFFFF; short n = (op >> 20) & 0xF; - fsr->regs[n] = next_addr + offset; - fsr->regs[n+1] = next_addr + offset + 2; + fi->saved_regs[n] = next_addr + offset; + fi->saved_regs[n + 1] = next_addr + offset + 2; } else break; @@ -363,51 +809,51 @@ d10v_frame_find_saved_regs (fi, fsr) { op2 = (op & 0x3FFF8000) >> 15; op1 = op & 0x7FFF; - } - else + } + else { op1 = (op & 0x3FFF8000) >> 15; op2 = op & 0x7FFF; } - if (!prologue_find_regs(op1,fsr,pc) || !prologue_find_regs(op2,fsr,pc)) + if (!prologue_find_regs (op1, fi, pc) || !prologue_find_regs (op2, fi, pc)) break; } pc += 4; } - - fi->size = -next_addr; + + fi->extra_info->size = -next_addr; if (!(fp & 0xffff)) - fp = D10V_MAKE_DADDR (read_register(SP_REGNUM)); + fp = D10V_MAKE_DADDR (read_register (SP_REGNUM)); - for (i=0; iregs[i]) + for (i = 0; i < NUM_REGS - 1; i++) + if (fi->saved_regs[i]) { - fsr->regs[i] = fp - (next_addr - fsr->regs[i]); + fi->saved_regs[i] = fp - (next_addr - fi->saved_regs[i]); } - if (fsr->regs[LR_REGNUM]) + if (fi->saved_regs[LR_REGNUM]) { - CORE_ADDR return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); - fi->return_pc = D10V_MAKE_IADDR (return_pc); + CORE_ADDR return_pc = read_memory_unsigned_integer (fi->saved_regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); + fi->extra_info->return_pc = D10V_MAKE_IADDR (return_pc); } else { - fi->return_pc = D10V_MAKE_IADDR (read_register(LR_REGNUM)); + fi->extra_info->return_pc = D10V_MAKE_IADDR (read_register (LR_REGNUM)); } - + /* th SP is not normally (ever?) saved, but check anyway */ - if (!fsr->regs[SP_REGNUM]) + if (!fi->saved_regs[SP_REGNUM]) { /* if the FP was saved, that means the current FP is valid, */ /* otherwise, it isn't being used, so we use the SP instead */ if (uses_frame) - fsr->regs[SP_REGNUM] = read_register(FP_REGNUM) + fi->size; + fi->saved_regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->extra_info->size; else { - fsr->regs[SP_REGNUM] = fp + fi->size; - fi->frameless = 1; - fsr->regs[FP_REGNUM] = 0; + fi->saved_regs[SP_REGNUM] = fp + fi->extra_info->size; + fi->extra_info->frameless = 1; + fi->saved_regs[FP_REGNUM] = 0; } } } @@ -417,9 +863,13 @@ d10v_init_extra_frame_info (fromleaf, fi) int fromleaf; struct frame_info *fi; { - fi->frameless = 0; - fi->size = 0; - fi->return_pc = 0; + fi->extra_info = (struct frame_extra_info *) + frame_obstack_alloc (sizeof (struct frame_extra_info)); + frame_saved_regs_zalloc (fi); + + fi->extra_info->frameless = 0; + fi->extra_info->size = 0; + fi->extra_info->return_pc = 0; /* The call dummy doesn't save any registers on the stack, so we can return now. */ @@ -429,8 +879,7 @@ d10v_init_extra_frame_info (fromleaf, fi) } else { - struct frame_saved_regs dummy; - d10v_frame_find_saved_regs (fi, &dummy); + d10v_frame_init_saved_regs (fi); } } @@ -440,41 +889,54 @@ show_regs (args, from_tty) int from_tty; { int a; - printf_filtered ("PC=%04x (0x%x) PSW=%04x RPT_S=%04x RPT_E=%04x RPT_C=%04x\n", - read_register (PC_REGNUM), D10V_MAKE_IADDR (read_register (PC_REGNUM)), - read_register (PSW_REGNUM), - read_register (24), - read_register (25), - read_register (23)); - printf_filtered ("R0-R7 %04x %04x %04x %04x %04x %04x %04x %04x\n", - read_register (0), - read_register (1), - read_register (2), - read_register (3), - read_register (4), - read_register (5), - read_register (6), - read_register (7)); - printf_filtered ("R8-R15 %04x %04x %04x %04x %04x %04x %04x %04x\n", - read_register (8), - read_register (9), - read_register (10), - read_register (11), - read_register (12), - read_register (13), - read_register (14), - read_register (15)); - printf_filtered ("IMAP0 %04x IMAP1 %04x DMAP %04x\n", - read_register (IMAP0_REGNUM), - read_register (IMAP1_REGNUM), - read_register (DMAP_REGNUM)); - printf_filtered ("A0-A1"); - for (a = A0_REGNUM; a <= A0_REGNUM + 1; a++) + printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", + (long) read_register (PC_REGNUM), + (long) D10V_MAKE_IADDR (read_register (PC_REGNUM)), + (long) read_register (PSW_REGNUM), + (long) read_register (24), + (long) read_register (25), + (long) read_register (23)); + printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", + (long) read_register (0), + (long) read_register (1), + (long) read_register (2), + (long) read_register (3), + (long) read_register (4), + (long) read_register (5), + (long) read_register (6), + (long) read_register (7)); + printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", + (long) read_register (8), + (long) read_register (9), + (long) read_register (10), + (long) read_register (11), + (long) read_register (12), + (long) read_register (13), + (long) read_register (14), + (long) read_register (15)); + for (a = 0; a < NR_IMAP_REGS; a++) + { + if (a > 0) + printf_filtered (" "); + printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); + } + if (NR_DMAP_REGS == 1) + printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); + else + { + for (a = 0; a < NR_DMAP_REGS; a++) + { + printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); + } + printf_filtered ("\n"); + } + printf_filtered ("A0-A%d", NR_A_REGS - 1); + for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) { char num[MAX_REGISTER_RAW_SIZE]; int i; printf_filtered (" "); - read_register_gen (a, (char *)&num); + read_register_gen (a, (char *) &num); for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) { printf_filtered ("%02x", (num[i] & 0xff)); @@ -535,13 +997,13 @@ d10v_write_fp (val) CORE_ADDR d10v_read_fp () { - return (D10V_MAKE_DADDR (read_register(FP_REGNUM))); + return (D10V_MAKE_DADDR (read_register (FP_REGNUM))); } /* Function: push_return_address (pc) Set up the return address for the inferior function call. Needed for targets where we don't actually execute a JSR/BSR instruction */ - + CORE_ADDR d10v_push_return_address (pc, sp) CORE_ADDR pc; @@ -550,7 +1012,7 @@ d10v_push_return_address (pc, sp) write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ())); return sp; } - + /* When arguments must be pushed onto the stack, they go on in reverse order. The below implements a FILO (stack) to do this. */ @@ -562,7 +1024,8 @@ struct stack_item void *data; }; -static struct stack_item *push_stack_item PARAMS ((struct stack_item *prev, void *contents, int len)); +static struct stack_item *push_stack_item (struct stack_item *prev, + void *contents, int len); static struct stack_item * push_stack_item (prev, contents, len) struct stack_item *prev; @@ -578,7 +1041,7 @@ push_stack_item (prev, contents, len) return si; } -static struct stack_item *pop_stack_item PARAMS ((struct stack_item *si)); +static struct stack_item *pop_stack_item (struct stack_item *si); static struct stack_item * pop_stack_item (si) struct stack_item *si; @@ -602,7 +1065,7 @@ d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) int i; int regnum = ARG1_REGNUM; struct stack_item *si = NULL; - + /* Fill in registers and arg lists */ for (i = 0; i < nargs; i++) { @@ -639,7 +1102,7 @@ d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) { char ptr[2]; /* arg will go onto stack */ - store_address (ptr, val & 0xffff, 2); + store_address (ptr, 2, val & 0xffff); si = push_stack_item (si, ptr, 2); } } @@ -654,7 +1117,7 @@ d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) } else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) /* value fits in remaining registers, store keeping left - aligned */ + aligned */ { int b; regnum = aligned_regnum; @@ -672,7 +1135,7 @@ d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) else { /* arg will go onto stack */ - regnum = ARGN_REGNUM + 1; + regnum = ARGN_REGNUM + 1; si = push_stack_item (si, contents, len); } } @@ -684,7 +1147,7 @@ d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) write_memory (sp, si->data, si->len); si = pop_stack_item (si); } - + return sp; } @@ -708,15 +1171,15 @@ d10v_extract_return_value (type, regbuf, valbuf) int num; short snum; snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); - store_address ( valbuf, 4, D10V_MAKE_IADDR(snum)); + store_address (valbuf, 4, D10V_MAKE_IADDR (snum)); } - else if (TYPE_CODE(type) == TYPE_CODE_PTR) + else if (TYPE_CODE (type) == TYPE_CODE_PTR) { /* pointer to data */ int num; short snum; snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); - store_address ( valbuf, 4, D10V_MAKE_DADDR(snum)); + store_address (valbuf, 4, D10V_MAKE_DADDR (snum)); } else { @@ -731,15 +1194,36 @@ d10v_extract_return_value (type, regbuf, valbuf) else { /* For return values of odd size, the first byte is in the - least significant part of the first register. The - remaining bytes in remaining registers. Interestingly, - when such values are passed in, the last byte is in the - most significant byte of that same register - wierd. */ + least significant part of the first register. The + remaining bytes in remaining registers. Interestingly, + when such values are passed in, the last byte is in the + most significant byte of that same register - wierd. */ memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); } } } +/* Translate a GDB virtual ADDR/LEN into a format the remote target + understands. Returns number of bytes that can be transfered + starting at TARG_ADDR. Return ZERO if no bytes can be transfered + (segmentation fault). Since the simulator knows all about how the + VM system works, we just call that to do the translation. */ + +static void +remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, + CORE_ADDR *targ_addr, int *targ_len) +{ + long out_addr; + long out_len; + out_len = sim_d10v_translate_addr (memaddr, nr_bytes, + &out_addr, + d10v_dmap_register, + d10v_imap_register); + *targ_addr = out_addr; + *targ_len = out_len; +} + + /* The following code implements access to, and display of, the D10V's instruction trace buffer. The buffer consists of 64K or more 4-byte words of data, of which each words includes an 8-bit count, @@ -766,15 +1250,15 @@ d10v_extract_return_value (type, regbuf, valbuf) #define TRACE_BUFFER_BASE (0xf40000) -static void trace_command PARAMS ((char *, int)); +static void trace_command (char *, int); -static void untrace_command PARAMS ((char *, int)); +static void untrace_command (char *, int); -static void trace_info PARAMS ((char *, int)); +static void trace_info (char *, int); -static void tdisassemble_command PARAMS ((char *, int)); +static void tdisassemble_command (char *, int); -static void display_trace PARAMS ((int, int)); +static void display_trace (int, int); /* True when instruction traces are being collected. */ @@ -792,11 +1276,13 @@ static int trace_display; static int default_trace_show_source = 1; -struct trace_buffer { - int size; - short *counts; - CORE_ADDR *addrs; -} trace_data; +struct trace_buffer + { + int size; + short *counts; + CORE_ADDR *addrs; + } +trace_data; static void trace_command (args, from_tty) @@ -806,9 +1292,9 @@ trace_command (args, from_tty) /* Clear the host-side trace buffer, allocating space if needed. */ trace_data.size = 0; if (trace_data.counts == NULL) - trace_data.counts = (short *) xmalloc (65536 * sizeof(short)); + trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); if (trace_data.addrs == NULL) - trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof(CORE_ADDR)); + trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); tracing = 1; @@ -838,10 +1324,11 @@ trace_info (args, from_tty) for (i = 0; i < trace_data.size; ++i) { - printf_filtered ("%d: %d instruction%s at 0x%x\n", - i, trace_data.counts[i], + printf_filtered ("%d: %d instruction%s at 0x%s\n", + i, + trace_data.counts[i], (trace_data.counts[i] == 1 ? "" : "s"), - trace_data.addrs[i]); + paddr_nz (trace_data.addrs[i])); } } else @@ -856,11 +1343,11 @@ trace_info (args, from_tty) static int print_insn (memaddr, stream) CORE_ADDR memaddr; - GDB_FILE *stream; + struct ui_file *stream; { /* If there's no disassembler, something is very wrong. */ if (tm_print_insn == NULL) - abort (); + internal_error ("print_insn: no disassembler"); if (TARGET_BYTE_ORDER == BIG_ENDIAN) tm_print_insn_info.endian = BFD_ENDIAN_BIG; @@ -869,7 +1356,7 @@ print_insn (memaddr, stream) return (*tm_print_insn) (memaddr, &tm_print_insn_info); } -void +static void d10v_eva_prepare_to_trace () { if (!tracing) @@ -881,7 +1368,7 @@ d10v_eva_prepare_to_trace () /* Collect trace data from the target board and format it into a form more useful for display. */ -void +static void d10v_eva_get_trace_data () { int count, i, j, oldsize; @@ -892,7 +1379,7 @@ d10v_eva_get_trace_data () if (!tracing) return; - tmpspace = xmalloc (65536 * sizeof(unsigned int)); + tmpspace = xmalloc (65536 * sizeof (unsigned int)); last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; @@ -970,7 +1457,7 @@ tdisassemble_command (arg, from_tty) high = low; } - printf_filtered ("Dump of trace from %d to %d:\n", low, high); + printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); display_trace (low, high); @@ -986,7 +1473,7 @@ display_trace (low, high) CORE_ADDR next_address; trace_show_source = default_trace_show_source; - if (!have_full_symbols () && !have_partial_symbols()) + if (!have_full_symbols () && !have_partial_symbols ()) { trace_show_source = 0; printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); @@ -998,7 +1485,7 @@ display_trace (low, high) for (i = low; i < high; ++i) { next_address = trace_data.addrs[i]; - count = trace_data.counts[i]; + count = trace_data.counts[i]; while (count-- > 0) { QUIT; @@ -1020,7 +1507,7 @@ display_trace (low, high) if (!suppress) /* FIXME-32x64--assumes sal.pc fits in long. */ printf_filtered ("No source file for address %s.\n", - local_hex_string((unsigned long) sal.pc)); + local_hex_string ((unsigned long) sal.pc)); suppress = 1; } } @@ -1036,12 +1523,173 @@ display_trace (low, high) } } -extern void (*target_resume_hook) PARAMS ((void)); -extern void (*target_wait_loop_hook) PARAMS ((void)); + +static gdbarch_init_ftype d10v_gdbarch_init; + +static struct gdbarch * +d10v_gdbarch_init (info, arches) + struct gdbarch_info info; + struct gdbarch_list *arches; +{ + static LONGEST d10v_call_dummy_words[] = + {0}; + struct gdbarch *gdbarch; + int d10v_num_regs; + struct gdbarch_tdep *tdep; + gdbarch_register_name_ftype *d10v_register_name; + + /* Find a candidate among the list of pre-declared architectures. */ + arches = gdbarch_list_lookup_by_info (arches, &info); + if (arches != NULL) + return arches->gdbarch; + + /* None found, create a new architecture from the information + provided. */ + tdep = XMALLOC (struct gdbarch_tdep); + gdbarch = gdbarch_alloc (&info, tdep); + + switch (info.bfd_arch_info->mach) + { + case bfd_mach_d10v_ts2: + d10v_num_regs = 37; + d10v_register_name = d10v_ts2_register_name; + tdep->a0_regnum = TS2_A0_REGNUM; + tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; + tdep->register_sim_regno = d10v_ts2_register_sim_regno; + tdep->dmap_register = d10v_ts2_dmap_register; + tdep->imap_register = d10v_ts2_imap_register; + break; + default: + case bfd_mach_d10v_ts3: + d10v_num_regs = 42; + d10v_register_name = d10v_ts3_register_name; + tdep->a0_regnum = TS3_A0_REGNUM; + tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; + tdep->register_sim_regno = d10v_ts3_register_sim_regno; + tdep->dmap_register = d10v_ts3_dmap_register; + tdep->imap_register = d10v_ts3_imap_register; + break; + } + + set_gdbarch_read_pc (gdbarch, d10v_read_pc); + set_gdbarch_write_pc (gdbarch, d10v_write_pc); + set_gdbarch_read_fp (gdbarch, d10v_read_fp); + set_gdbarch_write_fp (gdbarch, d10v_write_fp); + set_gdbarch_read_sp (gdbarch, d10v_read_sp); + set_gdbarch_write_sp (gdbarch, d10v_write_sp); + + set_gdbarch_num_regs (gdbarch, d10v_num_regs); + set_gdbarch_sp_regnum (gdbarch, 15); + set_gdbarch_fp_regnum (gdbarch, 11); + set_gdbarch_pc_regnum (gdbarch, 18); + set_gdbarch_register_name (gdbarch, d10v_register_name); + set_gdbarch_register_size (gdbarch, 2); + set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); + set_gdbarch_register_byte (gdbarch, d10v_register_byte); + set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); + set_gdbarch_max_register_raw_size (gdbarch, 8); + set_gdbarch_register_virtual_size (gdbarch, d10v_register_virtual_size); + set_gdbarch_max_register_virtual_size (gdbarch, 8); + set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); + + set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); + set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); + set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_long_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); + /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long + double'' is 64 bits. */ + set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); + switch (info.byte_order) + { + case BIG_ENDIAN: + set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); + set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); + set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); + break; + case LITTLE_ENDIAN: + set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); + set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); + set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); + break; + default: + internal_error ("d10v_gdbarch_init: bad byte order for float format"); + } + + set_gdbarch_use_generic_dummy_frames (gdbarch, 1); + set_gdbarch_call_dummy_length (gdbarch, 0); + set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); + set_gdbarch_call_dummy_address (gdbarch, entry_point_address); + set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); + set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); + set_gdbarch_call_dummy_start_offset (gdbarch, 0); + set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); + set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); + set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); + set_gdbarch_call_dummy_p (gdbarch, 1); + set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); + set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); + set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); + + set_gdbarch_register_convertible (gdbarch, d10v_register_convertible); + set_gdbarch_register_convert_to_virtual (gdbarch, d10v_register_convert_to_virtual); + set_gdbarch_register_convert_to_raw (gdbarch, d10v_register_convert_to_raw); + + set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); + set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); + set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); + set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); + + set_gdbarch_d10v_make_daddr (gdbarch, d10v_make_daddr); + set_gdbarch_d10v_make_iaddr (gdbarch, d10v_make_iaddr); + set_gdbarch_d10v_daddr_p (gdbarch, d10v_daddr_p); + set_gdbarch_d10v_iaddr_p (gdbarch, d10v_iaddr_p); + set_gdbarch_d10v_convert_daddr_to_raw (gdbarch, d10v_convert_daddr_to_raw); + set_gdbarch_d10v_convert_iaddr_to_raw (gdbarch, d10v_convert_iaddr_to_raw); + + set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); + set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); + set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); + set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); + + set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); + set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); + + set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); + + set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); + set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + set_gdbarch_decr_pc_after_break (gdbarch, 4); + set_gdbarch_function_start_offset (gdbarch, 0); + set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); + + set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); + + set_gdbarch_frame_args_skip (gdbarch, 0); + set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); + set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); + set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); + set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); + set_gdbarch_frame_args_address (gdbarch, d10v_frame_args_address); + set_gdbarch_frame_locals_address (gdbarch, d10v_frame_locals_address); + set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); + set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); + set_gdbarch_stack_align (gdbarch, d10v_stack_align); + + return gdbarch; +} + + +extern void (*target_resume_hook) (void); +extern void (*target_wait_loop_hook) (void); void _initialize_d10v_tdep () { + register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); + tm_print_insn = print_insn_d10v; target_resume_hook = d10v_eva_prepare_to_trace; @@ -1049,27 +1697,27 @@ _initialize_d10v_tdep () add_com ("regs", class_vars, show_regs, "Print all registers"); - add_com ("trace", class_support, trace_command, + add_com ("itrace", class_support, trace_command, "Enable tracing of instruction execution."); - add_com ("untrace", class_support, untrace_command, + add_com ("iuntrace", class_support, untrace_command, "Disable tracing of instruction execution."); - add_com ("tdisassemble", class_vars, tdisassemble_command, + add_com ("itdisassemble", class_vars, tdisassemble_command, "Disassemble the trace buffer.\n\ Two optional arguments specify a range of trace buffer entries\n\ as reported by info trace (NOT addresses!)."); - add_info ("trace", trace_info, + add_info ("itrace", trace_info, "Display info about the trace data buffer."); - add_show_from_set (add_set_cmd ("tracedisplay", no_class, - var_integer, (char *)&trace_display, - "Set automatic display of trace.\n", &setlist), + add_show_from_set (add_set_cmd ("itracedisplay", no_class, + var_integer, (char *) &trace_display, + "Set automatic display of trace.\n", &setlist), &showlist); - add_show_from_set (add_set_cmd ("tracesource", no_class, - var_integer, (char *)&default_trace_show_source, - "Set display of source code with trace.\n", &setlist), + add_show_from_set (add_set_cmd ("itracesource", no_class, + var_integer, (char *) &default_trace_show_source, + "Set display of source code with trace.\n", &setlist), &showlist); -} +}