X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fi387-tdep.c;h=b8c342d22aaee73f8fea66b87d322b2e40c6e69d;hb=refs%2Fheads%2Fconcurrent-displaced-stepping-2020-04-01;hp=3fc344d590dfaf92fb15bc39eef16df6d7d56e65;hpb=b4d36fb80a261e933b7fdf0675fc98cbfb2d9c95;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c index 3fc344d590..b8c342d22a 100644 --- a/gdb/i387-tdep.c +++ b/gdb/i387-tdep.c @@ -1,7 +1,6 @@ /* Intel 387 floating point stuff. - Copyright (C) 1988-1989, 1991-1994, 1998-2005, 2007-2012 Free - Software Foundation, Inc. + Copyright (C) 1988-2020 Free Software Foundation, Inc. This file is part of GDB. @@ -19,21 +18,17 @@ along with this program. If not, see . */ #include "defs.h" -#include "doublest.h" -#include "floatformat.h" #include "frame.h" #include "gdbcore.h" #include "inferior.h" #include "language.h" #include "regcache.h" +#include "target-float.h" #include "value.h" -#include "gdb_assert.h" -#include "gdb_string.h" - #include "i386-tdep.h" #include "i387-tdep.h" -#include "i386-xstate.h" +#include "gdbsupport/x86-xstate.h" /* Print the floating point number specified by RAW. */ @@ -41,23 +36,13 @@ static void print_i387_value (struct gdbarch *gdbarch, const gdb_byte *raw, struct ui_file *file) { - DOUBLEST value; - - /* Using extract_typed_floating here might affect the representation - of certain numbers such as NaNs, even if GDB is running natively. - This is fine since our caller already detects such special - numbers and we print the hexadecimal representation anyway. */ - value = extract_typed_floating (raw, i387_ext_type (gdbarch)); - /* We try to print 19 digits. The last digit may or may not contain garbage, but we'd better print one too many. We need enough room to print the value, 1 position for the sign, 1 for the decimal point, 19 for the digits and 6 for the exponent adds up to 27. */ -#ifdef PRINTF_HAS_LONG_DOUBLE - fprintf_filtered (file, " %-+27.19Lg", (long double) value); -#else - fprintf_filtered (file, " %-+27.19g", (double) value); -#endif + const struct type *type = i387_ext_type (gdbarch); + std::string str = target_float_to_string (raw, type, " %-+27.19g"); + fprintf_filtered (file, "%s", str.c_str ()); } /* Print the classification for the register contents RAW. */ @@ -237,9 +222,7 @@ i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, ULONGEST fop; int fop_p; int fpreg; - int fpreg_p; int top; - int top_p; gdb_assert (gdbarch == get_frame_arch (frame)); @@ -301,7 +284,7 @@ i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, if (value_entirely_available (regval)) { - const char *raw = value_contents (regval); + const gdb_byte *raw = value_contents (regval); fputs_filtered ("0x", file); for (i = 9; i >= 0; i--) @@ -347,8 +330,9 @@ i387_convert_register_p (struct gdbarch *gdbarch, int regnum, if (i386_fp_regnum_p (gdbarch, regnum)) { /* Floating point registers must be converted unless we are - accessing them in their hardware type. */ - if (type == i387_ext_type (gdbarch)) + accessing them in their hardware type or TYPE is not float. */ + if (type == i387_ext_type (gdbarch) + || type->code () != TYPE_CODE_FLT) return 0; else return 1; @@ -371,7 +355,7 @@ i387_register_to_value (struct frame_info *frame, int regnum, gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); /* We only support floating-point values. */ - if (TYPE_CODE (type) != TYPE_CODE_FLT) + if (type->code () != TYPE_CODE_FLT) { warning (_("Cannot convert floating-point register value " "to non-floating-point type.")); @@ -380,11 +364,12 @@ i387_register_to_value (struct frame_info *frame, int regnum, } /* Convert to TYPE. */ - if (!get_frame_register_bytes (frame, regnum, 0, TYPE_LENGTH (type), + if (!get_frame_register_bytes (frame, regnum, 0, + register_size (gdbarch, regnum), from, optimizedp, unavailablep)) return 0; - convert_typed_floating (from, i387_ext_type (gdbarch), to, type); + target_float_convert (from, i387_ext_type (gdbarch), to, type); *optimizedp = *unavailablep = 0; return 1; } @@ -402,7 +387,7 @@ i387_value_to_register (struct frame_info *frame, int regnum, gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); /* We only support floating-point values. */ - if (TYPE_CODE (type) != TYPE_CODE_FLT) + if (type->code () != TYPE_CODE_FLT) { warning (_("Cannot convert non-floating-point type " "to floating-point register value.")); @@ -410,7 +395,7 @@ i387_value_to_register (struct frame_info *frame, int regnum, } /* Convert from TYPE. */ - convert_typed_floating (from, type, to, i387_ext_type (gdbarch)); + target_float_convert (from, type, to, i387_ext_type (gdbarch)); put_frame_register (frame, regnum, to); } @@ -452,10 +437,10 @@ static int fsave_offset[] = void i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - const gdb_byte *regs = fsave; + const gdb_byte *regs = (const gdb_byte *) fsave; int i; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); @@ -465,7 +450,7 @@ i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) { if (fsave == NULL) { - regcache_raw_supply (regcache, i, NULL); + regcache->raw_supply (i, NULL); continue; } @@ -480,22 +465,22 @@ i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) val[2] = val[3] = 0; if (i == I387_FOP_REGNUM (tdep)) val[1] &= ((1 << 3) - 1); - regcache_raw_supply (regcache, i, val); + regcache->raw_supply (i, val); } else - regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i)); + regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i)); } /* Provide dummy values for the SSE registers. */ for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) if (regnum == -1 || regnum == i) - regcache_raw_supply (regcache, i, NULL); + regcache->raw_supply (i, NULL); if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep)) { gdb_byte buf[4]; - store_unsigned_integer (buf, 4, byte_order, 0x1f80); - regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf); + store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); } } @@ -507,8 +492,8 @@ i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) void i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - gdb_byte *regs = fsave; + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + gdb_byte *regs = (gdb_byte *) fsave; int i; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); @@ -523,7 +508,7 @@ i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) { gdb_byte buf[4]; - regcache_raw_collect (regcache, i, buf); + regcache->raw_collect (i, buf); if (i == I387_FOP_REGNUM (tdep)) { @@ -535,7 +520,7 @@ i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2); } else - regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i)); + regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i)); } } @@ -600,8 +585,8 @@ static int i387_tag (const gdb_byte *raw); void i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - const gdb_byte *regs = fxsave; + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + const gdb_byte *regs = (const gdb_byte *) fxsave; int i; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); @@ -612,7 +597,7 @@ i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) { if (regs == NULL) { - regcache_raw_supply (regcache, i, NULL); + regcache->raw_supply (i, NULL); continue; } @@ -659,18 +644,18 @@ i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) val[0] = ftag & 0xff; val[1] = (ftag >> 8) & 0xff; } - regcache_raw_supply (regcache, i, val); + regcache->raw_supply (i, val); } else - regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); + regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); } if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) { if (regs == NULL) - regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL); + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL); else - regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), FXSAVE_MXCSR_ADDR (regs)); } } @@ -683,8 +668,8 @@ i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) void i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - gdb_byte *regs = fxsave; + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + gdb_byte *regs = (gdb_byte *) fxsave; int i; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); @@ -700,7 +685,7 @@ i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) { gdb_byte buf[4]; - regcache_raw_collect (regcache, i, buf); + regcache->raw_collect (i, buf); if (i == I387_FOP_REGNUM (tdep)) { @@ -731,11 +716,11 @@ i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); } else - regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i)); + regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i)); } if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) - regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep), + regcache->raw_collect (I387_MXCSR_REGNUM (tdep), FXSAVE_MXCSR_ADDR (regs)); } @@ -769,36 +754,228 @@ static int xsave_avxh_offset[] = #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) +/* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in + the upper 128bit of ZMM register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_ymm_avx512_offset[] = +{ + /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */ + 1664 + 16 + 0 * 64, /* %ymm16 through... */ + 1664 + 16 + 1 * 64, + 1664 + 16 + 2 * 64, + 1664 + 16 + 3 * 64, + 1664 + 16 + 4 * 64, + 1664 + 16 + 5 * 64, + 1664 + 16 + 6 * 64, + 1664 + 16 + 7 * 64, + 1664 + 16 + 8 * 64, + 1664 + 16 + 9 * 64, + 1664 + 16 + 10 * 64, + 1664 + 16 + 11 * 64, + 1664 + 16 + 12 * 64, + 1664 + 16 + 13 * 64, + 1664 + 16 + 14 * 64, + 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ +}; + +#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) + +static int xsave_xmm_avx512_offset[] = +{ + 1664 + 0 * 64, /* %ymm16 through... */ + 1664 + 1 * 64, + 1664 + 2 * 64, + 1664 + 3 * 64, + 1664 + 4 * 64, + 1664 + 5 * 64, + 1664 + 6 * 64, + 1664 + 7 * 64, + 1664 + 8 * 64, + 1664 + 9 * 64, + 1664 + 10 * 64, + 1664 + 11 * 64, + 1664 + 12 * 64, + 1664 + 13 * 64, + 1664 + 14 * 64, + 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */ +}; + +#define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)]) + +static int xsave_mpx_offset[] = { + 960 + 0 * 16, /* bnd0r...bnd3r registers. */ + 960 + 1 * 16, + 960 + 2 * 16, + 960 + 3 * 16, + 1024 + 0 * 8, /* bndcfg ... bndstatus. */ + 1024 + 1 * 8, +}; + +#define XSAVE_MPX_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)]) + + /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location + of the AVX512 opmask register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_avx512_k_offset[] = +{ + 1088 + 0 * 8, /* %k0 through... */ + 1088 + 1 * 8, + 1088 + 2 * 8, + 1088 + 3 * 8, + 1088 + 4 * 8, + 1088 + 5 * 8, + 1088 + 6 * 8, + 1088 + 7 * 8 /* %k7 (64 bits each). */ +}; + +#define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)]) + +/* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in + the upper 256bit of AVX512 ZMMH register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_avx512_zmm_h_offset[] = +{ + 1152 + 0 * 32, + 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */ + 1152 + 2 * 32, + 1152 + 3 * 32, + 1152 + 4 * 32, + 1152 + 5 * 32, + 1152 + 6 * 32, + 1152 + 7 * 32, + 1152 + 8 * 32, + 1152 + 9 * 32, + 1152 + 10 * 32, + 1152 + 11 * 32, + 1152 + 12 * 32, + 1152 + 13 * 32, + 1152 + 14 * 32, + 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */ + 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */ + 1664 + 32 + 1 * 64, + 1664 + 32 + 2 * 64, + 1664 + 32 + 3 * 64, + 1664 + 32 + 4 * 64, + 1664 + 32 + 5 * 64, + 1664 + 32 + 6 * 64, + 1664 + 32 + 7 * 64, + 1664 + 32 + 8 * 64, + 1664 + 32 + 9 * 64, + 1664 + 32 + 10 * 64, + 1664 + 32 + 11 * 64, + 1664 + 32 + 12 * 64, + 1664 + 32 + 13 * 64, + 1664 + 32 + 14 * 64, + 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */ +}; + +#define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)]) + +/* At xsave_pkeys_offset[REGNUM] you find the offset to the location + of the PKRU register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_pkeys_offset[] = +{ +2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by + instructions and applications). */ +}; + +#define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) + + +/* Extract from XSAVE a bitset of the features that are available on the + target, but which have not yet been enabled. */ + +ULONGEST +i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave) +{ + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + const gdb_byte *regs = (const gdb_byte *) xsave; + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */ + ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), + 8, byte_order); + + /* Clear part in vector registers if its bit in xstat_bv is zero. */ + ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0; + + return clear_bv; +} + /* Similar to i387_supply_fxsave, but use XSAVE extended state. */ void i387_supply_xsave (struct regcache *regcache, int regnum, const void *xsave) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - const gdb_byte *regs = xsave; + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + const gdb_byte *regs = (const gdb_byte *) xsave; int i; - unsigned int clear_bv; - static const gdb_byte zero[MAX_REGISTER_SIZE] = { 0 }; - const gdb_byte *p; + /* In 64-bit mode the split between "low" and "high" ZMM registers is at + ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all. + Precalculate the number to be used for the split point, with the all + registers in the "low" portion outside of 64-bit mode. */ + unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) + + std::min (tdep->num_zmm_regs, 16); + ULONGEST clear_bv; + static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 }; enum { none = 0x0, x87 = 0x1, sse = 0x2, avxh = 0x4, - all = x87 | sse | avxh + mpx = 0x8, + avx512_k = 0x10, + avx512_zmm_h = 0x20, + avx512_ymmh_avx512 = 0x40, + avx512_xmm_avx512 = 0x80, + pkeys = 0x100, + all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h + | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys } regclass; + gdb_assert (regs != NULL); gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); gdb_assert (tdep->num_xmm_regs > 0); if (regnum == -1) regclass = all; + else if (regnum >= I387_PKRU_REGNUM (tdep) + && regnum < I387_PKEYSEND_REGNUM (tdep)) + regclass = pkeys; + else if (regnum >= I387_ZMM0H_REGNUM (tdep) + && regnum < I387_ZMMENDH_REGNUM (tdep)) + regclass = avx512_zmm_h; + else if (regnum >= I387_K0_REGNUM (tdep) + && regnum < I387_KEND_REGNUM (tdep)) + regclass = avx512_k; + else if (regnum >= I387_YMM16H_REGNUM (tdep) + && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) + regclass = avx512_ymmh_avx512; + else if (regnum >= I387_XMM16_REGNUM (tdep) + && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) + regclass = avx512_xmm_avx512; else if (regnum >= I387_YMM0H_REGNUM (tdep) && regnum < I387_YMMENDH_REGNUM (tdep)) regclass = avxh; - else if (regnum >= I387_XMM0_REGNUM(tdep) + else if (regnum >= I387_BND0R_REGNUM (tdep) + && regnum < I387_MPXEND_REGNUM (tdep)) + regclass = mpx; + else if (regnum >= I387_XMM0_REGNUM (tdep) && regnum < I387_MXCSR_REGNUM (tdep)) regclass = sse; else if (regnum >= I387_ST0_REGNUM (tdep) @@ -807,17 +984,7 @@ i387_supply_xsave (struct regcache *regcache, int regnum, else regclass = none; - if (regs != NULL && regclass != none) - { - /* Get `xstat_bv'. */ - const gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs); - - /* The supported bits in `xstat_bv' are 1 byte. Clear part in - vector registers if its bit in xstat_bv is zero. */ - clear_bv = (~(*xstate_bv_p)) & tdep->xcr0; - } - else - clear_bv = I386_XSTATE_AVX_MASK; + clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave); /* With the delayed xsave mechanism, in between the program starting, and the program accessing the vector registers for the @@ -826,97 +993,253 @@ i387_supply_xsave (struct regcache *regcache, int regnum, time in a program. This means that from the user-space programs' perspective, it's the same as if the registers have always been zero from the start of the program. Therefore, the debugger - should provide the same illusion to the user. - - Note however, the case when REGS is NULL is a different case. - That case means we do not have access to the x87 states, so we - should mark the registers as unavailable (by supplying NULL). */ + should provide the same illusion to the user. */ switch (regclass) { case none: break; + case pkeys: + if ((clear_bv & X86_XSTATE_PKRU)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum)); + return; + + case avx512_zmm_h: + if ((clear_bv & (regnum < zmm_endlo_regnum ? X86_XSTATE_ZMM_H + : X86_XSTATE_ZMM))) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, + XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum)); + return; + + case avx512_k: + if ((clear_bv & X86_XSTATE_K)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, XSAVE_AVX512_K_ADDR (tdep, regs, regnum)); + return; + + case avx512_ymmh_avx512: + if ((clear_bv & X86_XSTATE_ZMM)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, + XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum)); + return; + + case avx512_xmm_avx512: + if ((clear_bv & X86_XSTATE_ZMM)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, + XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum)); + return; + case avxh: - if ((clear_bv & I386_XSTATE_AVX)) - regcache_raw_supply (regcache, regnum, regs == NULL ? NULL : zero); + if ((clear_bv & X86_XSTATE_AVX)) + regcache->raw_supply (regnum, zero); else - regcache_raw_supply (regcache, regnum, - XSAVE_AVXH_ADDR (tdep, regs, regnum)); + regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum)); + return; + + case mpx: + if ((clear_bv & X86_XSTATE_BNDREGS)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, XSAVE_MPX_ADDR (tdep, regs, regnum)); return; case sse: - if ((clear_bv & I386_XSTATE_SSE)) - regcache_raw_supply (regcache, regnum, regs == NULL ? NULL : zero); + if ((clear_bv & X86_XSTATE_SSE)) + regcache->raw_supply (regnum, zero); else - regcache_raw_supply (regcache, regnum, - FXSAVE_ADDR (tdep, regs, regnum)); + regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); return; case x87: - if ((clear_bv & I386_XSTATE_X87)) - regcache_raw_supply (regcache, regnum, regs == NULL ? NULL : zero); + if ((clear_bv & X86_XSTATE_X87)) + regcache->raw_supply (regnum, zero); else - regcache_raw_supply (regcache, regnum, - FXSAVE_ADDR (tdep, regs, regnum)); + regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); return; case all: + /* Handle PKEYS registers. */ + if ((tdep->xcr0 & X86_XSTATE_PKRU)) + { + if ((clear_bv & X86_XSTATE_PKRU)) + { + for (i = I387_PKRU_REGNUM (tdep); + i < I387_PKEYSEND_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_PKRU_REGNUM (tdep); + i < I387_PKEYSEND_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i)); + } + } + + /* Handle the upper halves of the low 8/16 ZMM registers. */ + if ((tdep->xcr0 & X86_XSTATE_ZMM_H)) + { + if ((clear_bv & X86_XSTATE_ZMM_H)) + { + for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) + regcache->raw_supply (i, + XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); + } + } + + /* Handle AVX512 OpMask registers. */ + if ((tdep->xcr0 & X86_XSTATE_K)) + { + if ((clear_bv & X86_XSTATE_K)) + { + for (i = I387_K0_REGNUM (tdep); + i < I387_KEND_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_K0_REGNUM (tdep); + i < I387_KEND_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i)); + } + } + + /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */ + if ((tdep->xcr0 & X86_XSTATE_ZMM)) + { + if ((clear_bv & X86_XSTATE_ZMM)) + { + for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) + regcache->raw_supply (i, zero); + for (i = I387_YMM16H_REGNUM (tdep); + i < I387_YMMH_AVX512_END_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + for (i = I387_XMM16_REGNUM (tdep); + i < I387_XMM_AVX512_END_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) + regcache->raw_supply (i, + XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); + for (i = I387_YMM16H_REGNUM (tdep); + i < I387_YMMH_AVX512_END_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i)); + for (i = I387_XMM16_REGNUM (tdep); + i < I387_XMM_AVX512_END_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i)); + } + } /* Handle the upper YMM registers. */ - if ((tdep->xcr0 & I386_XSTATE_AVX)) + if ((tdep->xcr0 & X86_XSTATE_AVX)) { - if ((clear_bv & I386_XSTATE_AVX)) + if ((clear_bv & X86_XSTATE_AVX)) { for (i = I387_YMM0H_REGNUM (tdep); i < I387_YMMENDH_REGNUM (tdep); i++) - regcache_raw_supply (regcache, i, regs == NULL ? NULL : zero); + regcache->raw_supply (i, zero); } else { for (i = I387_YMM0H_REGNUM (tdep); i < I387_YMMENDH_REGNUM (tdep); i++) - regcache_raw_supply (regcache, i, - XSAVE_AVXH_ADDR (tdep, regs, i)); + regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i)); + } + } + + /* Handle the MPX registers. */ + if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) + { + if (clear_bv & X86_XSTATE_BNDREGS) + { + for (i = I387_BND0R_REGNUM (tdep); + i < I387_BNDCFGU_REGNUM (tdep); i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_BND0R_REGNUM (tdep); + i < I387_BNDCFGU_REGNUM (tdep); i++) + regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); + } + } + + /* Handle the MPX registers. */ + if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) + { + if (clear_bv & X86_XSTATE_BNDCFG) + { + for (i = I387_BNDCFGU_REGNUM (tdep); + i < I387_MPXEND_REGNUM (tdep); i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_BNDCFGU_REGNUM (tdep); + i < I387_MPXEND_REGNUM (tdep); i++) + regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); } } /* Handle the XMM registers. */ - if ((tdep->xcr0 & I386_XSTATE_SSE)) + if ((tdep->xcr0 & X86_XSTATE_SSE)) { - if ((clear_bv & I386_XSTATE_SSE)) + if ((clear_bv & X86_XSTATE_SSE)) { for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) - regcache_raw_supply (regcache, i, regs == NULL ? NULL : zero); + regcache->raw_supply (i, zero); } else { for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) - regcache_raw_supply (regcache, i, - FXSAVE_ADDR (tdep, regs, i)); + regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); } } /* Handle the x87 registers. */ - if ((tdep->xcr0 & I386_XSTATE_X87)) + if ((tdep->xcr0 & X86_XSTATE_X87)) { - if ((clear_bv & I386_XSTATE_X87)) + if ((clear_bv & X86_XSTATE_X87)) { for (i = I387_ST0_REGNUM (tdep); i < I387_FCTRL_REGNUM (tdep); i++) - regcache_raw_supply (regcache, i, regs == NULL ? NULL : zero); + regcache->raw_supply (i, zero); } else { for (i = I387_ST0_REGNUM (tdep); i < I387_FCTRL_REGNUM (tdep); i++) - regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); + regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); } } break; @@ -926,16 +1249,30 @@ i387_supply_xsave (struct regcache *regcache, int regnum, for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) if (regnum == -1 || regnum == i) { - if (regs == NULL) + if (clear_bv & X86_XSTATE_X87) { - regcache_raw_supply (regcache, i, NULL); - continue; - } + if (i == I387_FCTRL_REGNUM (tdep)) + { + gdb_byte buf[4]; + + store_unsigned_integer (buf, 4, byte_order, + I387_FCTRL_INIT_VAL); + regcache->raw_supply (i, buf); + } + else if (i == I387_FTAG_REGNUM (tdep)) + { + gdb_byte buf[4]; + store_unsigned_integer (buf, 4, byte_order, 0xffff); + regcache->raw_supply (i, buf); + } + else + regcache->raw_supply (i, zero); + } /* Most of the FPU control registers occupy only 16 bits in the xsave extended state. Give those a special treatment. */ - if (i != I387_FIOFF_REGNUM (tdep) - && i != I387_FOOFF_REGNUM (tdep)) + else if (i != I387_FIOFF_REGNUM (tdep) + && i != I387_FOOFF_REGNUM (tdep)) { gdb_byte val[4]; @@ -943,7 +1280,7 @@ i387_supply_xsave (struct regcache *regcache, int regnum, val[2] = val[3] = 0; if (i == I387_FOP_REGNUM (tdep)) val[1] &= ((1 << 3) - 1); - else if (i== I387_FTAG_REGNUM (tdep)) + else if (i == I387_FTAG_REGNUM (tdep)) { /* The fxsave area contains a simplified version of the tag word. We have to look at the actual 80-bit @@ -975,16 +1312,27 @@ i387_supply_xsave (struct regcache *regcache, int regnum, val[0] = ftag & 0xff; val[1] = (ftag >> 8) & 0xff; } - regcache_raw_supply (regcache, i, val); + regcache->raw_supply (i, val); } - else - regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); + else + regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); } if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) { - p = regs == NULL ? NULL : FXSAVE_MXCSR_ADDR (regs); - regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), p); + /* The MXCSR register is placed into the xsave buffer if either the + AVX or SSE features are enabled. */ + if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) + == (X86_XSTATE_AVX | X86_XSTATE_SSE)) + { + gdb_byte buf[4]; + + store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); + } + else + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), + FXSAVE_MXCSR_ADDR (regs)); } } @@ -994,17 +1342,30 @@ void i387_collect_xsave (const struct regcache *regcache, int regnum, void *xsave, int gcore) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - gdb_byte *regs = xsave; - int i; + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + gdb_byte *p, *regs = (gdb_byte *) xsave; + gdb_byte raw[I386_MAX_REGISTER_SIZE]; + ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0; + unsigned int i; + /* See the comment in i387_supply_xsave(). */ + unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) + + std::min (tdep->num_zmm_regs, 16); enum { - none = 0x0, - check = 0x1, - x87 = 0x2 | check, - sse = 0x4 | check, - avxh = 0x8 | check, - all = x87 | sse | avxh + x87_ctrl_or_mxcsr = 0x1, + x87 = 0x2, + sse = 0x4, + avxh = 0x8, + mpx = 0x10, + avx512_k = 0x20, + avx512_zmm_h = 0x40, + avx512_ymmh_avx512 = 0x80, + avx512_xmm_avx512 = 0x100, + pkeys = 0x200, + all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h + | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys } regclass; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); @@ -1012,22 +1373,44 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, if (regnum == -1) regclass = all; + else if (regnum >= I387_PKRU_REGNUM (tdep) + && regnum < I387_PKEYSEND_REGNUM (tdep)) + regclass = pkeys; + else if (regnum >= I387_ZMM0H_REGNUM (tdep) + && regnum < I387_ZMMENDH_REGNUM (tdep)) + regclass = avx512_zmm_h; + else if (regnum >= I387_K0_REGNUM (tdep) + && regnum < I387_KEND_REGNUM (tdep)) + regclass = avx512_k; + else if (regnum >= I387_YMM16H_REGNUM (tdep) + && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) + regclass = avx512_ymmh_avx512; + else if (regnum >= I387_XMM16_REGNUM (tdep) + && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) + regclass = avx512_xmm_avx512; else if (regnum >= I387_YMM0H_REGNUM (tdep) && regnum < I387_YMMENDH_REGNUM (tdep)) regclass = avxh; - else if (regnum >= I387_XMM0_REGNUM(tdep) + else if (regnum >= I387_BND0R_REGNUM (tdep) + && regnum < I387_MPXEND_REGNUM (tdep)) + regclass = mpx; + else if (regnum >= I387_XMM0_REGNUM (tdep) && regnum < I387_MXCSR_REGNUM (tdep)) regclass = sse; else if (regnum >= I387_ST0_REGNUM (tdep) && regnum < I387_FCTRL_REGNUM (tdep)) regclass = x87; + else if ((regnum >= I387_FCTRL_REGNUM (tdep) + && regnum < I387_XMM0_REGNUM (tdep)) + || regnum == I387_MXCSR_REGNUM (tdep)) + regclass = x87_ctrl_or_mxcsr; else - regclass = none; + internal_error (__FILE__, __LINE__, _("invalid i387 regnum %d"), regnum); if (gcore) { /* Clear XSAVE extended state. */ - memset (regs, 0, I386_XSTATE_SIZE (tdep->xcr0)); + memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0)); /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */ if (tdep->xsave_xcr0_offset != -1) @@ -1035,149 +1418,387 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8); } - if ((regclass & check)) + /* The supported bits in `xstat_bv' are 8 bytes. */ + initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), + 8, byte_order); + clear_bv = (~(initial_xstate_bv)) & tdep->xcr0; + + /* The XSAVE buffer was filled lazily by the kernel. Only those + features that are enabled were written into the buffer, disabled + features left the buffer uninitialised. In order to identify if any + registers have changed we will be comparing the register cache + version to the version in the XSAVE buffer, it is important then that + at this point we initialise to the default values any features in + XSAVE that are not yet initialised. + + This could be made more efficient, we know which features (from + REGNUM) we will be potentially updating, and could limit ourselves to + only clearing that feature. However, the extra complexity does not + seem justified at this point. */ + if (clear_bv) { - gdb_byte raw[I386_MAX_REGISTER_SIZE]; - gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs); - unsigned int xstate_bv = 0; - /* The supported bits in `xstat_bv' are 1 byte. */ - unsigned int clear_bv = (~(*xstate_bv_p)) & tdep->xcr0; - gdb_byte *p; - - /* Clear register set if its bit in xstat_bv is zero. */ - if (clear_bv) + if ((clear_bv & X86_XSTATE_PKRU)) + for (i = I387_PKRU_REGNUM (tdep); + i < I387_PKEYSEND_REGNUM (tdep); i++) + memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4); + + if ((clear_bv & X86_XSTATE_BNDREGS)) + for (i = I387_BND0R_REGNUM (tdep); + i < I387_BNDCFGU_REGNUM (tdep); i++) + memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16); + + if ((clear_bv & X86_XSTATE_BNDCFG)) + for (i = I387_BNDCFGU_REGNUM (tdep); + i < I387_MPXEND_REGNUM (tdep); i++) + memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8); + + if ((clear_bv & X86_XSTATE_ZMM_H)) + for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) + memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); + + if ((clear_bv & X86_XSTATE_K)) + for (i = I387_K0_REGNUM (tdep); + i < I387_KEND_REGNUM (tdep); i++) + memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8); + + if ((clear_bv & X86_XSTATE_ZMM)) { - if ((clear_bv & I386_XSTATE_AVX)) - for (i = I387_YMM0H_REGNUM (tdep); - i < I387_YMMENDH_REGNUM (tdep); i++) - memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16); - - if ((clear_bv & I386_XSTATE_SSE)) - for (i = I387_XMM0_REGNUM (tdep); - i < I387_MXCSR_REGNUM (tdep); i++) - memset (FXSAVE_ADDR (tdep, regs, i), 0, 16); - - if ((clear_bv & I386_XSTATE_X87)) - for (i = I387_ST0_REGNUM (tdep); - i < I387_FCTRL_REGNUM (tdep); i++) - memset (FXSAVE_ADDR (tdep, regs, i), 0, 10); + for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) + memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); + for (i = I387_YMM16H_REGNUM (tdep); + i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) + memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16); + for (i = I387_XMM16_REGNUM (tdep); + i < I387_XMM_AVX512_END_REGNUM (tdep); i++) + memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16); } - if (regclass == all) + if ((clear_bv & X86_XSTATE_AVX)) + for (i = I387_YMM0H_REGNUM (tdep); + i < I387_YMMENDH_REGNUM (tdep); i++) + memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16); + + if ((clear_bv & X86_XSTATE_SSE)) + for (i = I387_XMM0_REGNUM (tdep); + i < I387_MXCSR_REGNUM (tdep); i++) + memset (FXSAVE_ADDR (tdep, regs, i), 0, 16); + + /* The mxcsr register is written into the xsave buffer if either AVX + or SSE is enabled, so only clear it if both of those features + require clearing. */ + if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) + == (X86_XSTATE_AVX | X86_XSTATE_SSE)) + store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order, + I387_MXCSR_INIT_VAL); + + if ((clear_bv & X86_XSTATE_X87)) { - /* Check if any upper YMM registers are changed. */ - if ((tdep->xcr0 & I386_XSTATE_AVX)) - for (i = I387_YMM0H_REGNUM (tdep); - i < I387_YMMENDH_REGNUM (tdep); i++) + for (i = I387_ST0_REGNUM (tdep); + i < I387_FCTRL_REGNUM (tdep); i++) + memset (FXSAVE_ADDR (tdep, regs, i), 0, 10); + + for (i = I387_FCTRL_REGNUM (tdep); + i < I387_XMM0_REGNUM (tdep); i++) + { + if (i == I387_FCTRL_REGNUM (tdep)) + store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2, + byte_order, I387_FCTRL_INIT_VAL); + else + memset (FXSAVE_ADDR (tdep, regs, i), 0, + regcache_register_size (regcache, i)); + } + } + } + + if (regclass == all) + { + /* Check if any PKEYS registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_PKRU)) + for (i = I387_PKRU_REGNUM (tdep); + i < I387_PKEYSEND_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_PKEYS_ADDR (tdep, regs, i); + if (memcmp (raw, p, 4) != 0) { - regcache_raw_collect (regcache, i, raw); - p = XSAVE_AVXH_ADDR (tdep, regs, i); - if (memcmp (raw, p, 16)) - { - xstate_bv |= I386_XSTATE_AVX; - memcpy (p, raw, 16); - } + xstate_bv |= X86_XSTATE_PKRU; + memcpy (p, raw, 4); } + } - /* Check if any SSE registers are changed. */ - if ((tdep->xcr0 & I386_XSTATE_SSE)) - for (i = I387_XMM0_REGNUM (tdep); - i < I387_MXCSR_REGNUM (tdep); i++) + /* Check if any ZMMH registers are changed. */ + if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) + for (i = I387_ZMM0H_REGNUM (tdep); + i < I387_ZMMENDH_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i); + if (memcmp (raw, p, 32) != 0) { - regcache_raw_collect (regcache, i, raw); - p = FXSAVE_ADDR (tdep, regs, i); - if (memcmp (raw, p, 16)) - { - xstate_bv |= I386_XSTATE_SSE; - memcpy (p, raw, 16); - } + xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); + memcpy (p, raw, 32); } + } - /* Check if any X87 registers are changed. */ - if ((tdep->xcr0 & I386_XSTATE_X87)) - for (i = I387_ST0_REGNUM (tdep); - i < I387_FCTRL_REGNUM (tdep); i++) + /* Check if any K registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_K)) + for (i = I387_K0_REGNUM (tdep); + i < I387_KEND_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_AVX512_K_ADDR (tdep, regs, i); + if (memcmp (raw, p, 8) != 0) { - regcache_raw_collect (regcache, i, raw); - p = FXSAVE_ADDR (tdep, regs, i); - if (memcmp (raw, p, 10)) - { - xstate_bv |= I386_XSTATE_X87; - memcpy (p, raw, 10); - } + xstate_bv |= X86_XSTATE_K; + memcpy (p, raw, 8); } - } - else - { - /* Check if REGNUM is changed. */ - regcache_raw_collect (regcache, regnum, raw); + } - switch (regclass) + /* Check if any XMM or upper YMM registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_ZMM)) + { + for (i = I387_YMM16H_REGNUM (tdep); + i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) { - default: - internal_error (__FILE__, __LINE__, - _("invalid i387 regclass")); - - case avxh: - /* This is an upper YMM register. */ - p = XSAVE_AVXH_ADDR (tdep, regs, regnum); - if (memcmp (raw, p, 16)) + regcache->raw_collect (i, raw); + p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16) != 0) { - xstate_bv |= I386_XSTATE_AVX; + xstate_bv |= X86_XSTATE_ZMM; memcpy (p, raw, 16); } - break; - - case sse: - /* This is an SSE register. */ - p = FXSAVE_ADDR (tdep, regs, regnum); - if (memcmp (raw, p, 16)) + } + for (i = I387_XMM16_REGNUM (tdep); + i < I387_XMM_AVX512_END_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16) != 0) { - xstate_bv |= I386_XSTATE_SSE; + xstate_bv |= X86_XSTATE_ZMM; memcpy (p, raw, 16); } - break; - - case x87: - /* This is an x87 register. */ - p = FXSAVE_ADDR (tdep, regs, regnum); - if (memcmp (raw, p, 10)) - { - xstate_bv |= I386_XSTATE_X87; - memcpy (p, raw, 10); - } - break; } } - /* Update the corresponding bits in `xstate_bv' if any SSE/AVX - registers are changed. */ - if (xstate_bv) - { - /* The supported bits in `xstat_bv' are 1 byte. */ - *xstate_bv_p |= (gdb_byte) xstate_bv; + /* Check if any upper MPX registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) + for (i = I387_BND0R_REGNUM (tdep); + i < I387_BNDCFGU_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_MPX_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_BNDREGS; + memcpy (p, raw, 16); + } + } + + /* Check if any upper MPX registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) + for (i = I387_BNDCFGU_REGNUM (tdep); + i < I387_MPXEND_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_MPX_ADDR (tdep, regs, i); + if (memcmp (raw, p, 8)) + { + xstate_bv |= X86_XSTATE_BNDCFG; + memcpy (p, raw, 8); + } + } + + /* Check if any upper YMM registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_AVX)) + for (i = I387_YMM0H_REGNUM (tdep); + i < I387_YMMENDH_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_AVXH_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_AVX; + memcpy (p, raw, 16); + } + } - switch (regclass) + /* Check if any SSE registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_SSE)) + for (i = I387_XMM0_REGNUM (tdep); + i < I387_MXCSR_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = FXSAVE_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_SSE; + memcpy (p, raw, 16); + } + } + + if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE)) + { + i = I387_MXCSR_REGNUM (tdep); + regcache->raw_collect (i, raw); + p = FXSAVE_MXCSR_ADDR (regs); + if (memcmp (raw, p, 4)) { - default: - internal_error (__FILE__, __LINE__, - _("invalid i387 regclass")); - - case all: - break; - - case x87: - case sse: - case avxh: - /* Register REGNUM has been updated. Return. */ - return; + /* Now, we need to mark one of either SSE of AVX as enabled. + We could pick either. What we do is check to see if one + of the features is already enabled, if it is then we leave + it at that, otherwise we pick SSE. */ + if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0) + xstate_bv |= X86_XSTATE_SSE; + memcpy (p, raw, 4); } } - else + + /* Check if any X87 registers are changed. Only the non-control + registers are handled here, the control registers are all handled + later on in this function. */ + if ((tdep->xcr0 & X86_XSTATE_X87)) + for (i = I387_ST0_REGNUM (tdep); + i < I387_FCTRL_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = FXSAVE_ADDR (tdep, regs, i); + if (memcmp (raw, p, 10)) + { + xstate_bv |= X86_XSTATE_X87; + memcpy (p, raw, 10); + } + } + } + else + { + /* Check if REGNUM is changed. */ + regcache->raw_collect (regnum, raw); + + switch (regclass) { - /* Return if REGNUM isn't changed. */ - if (regclass != all) - return; + default: + internal_error (__FILE__, __LINE__, + _("invalid i387 regclass")); + + case pkeys: + /* This is a PKEYS register. */ + p = XSAVE_PKEYS_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 4) != 0) + { + xstate_bv |= X86_XSTATE_PKRU; + memcpy (p, raw, 4); + } + break; + + case avx512_zmm_h: + /* This is a ZMM register. */ + p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 32) != 0) + { + xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); + memcpy (p, raw, 32); + } + break; + case avx512_k: + /* This is a AVX512 mask register. */ + p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 8) != 0) + { + xstate_bv |= X86_XSTATE_K; + memcpy (p, raw, 8); + } + break; + + case avx512_ymmh_avx512: + /* This is an upper YMM16-31 register. */ + p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16) != 0) + { + xstate_bv |= X86_XSTATE_ZMM; + memcpy (p, raw, 16); + } + break; + + case avx512_xmm_avx512: + /* This is an upper XMM16-31 register. */ + p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16) != 0) + { + xstate_bv |= X86_XSTATE_ZMM; + memcpy (p, raw, 16); + } + break; + + case avxh: + /* This is an upper YMM register. */ + p = XSAVE_AVXH_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_AVX; + memcpy (p, raw, 16); + } + break; + + case mpx: + if (regnum < I387_BNDCFGU_REGNUM (tdep)) + { + regcache->raw_collect (regnum, raw); + p = XSAVE_MPX_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_BNDREGS; + memcpy (p, raw, 16); + } + } + else + { + p = XSAVE_MPX_ADDR (tdep, regs, regnum); + xstate_bv |= X86_XSTATE_BNDCFG; + memcpy (p, raw, 8); + } + break; + + case sse: + /* This is an SSE register. */ + p = FXSAVE_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_SSE; + memcpy (p, raw, 16); + } + break; + + case x87: + /* This is an x87 register. */ + p = FXSAVE_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 10)) + { + xstate_bv |= X86_XSTATE_X87; + memcpy (p, raw, 10); + } + break; + + case x87_ctrl_or_mxcsr: + /* We only handle MXCSR here. All other x87 control registers + are handled separately below. */ + if (regnum == I387_MXCSR_REGNUM (tdep)) + { + p = FXSAVE_MXCSR_ADDR (regs); + if (memcmp (raw, p, 2)) + { + /* We're only setting MXCSR, so check the initial state + to see if either of AVX or SSE are already enabled. + If they are then we'll attribute this changed MXCSR to + that feature. If neither feature is enabled, then + we'll attribute this change to the SSE feature. */ + xstate_bv |= (initial_xstate_bv + & (X86_XSTATE_AVX | X86_XSTATE_SSE)); + if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0) + xstate_bv |= X86_XSTATE_SSE; + memcpy (p, raw, 2); + } + } } } @@ -1192,7 +1813,7 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, { gdb_byte buf[4]; - regcache_raw_collect (regcache, i, buf); + regcache->raw_collect (i, buf); if (i == I387_FOP_REGNUM (tdep)) { @@ -1220,15 +1841,38 @@ i387_collect_xsave (const struct regcache *regcache, int regnum, buf[0] |= (1 << fpreg); } } - memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); + p = FXSAVE_ADDR (tdep, regs, i); + if (memcmp (p, buf, 2)) + { + xstate_bv |= X86_XSTATE_X87; + memcpy (p, buf, 2); + } } else - regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i)); + { + int regsize; + + regcache->raw_collect (i, raw); + regsize = regcache_register_size (regcache, i); + p = FXSAVE_ADDR (tdep, regs, i); + if (memcmp (raw, p, regsize)) + { + xstate_bv |= X86_XSTATE_X87; + memcpy (p, raw, regsize); + } + } } - if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) - regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep), - FXSAVE_MXCSR_ADDR (regs)); + /* Update the corresponding bits in `xstate_bv' if any + registers are changed. */ + if (xstate_bv) + { + /* The supported bits in `xstat_bv' are 8 bytes. */ + initial_xstate_bv |= xstate_bv; + store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), + 8, byte_order, + initial_xstate_bv); + } } /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in @@ -1302,3 +1946,20 @@ i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache) regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); } + +/* See i387-tdep.h. */ + +void +i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + if (I387_BND0R_REGNUM (tdep) > 0) + { + gdb_byte bnd_buf[16]; + + memset (bnd_buf, 0, 16); + for (int i = 0; i < I387_NUM_BND_REGS; i++) + regcache->raw_write (I387_BND0R_REGNUM (tdep) + i, bnd_buf); + } +}