X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fi387-tdep.c;h=b8c342d22aaee73f8fea66b87d322b2e40c6e69d;hb=refs%2Fheads%2Fconcurrent-displaced-stepping-2020-04-01;hp=73a7797b0a90bcaba5e4a88d312bdd8fb7a4b06e;hpb=e071d1f67462901649858166f71b581ab22bf929;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/i387-tdep.c b/gdb/i387-tdep.c index 73a7797b0a..b8c342d22a 100644 --- a/gdb/i387-tdep.c +++ b/gdb/i387-tdep.c @@ -1,7 +1,6 @@ /* Intel 387 floating point stuff. - Copyright (C) 1988, 1989, 1991, 1992, 1993, 1994, 1998, 1999, 2000, 2001, - 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc. + Copyright (C) 1988-2020 Free Software Foundation, Inc. This file is part of GDB. @@ -19,49 +18,38 @@ along with this program. If not, see . */ #include "defs.h" -#include "doublest.h" -#include "floatformat.h" #include "frame.h" #include "gdbcore.h" #include "inferior.h" #include "language.h" #include "regcache.h" +#include "target-float.h" #include "value.h" -#include "gdb_assert.h" -#include "gdb_string.h" - #include "i386-tdep.h" #include "i387-tdep.h" +#include "gdbsupport/x86-xstate.h" /* Print the floating point number specified by RAW. */ static void -print_i387_value (const gdb_byte *raw, struct ui_file *file) +print_i387_value (struct gdbarch *gdbarch, + const gdb_byte *raw, struct ui_file *file) { - DOUBLEST value; - - /* Using extract_typed_floating here might affect the representation - of certain numbers such as NaNs, even if GDB is running natively. - This is fine since our caller already detects such special - numbers and we print the hexadecimal representation anyway. */ - value = extract_typed_floating (raw, builtin_type_i387_ext); - /* We try to print 19 digits. The last digit may or may not contain garbage, but we'd better print one too many. We need enough room to print the value, 1 position for the sign, 1 for the decimal point, 19 for the digits and 6 for the exponent adds up to 27. */ -#ifdef PRINTF_HAS_LONG_DOUBLE - fprintf_filtered (file, " %-+27.19Lg", (long double) value); -#else - fprintf_filtered (file, " %-+27.19g", (double) value); -#endif + const struct type *type = i387_ext_type (gdbarch); + std::string str = target_float_to_string (raw, type, " %-+27.19g"); + fprintf_filtered (file, "%s", str.c_str ()); } /* Print the classification for the register contents RAW. */ static void -print_i387_ext (const gdb_byte *raw, struct ui_file *file) +print_i387_ext (struct gdbarch *gdbarch, + const gdb_byte *raw, struct ui_file *file) { int sign; int integer; @@ -92,11 +80,11 @@ print_i387_ext (const gdb_byte *raw, struct ui_file *file) } else if (exponent < 0x7fff && exponent > 0x0000 && integer) /* Normal. */ - print_i387_value (raw, file); + print_i387_value (gdbarch, raw, file); else if (exponent == 0x0000) { /* Denormal or zero. */ - print_i387_value (raw, file); + print_i387_value (gdbarch, raw, file); if (integer) /* Pseudo-denormal. */ @@ -110,13 +98,21 @@ print_i387_ext (const gdb_byte *raw, struct ui_file *file) fputs_filtered (" Unsupported", file); } -/* Print the status word STATUS. */ +/* Print the status word STATUS. If STATUS_P is false, then STATUS + was unavailable. */ static void -print_i387_status_word (unsigned int status, struct ui_file *file) +print_i387_status_word (int status_p, + unsigned int status, struct ui_file *file) { - fprintf_filtered (file, "Status Word: %s", - hex_string_custom (status, 4)); + fprintf_filtered (file, "Status Word: "); + if (!status_p) + { + fprintf_filtered (file, "%s\n", _("")); + return; + } + + fprintf_filtered (file, "%s", hex_string_custom (status, 4)); fputs_filtered (" ", file); fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " "); fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " "); @@ -140,13 +136,21 @@ print_i387_status_word (unsigned int status, struct ui_file *file) " TOP: %d\n", ((status >> 11) & 7)); } -/* Print the control word CONTROL. */ +/* Print the control word CONTROL. If CONTROL_P is false, then + CONTROL was unavailable. */ static void -print_i387_control_word (unsigned int control, struct ui_file *file) +print_i387_control_word (int control_p, + unsigned int control, struct ui_file *file) { - fprintf_filtered (file, "Control Word: %s", - hex_string_custom (control, 4)); + fprintf_filtered (file, "Control Word: "); + if (!control_p) + { + fprintf_filtered (file, "%s\n", _("")); + return; + } + + fprintf_filtered (file, "%s", hex_string_custom (control, 4)); fputs_filtered (" ", file); fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " "); fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " "); @@ -201,113 +205,173 @@ i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, struct frame_info *frame, const char *args) { struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); - gdb_byte buf[4]; ULONGEST fctrl; + int fctrl_p; ULONGEST fstat; + int fstat_p; ULONGEST ftag; + int ftag_p; ULONGEST fiseg; + int fiseg_p; ULONGEST fioff; + int fioff_p; ULONGEST foseg; + int foseg_p; ULONGEST fooff; + int fooff_p; ULONGEST fop; + int fop_p; int fpreg; int top; gdb_assert (gdbarch == get_frame_arch (frame)); - /* Define I387_ST0_REGNUM such that we use the proper definitions - for FRAME's architecture. */ -#define I387_ST0_REGNUM tdep->st0_regnum - - fctrl = get_frame_register_unsigned (frame, I387_FCTRL_REGNUM); - fstat = get_frame_register_unsigned (frame, I387_FSTAT_REGNUM); - ftag = get_frame_register_unsigned (frame, I387_FTAG_REGNUM); - fiseg = get_frame_register_unsigned (frame, I387_FISEG_REGNUM); - fioff = get_frame_register_unsigned (frame, I387_FIOFF_REGNUM); - foseg = get_frame_register_unsigned (frame, I387_FOSEG_REGNUM); - fooff = get_frame_register_unsigned (frame, I387_FOOFF_REGNUM); - fop = get_frame_register_unsigned (frame, I387_FOP_REGNUM); - - top = ((fstat >> 11) & 7); - - for (fpreg = 7; fpreg >= 0; fpreg--) + fctrl_p = read_frame_register_unsigned (frame, + I387_FCTRL_REGNUM (tdep), &fctrl); + fstat_p = read_frame_register_unsigned (frame, + I387_FSTAT_REGNUM (tdep), &fstat); + ftag_p = read_frame_register_unsigned (frame, + I387_FTAG_REGNUM (tdep), &ftag); + fiseg_p = read_frame_register_unsigned (frame, + I387_FISEG_REGNUM (tdep), &fiseg); + fioff_p = read_frame_register_unsigned (frame, + I387_FIOFF_REGNUM (tdep), &fioff); + foseg_p = read_frame_register_unsigned (frame, + I387_FOSEG_REGNUM (tdep), &foseg); + fooff_p = read_frame_register_unsigned (frame, + I387_FOOFF_REGNUM (tdep), &fooff); + fop_p = read_frame_register_unsigned (frame, + I387_FOP_REGNUM (tdep), &fop); + + if (fstat_p) { - gdb_byte raw[I386_MAX_REGISTER_SIZE]; - int tag = (ftag >> (fpreg * 2)) & 3; - int i; - - fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg); + top = ((fstat >> 11) & 7); - switch (tag) + for (fpreg = 7; fpreg >= 0; fpreg--) { - case 0: - fputs_filtered ("Valid ", file); - break; - case 1: - fputs_filtered ("Zero ", file); - break; - case 2: - fputs_filtered ("Special ", file); - break; - case 3: - fputs_filtered ("Empty ", file); - break; + struct value *regval; + int regnum; + int i; + int tag = -1; + + fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg); + + if (ftag_p) + { + tag = (ftag >> (fpreg * 2)) & 3; + + switch (tag) + { + case 0: + fputs_filtered ("Valid ", file); + break; + case 1: + fputs_filtered ("Zero ", file); + break; + case 2: + fputs_filtered ("Special ", file); + break; + case 3: + fputs_filtered ("Empty ", file); + break; + } + } + else + fputs_filtered ("Unknown ", file); + + regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep); + regval = get_frame_register_value (frame, regnum); + + if (value_entirely_available (regval)) + { + const gdb_byte *raw = value_contents (regval); + + fputs_filtered ("0x", file); + for (i = 9; i >= 0; i--) + fprintf_filtered (file, "%02x", raw[i]); + + if (tag != -1 && tag != 3) + print_i387_ext (gdbarch, raw, file); + } + else + fprintf_filtered (file, "%s", _("")); + + fputs_filtered ("\n", file); } - - get_frame_register (frame, (fpreg + 8 - top) % 8 + I387_ST0_REGNUM, raw); - - fputs_filtered ("0x", file); - for (i = 9; i >= 0; i--) - fprintf_filtered (file, "%02x", raw[i]); - - if (tag != 3) - print_i387_ext (raw, file); - - fputs_filtered ("\n", file); } fputs_filtered ("\n", file); - - print_i387_status_word (fstat, file); - print_i387_control_word (fctrl, file); + print_i387_status_word (fstat_p, fstat, file); + print_i387_control_word (fctrl_p, fctrl, file); fprintf_filtered (file, "Tag Word: %s\n", - hex_string_custom (ftag, 4)); + ftag_p ? hex_string_custom (ftag, 4) : _("")); fprintf_filtered (file, "Instruction Pointer: %s:", - hex_string_custom (fiseg, 2)); - fprintf_filtered (file, "%s\n", hex_string_custom (fioff, 8)); + fiseg_p ? hex_string_custom (fiseg, 2) : _("")); + fprintf_filtered (file, "%s\n", + fioff_p ? hex_string_custom (fioff, 8) : _("")); fprintf_filtered (file, "Operand Pointer: %s:", - hex_string_custom (foseg, 2)); - fprintf_filtered (file, "%s\n", hex_string_custom (fooff, 8)); + foseg_p ? hex_string_custom (foseg, 2) : _("")); + fprintf_filtered (file, "%s\n", + fooff_p ? hex_string_custom (fooff, 8) : _("")); fprintf_filtered (file, "Opcode: %s\n", - hex_string_custom (fop ? (fop | 0xd800) : 0, 4)); - -#undef I387_ST0_REGNUM + fop_p + ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4)) + : _("")); } +/* Return nonzero if a value of type TYPE stored in register REGNUM + needs any special handling. */ + +int +i387_convert_register_p (struct gdbarch *gdbarch, int regnum, + struct type *type) +{ + if (i386_fp_regnum_p (gdbarch, regnum)) + { + /* Floating point registers must be converted unless we are + accessing them in their hardware type or TYPE is not float. */ + if (type == i387_ext_type (gdbarch) + || type->code () != TYPE_CODE_FLT) + return 0; + else + return 1; + } + + return 0; +} + /* Read a value of type TYPE from register REGNUM in frame FRAME, and return its contents in TO. */ -void +int i387_register_to_value (struct frame_info *frame, int regnum, - struct type *type, gdb_byte *to) + struct type *type, gdb_byte *to, + int *optimizedp, int *unavailablep) { + struct gdbarch *gdbarch = get_frame_arch (frame); gdb_byte from[I386_MAX_REGISTER_SIZE]; - gdb_assert (i386_fp_regnum_p (regnum)); + gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); /* We only support floating-point values. */ - if (TYPE_CODE (type) != TYPE_CODE_FLT) + if (type->code () != TYPE_CODE_FLT) { warning (_("Cannot convert floating-point register value " "to non-floating-point type.")); - return; + *optimizedp = *unavailablep = 0; + return 0; } - /* Convert to TYPE. This should be a no-op if TYPE is equivalent to - the extended floating-point format used by the FPU. */ - get_frame_register (frame, regnum, from); - convert_typed_floating (from, builtin_type_i387_ext, to, type); + /* Convert to TYPE. */ + if (!get_frame_register_bytes (frame, regnum, 0, + register_size (gdbarch, regnum), + from, optimizedp, unavailablep)) + return 0; + + target_float_convert (from, i387_ext_type (gdbarch), to, type); + *optimizedp = *unavailablep = 0; + return 1; } /* Write the contents FROM of a value of type TYPE into register @@ -317,21 +381,21 @@ void i387_value_to_register (struct frame_info *frame, int regnum, struct type *type, const gdb_byte *from) { + struct gdbarch *gdbarch = get_frame_arch (frame); gdb_byte to[I386_MAX_REGISTER_SIZE]; - gdb_assert (i386_fp_regnum_p (regnum)); + gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); /* We only support floating-point values. */ - if (TYPE_CODE (type) != TYPE_CODE_FLT) + if (type->code () != TYPE_CODE_FLT) { warning (_("Cannot convert non-floating-point type " "to floating-point register value.")); return; } - /* Convert from TYPE. This should be a no-op if TYPE is equivalent - to the extended floating-point format used by the FPU. */ - convert_typed_floating (from, type, to, builtin_type_i387_ext); + /* Convert from TYPE. */ + target_float_convert (from, type, to, i387_ext_type (gdbarch)); put_frame_register (frame, regnum, to); } @@ -362,8 +426,8 @@ static int fsave_offset[] = 18 /* `fop' (bottom 11 bits). */ }; -#define FSAVE_ADDR(fsave, regnum) \ - (fsave + fsave_offset[regnum - I387_ST0_REGNUM]) +#define FSAVE_ADDR(tdep, fsave, regnum) \ + (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)]) /* Fill register REGNUM in REGCACHE with the appropriate value from @@ -373,58 +437,51 @@ static int fsave_offset[] = void i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - const gdb_byte *regs = fsave; + struct gdbarch *gdbarch = regcache->arch (); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + const gdb_byte *regs = (const gdb_byte *) fsave; int i; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); - /* Define I387_ST0_REGNUM and I387_NUM_XMM_REGS such that we use the - proper definitions for REGCACHE's architecture. */ - -#define I387_ST0_REGNUM tdep->st0_regnum -#define I387_NUM_XMM_REGS tdep->num_xmm_regs - - for (i = I387_ST0_REGNUM; i < I387_XMM0_REGNUM; i++) + for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) if (regnum == -1 || regnum == i) { if (fsave == NULL) { - regcache_raw_supply (regcache, i, NULL); + regcache->raw_supply (i, NULL); continue; } /* Most of the FPU control registers occupy only 16 bits in the fsave area. Give those a special treatment. */ - if (i >= I387_FCTRL_REGNUM - && i != I387_FIOFF_REGNUM && i != I387_FOOFF_REGNUM) + if (i >= I387_FCTRL_REGNUM (tdep) + && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) { gdb_byte val[4]; - memcpy (val, FSAVE_ADDR (regs, i), 2); + memcpy (val, FSAVE_ADDR (tdep, regs, i), 2); val[2] = val[3] = 0; - if (i == I387_FOP_REGNUM) + if (i == I387_FOP_REGNUM (tdep)) val[1] &= ((1 << 3) - 1); - regcache_raw_supply (regcache, i, val); + regcache->raw_supply (i, val); } else - regcache_raw_supply (regcache, i, FSAVE_ADDR (regs, i)); + regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i)); } /* Provide dummy values for the SSE registers. */ - for (i = I387_XMM0_REGNUM; i < I387_MXCSR_REGNUM; i++) + for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) if (regnum == -1 || regnum == i) - regcache_raw_supply (regcache, i, NULL); - if (regnum == -1 || regnum == I387_MXCSR_REGNUM) + regcache->raw_supply (i, NULL); + if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep)) { gdb_byte buf[4]; - store_unsigned_integer (buf, 4, 0x1f80); - regcache_raw_supply (regcache, I387_MXCSR_REGNUM, buf); + store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); } - -#undef I387_ST0_REGNUM -#undef I387_NUM_XMM_REGS } /* Fill register REGNUM (if it is a floating-point register) in *FSAVE @@ -435,41 +492,36 @@ i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) void i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - gdb_byte *regs = fsave; + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + gdb_byte *regs = (gdb_byte *) fsave; int i; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); - /* Define I387_ST0_REGNUM such that we use the proper definitions - for REGCACHE's architecture. */ -#define I387_ST0_REGNUM tdep->st0_regnum - - for (i = I387_ST0_REGNUM; i < I387_XMM0_REGNUM; i++) + for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) if (regnum == -1 || regnum == i) { /* Most of the FPU control registers occupy only 16 bits in the fsave area. Give those a special treatment. */ - if (i >= I387_FCTRL_REGNUM - && i != I387_FIOFF_REGNUM && i != I387_FOOFF_REGNUM) + if (i >= I387_FCTRL_REGNUM (tdep) + && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) { gdb_byte buf[4]; - regcache_raw_collect (regcache, i, buf); + regcache->raw_collect (i, buf); - if (i == I387_FOP_REGNUM) + if (i == I387_FOP_REGNUM (tdep)) { /* The opcode occupies only 11 bits. Make sure we don't touch the other bits. */ buf[1] &= ((1 << 3) - 1); - buf[1] |= ((FSAVE_ADDR (regs, i))[1] & ~((1 << 3) - 1)); + buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); } - memcpy (FSAVE_ADDR (regs, i), buf, 2); + memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2); } else - regcache_raw_collect (regcache, i, FSAVE_ADDR (regs, i)); + regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i)); } -#undef I387_ST0_REGNUM } @@ -513,8 +565,8 @@ static int fxsave_offset[] = 160 + 15 * 16, /* ... %xmm15 (128 bits each). */ }; -#define FXSAVE_ADDR(fxsave, regnum) \ - (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM]) +#define FXSAVE_ADDR(tdep, fxsave, regnum) \ + (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)]) /* We made an unfortunate choice in putting %mxcsr after the SSE registers %xmm0-%xmm7 instead of before, since it makes supporting @@ -533,40 +585,34 @@ static int i387_tag (const gdb_byte *raw); void i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - const gdb_byte *regs = fxsave; + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + const gdb_byte *regs = (const gdb_byte *) fxsave; int i; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); gdb_assert (tdep->num_xmm_regs > 0); - /* Define I387_ST0_REGNUM and I387_NUM_XMM_REGS such that we use the - proper definitions for REGCACHE's architecture. */ - -#define I387_ST0_REGNUM tdep->st0_regnum -#define I387_NUM_XMM_REGS tdep->num_xmm_regs - - for (i = I387_ST0_REGNUM; i < I387_MXCSR_REGNUM; i++) + for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) if (regnum == -1 || regnum == i) { if (regs == NULL) { - regcache_raw_supply (regcache, i, NULL); + regcache->raw_supply (i, NULL); continue; } /* Most of the FPU control registers occupy only 16 bits in the fxsave area. Give those a special treatment. */ - if (i >= I387_FCTRL_REGNUM && i < I387_XMM0_REGNUM - && i != I387_FIOFF_REGNUM && i != I387_FOOFF_REGNUM) + if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) + && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) { gdb_byte val[4]; - memcpy (val, FXSAVE_ADDR (regs, i), 2); + memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); val[2] = val[3] = 0; - if (i == I387_FOP_REGNUM) + if (i == I387_FOP_REGNUM (tdep)) val[1] &= ((1 << 3) - 1); - else if (i== I387_FTAG_REGNUM) + else if (i== I387_FTAG_REGNUM (tdep)) { /* The fxsave area contains a simplified version of the tag word. We have to look at the actual 80-bit @@ -576,7 +622,8 @@ i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) int fpreg; int top; - top = ((FXSAVE_ADDR (regs, I387_FSTAT_REGNUM))[1] >> 3); + top = ((FXSAVE_ADDR (tdep, regs, + I387_FSTAT_REGNUM (tdep)))[1] >> 3); top &= 0x7; for (fpreg = 7; fpreg >= 0; fpreg--) @@ -585,8 +632,9 @@ i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) if (val[0] & (1 << fpreg)) { - int regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM; - tag = i387_tag (FXSAVE_ADDR (regs, regnum)); + int thisreg = (fpreg + 8 - top) % 8 + + I387_ST0_REGNUM (tdep); + tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); } else tag = 3; /* Empty */ @@ -596,23 +644,20 @@ i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) val[0] = ftag & 0xff; val[1] = (ftag >> 8) & 0xff; } - regcache_raw_supply (regcache, i, val); + regcache->raw_supply (i, val); } else - regcache_raw_supply (regcache, i, FXSAVE_ADDR (regs, i)); + regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); } - if (regnum == I387_MXCSR_REGNUM || regnum == -1) + if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) { if (regs == NULL) - regcache_raw_supply (regcache, I387_MXCSR_REGNUM, NULL); + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL); else - regcache_raw_supply (regcache, I387_MXCSR_REGNUM, + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), FXSAVE_MXCSR_ADDR (regs)); } - -#undef I387_ST0_REGNUM -#undef I387_NUM_XMM_REGS } /* Fill register REGNUM (if it is a floating-point or SSE register) in @@ -623,39 +668,33 @@ i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) void i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); - gdb_byte *regs = fxsave; + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + gdb_byte *regs = (gdb_byte *) fxsave; int i; gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); gdb_assert (tdep->num_xmm_regs > 0); - /* Define I387_ST0_REGNUM and I387_NUM_XMM_REGS such that we use the - proper definitions for REGCACHE's architecture. */ - -#define I387_ST0_REGNUM tdep->st0_regnum -#define I387_NUM_XMM_REGS tdep->num_xmm_regs - - for (i = I387_ST0_REGNUM; i < I387_MXCSR_REGNUM; i++) + for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) if (regnum == -1 || regnum == i) { /* Most of the FPU control registers occupy only 16 bits in the fxsave area. Give those a special treatment. */ - if (i >= I387_FCTRL_REGNUM && i < I387_XMM0_REGNUM - && i != I387_FIOFF_REGNUM && i != I387_FOOFF_REGNUM) + if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) + && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) { gdb_byte buf[4]; - regcache_raw_collect (regcache, i, buf); + regcache->raw_collect (i, buf); - if (i == I387_FOP_REGNUM) + if (i == I387_FOP_REGNUM (tdep)) { /* The opcode occupies only 11 bits. Make sure we don't touch the other bits. */ buf[1] &= ((1 << 3) - 1); - buf[1] |= ((FXSAVE_ADDR (regs, i))[1] & ~((1 << 3) - 1)); + buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); } - else if (i == I387_FTAG_REGNUM) + else if (i == I387_FTAG_REGNUM (tdep)) { /* Converting back is much easier. */ @@ -674,18 +713,1166 @@ i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) buf[0] |= (1 << fpreg); } } - memcpy (FXSAVE_ADDR (regs, i), buf, 2); + memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); } else - regcache_raw_collect (regcache, i, FXSAVE_ADDR (regs, i)); + regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i)); } - if (regnum == I387_MXCSR_REGNUM || regnum == -1) - regcache_raw_collect (regcache, I387_MXCSR_REGNUM, + if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) + regcache->raw_collect (I387_MXCSR_REGNUM (tdep), FXSAVE_MXCSR_ADDR (regs)); +} + +/* `xstate_bv' is at byte offset 512. */ +#define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512) + +/* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in + the upper 128bit of AVX register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_avxh_offset[] = +{ + 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */ + 576 + 1 * 16, + 576 + 2 * 16, + 576 + 3 * 16, + 576 + 4 * 16, + 576 + 5 * 16, + 576 + 6 * 16, + 576 + 7 * 16, + 576 + 8 * 16, + 576 + 9 * 16, + 576 + 10 * 16, + 576 + 11 * 16, + 576 + 12 * 16, + 576 + 13 * 16, + 576 + 14 * 16, + 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */ +}; + +#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) + +/* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in + the upper 128bit of ZMM register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_ymm_avx512_offset[] = +{ + /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */ + 1664 + 16 + 0 * 64, /* %ymm16 through... */ + 1664 + 16 + 1 * 64, + 1664 + 16 + 2 * 64, + 1664 + 16 + 3 * 64, + 1664 + 16 + 4 * 64, + 1664 + 16 + 5 * 64, + 1664 + 16 + 6 * 64, + 1664 + 16 + 7 * 64, + 1664 + 16 + 8 * 64, + 1664 + 16 + 9 * 64, + 1664 + 16 + 10 * 64, + 1664 + 16 + 11 * 64, + 1664 + 16 + 12 * 64, + 1664 + 16 + 13 * 64, + 1664 + 16 + 14 * 64, + 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ +}; + +#define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) + +static int xsave_xmm_avx512_offset[] = +{ + 1664 + 0 * 64, /* %ymm16 through... */ + 1664 + 1 * 64, + 1664 + 2 * 64, + 1664 + 3 * 64, + 1664 + 4 * 64, + 1664 + 5 * 64, + 1664 + 6 * 64, + 1664 + 7 * 64, + 1664 + 8 * 64, + 1664 + 9 * 64, + 1664 + 10 * 64, + 1664 + 11 * 64, + 1664 + 12 * 64, + 1664 + 13 * 64, + 1664 + 14 * 64, + 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */ +}; + +#define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)]) + +static int xsave_mpx_offset[] = { + 960 + 0 * 16, /* bnd0r...bnd3r registers. */ + 960 + 1 * 16, + 960 + 2 * 16, + 960 + 3 * 16, + 1024 + 0 * 8, /* bndcfg ... bndstatus. */ + 1024 + 1 * 8, +}; + +#define XSAVE_MPX_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)]) + + /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location + of the AVX512 opmask register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_avx512_k_offset[] = +{ + 1088 + 0 * 8, /* %k0 through... */ + 1088 + 1 * 8, + 1088 + 2 * 8, + 1088 + 3 * 8, + 1088 + 4 * 8, + 1088 + 5 * 8, + 1088 + 6 * 8, + 1088 + 7 * 8 /* %k7 (64 bits each). */ +}; -#undef I387_ST0_REGNUM -#undef I387_NUM_XMM_REGS +#define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)]) + +/* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in + the upper 256bit of AVX512 ZMMH register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_avx512_zmm_h_offset[] = +{ + 1152 + 0 * 32, + 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */ + 1152 + 2 * 32, + 1152 + 3 * 32, + 1152 + 4 * 32, + 1152 + 5 * 32, + 1152 + 6 * 32, + 1152 + 7 * 32, + 1152 + 8 * 32, + 1152 + 9 * 32, + 1152 + 10 * 32, + 1152 + 11 * 32, + 1152 + 12 * 32, + 1152 + 13 * 32, + 1152 + 14 * 32, + 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */ + 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */ + 1664 + 32 + 1 * 64, + 1664 + 32 + 2 * 64, + 1664 + 32 + 3 * 64, + 1664 + 32 + 4 * 64, + 1664 + 32 + 5 * 64, + 1664 + 32 + 6 * 64, + 1664 + 32 + 7 * 64, + 1664 + 32 + 8 * 64, + 1664 + 32 + 9 * 64, + 1664 + 32 + 10 * 64, + 1664 + 32 + 11 * 64, + 1664 + 32 + 12 * 64, + 1664 + 32 + 13 * 64, + 1664 + 32 + 14 * 64, + 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */ +}; + +#define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)]) + +/* At xsave_pkeys_offset[REGNUM] you find the offset to the location + of the PKRU register data structure used by the "xsave" + instruction where GDB register REGNUM is stored. */ + +static int xsave_pkeys_offset[] = +{ +2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by + instructions and applications). */ +}; + +#define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \ + (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) + + +/* Extract from XSAVE a bitset of the features that are available on the + target, but which have not yet been enabled. */ + +ULONGEST +i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave) +{ + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + const gdb_byte *regs = (const gdb_byte *) xsave; + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */ + ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), + 8, byte_order); + + /* Clear part in vector registers if its bit in xstat_bv is zero. */ + ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0; + + return clear_bv; +} + +/* Similar to i387_supply_fxsave, but use XSAVE extended state. */ + +void +i387_supply_xsave (struct regcache *regcache, int regnum, + const void *xsave) +{ + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + const gdb_byte *regs = (const gdb_byte *) xsave; + int i; + /* In 64-bit mode the split between "low" and "high" ZMM registers is at + ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all. + Precalculate the number to be used for the split point, with the all + registers in the "low" portion outside of 64-bit mode. */ + unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) + + std::min (tdep->num_zmm_regs, 16); + ULONGEST clear_bv; + static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 }; + enum + { + none = 0x0, + x87 = 0x1, + sse = 0x2, + avxh = 0x4, + mpx = 0x8, + avx512_k = 0x10, + avx512_zmm_h = 0x20, + avx512_ymmh_avx512 = 0x40, + avx512_xmm_avx512 = 0x80, + pkeys = 0x100, + all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h + | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys + } regclass; + + gdb_assert (regs != NULL); + gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); + gdb_assert (tdep->num_xmm_regs > 0); + + if (regnum == -1) + regclass = all; + else if (regnum >= I387_PKRU_REGNUM (tdep) + && regnum < I387_PKEYSEND_REGNUM (tdep)) + regclass = pkeys; + else if (regnum >= I387_ZMM0H_REGNUM (tdep) + && regnum < I387_ZMMENDH_REGNUM (tdep)) + regclass = avx512_zmm_h; + else if (regnum >= I387_K0_REGNUM (tdep) + && regnum < I387_KEND_REGNUM (tdep)) + regclass = avx512_k; + else if (regnum >= I387_YMM16H_REGNUM (tdep) + && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) + regclass = avx512_ymmh_avx512; + else if (regnum >= I387_XMM16_REGNUM (tdep) + && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) + regclass = avx512_xmm_avx512; + else if (regnum >= I387_YMM0H_REGNUM (tdep) + && regnum < I387_YMMENDH_REGNUM (tdep)) + regclass = avxh; + else if (regnum >= I387_BND0R_REGNUM (tdep) + && regnum < I387_MPXEND_REGNUM (tdep)) + regclass = mpx; + else if (regnum >= I387_XMM0_REGNUM (tdep) + && regnum < I387_MXCSR_REGNUM (tdep)) + regclass = sse; + else if (regnum >= I387_ST0_REGNUM (tdep) + && regnum < I387_FCTRL_REGNUM (tdep)) + regclass = x87; + else + regclass = none; + + clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave); + + /* With the delayed xsave mechanism, in between the program + starting, and the program accessing the vector registers for the + first time, the register's values are invalid. The kernel + initializes register states to zero when they are set the first + time in a program. This means that from the user-space programs' + perspective, it's the same as if the registers have always been + zero from the start of the program. Therefore, the debugger + should provide the same illusion to the user. */ + + switch (regclass) + { + case none: + break; + + case pkeys: + if ((clear_bv & X86_XSTATE_PKRU)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum)); + return; + + case avx512_zmm_h: + if ((clear_bv & (regnum < zmm_endlo_regnum ? X86_XSTATE_ZMM_H + : X86_XSTATE_ZMM))) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, + XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum)); + return; + + case avx512_k: + if ((clear_bv & X86_XSTATE_K)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, XSAVE_AVX512_K_ADDR (tdep, regs, regnum)); + return; + + case avx512_ymmh_avx512: + if ((clear_bv & X86_XSTATE_ZMM)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, + XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum)); + return; + + case avx512_xmm_avx512: + if ((clear_bv & X86_XSTATE_ZMM)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, + XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum)); + return; + + case avxh: + if ((clear_bv & X86_XSTATE_AVX)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum)); + return; + + case mpx: + if ((clear_bv & X86_XSTATE_BNDREGS)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, XSAVE_MPX_ADDR (tdep, regs, regnum)); + return; + + case sse: + if ((clear_bv & X86_XSTATE_SSE)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); + return; + + case x87: + if ((clear_bv & X86_XSTATE_X87)) + regcache->raw_supply (regnum, zero); + else + regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); + return; + + case all: + /* Handle PKEYS registers. */ + if ((tdep->xcr0 & X86_XSTATE_PKRU)) + { + if ((clear_bv & X86_XSTATE_PKRU)) + { + for (i = I387_PKRU_REGNUM (tdep); + i < I387_PKEYSEND_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_PKRU_REGNUM (tdep); + i < I387_PKEYSEND_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i)); + } + } + + /* Handle the upper halves of the low 8/16 ZMM registers. */ + if ((tdep->xcr0 & X86_XSTATE_ZMM_H)) + { + if ((clear_bv & X86_XSTATE_ZMM_H)) + { + for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) + regcache->raw_supply (i, + XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); + } + } + + /* Handle AVX512 OpMask registers. */ + if ((tdep->xcr0 & X86_XSTATE_K)) + { + if ((clear_bv & X86_XSTATE_K)) + { + for (i = I387_K0_REGNUM (tdep); + i < I387_KEND_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_K0_REGNUM (tdep); + i < I387_KEND_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i)); + } + } + + /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */ + if ((tdep->xcr0 & X86_XSTATE_ZMM)) + { + if ((clear_bv & X86_XSTATE_ZMM)) + { + for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) + regcache->raw_supply (i, zero); + for (i = I387_YMM16H_REGNUM (tdep); + i < I387_YMMH_AVX512_END_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + for (i = I387_XMM16_REGNUM (tdep); + i < I387_XMM_AVX512_END_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) + regcache->raw_supply (i, + XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); + for (i = I387_YMM16H_REGNUM (tdep); + i < I387_YMMH_AVX512_END_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i)); + for (i = I387_XMM16_REGNUM (tdep); + i < I387_XMM_AVX512_END_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i)); + } + } + /* Handle the upper YMM registers. */ + if ((tdep->xcr0 & X86_XSTATE_AVX)) + { + if ((clear_bv & X86_XSTATE_AVX)) + { + for (i = I387_YMM0H_REGNUM (tdep); + i < I387_YMMENDH_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_YMM0H_REGNUM (tdep); + i < I387_YMMENDH_REGNUM (tdep); + i++) + regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i)); + } + } + + /* Handle the MPX registers. */ + if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) + { + if (clear_bv & X86_XSTATE_BNDREGS) + { + for (i = I387_BND0R_REGNUM (tdep); + i < I387_BNDCFGU_REGNUM (tdep); i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_BND0R_REGNUM (tdep); + i < I387_BNDCFGU_REGNUM (tdep); i++) + regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); + } + } + + /* Handle the MPX registers. */ + if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) + { + if (clear_bv & X86_XSTATE_BNDCFG) + { + for (i = I387_BNDCFGU_REGNUM (tdep); + i < I387_MPXEND_REGNUM (tdep); i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_BNDCFGU_REGNUM (tdep); + i < I387_MPXEND_REGNUM (tdep); i++) + regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); + } + } + + /* Handle the XMM registers. */ + if ((tdep->xcr0 & X86_XSTATE_SSE)) + { + if ((clear_bv & X86_XSTATE_SSE)) + { + for (i = I387_XMM0_REGNUM (tdep); + i < I387_MXCSR_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_XMM0_REGNUM (tdep); + i < I387_MXCSR_REGNUM (tdep); i++) + regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); + } + } + + /* Handle the x87 registers. */ + if ((tdep->xcr0 & X86_XSTATE_X87)) + { + if ((clear_bv & X86_XSTATE_X87)) + { + for (i = I387_ST0_REGNUM (tdep); + i < I387_FCTRL_REGNUM (tdep); + i++) + regcache->raw_supply (i, zero); + } + else + { + for (i = I387_ST0_REGNUM (tdep); + i < I387_FCTRL_REGNUM (tdep); + i++) + regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); + } + } + break; + } + + /* Only handle x87 control registers. */ + for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) + if (regnum == -1 || regnum == i) + { + if (clear_bv & X86_XSTATE_X87) + { + if (i == I387_FCTRL_REGNUM (tdep)) + { + gdb_byte buf[4]; + + store_unsigned_integer (buf, 4, byte_order, + I387_FCTRL_INIT_VAL); + regcache->raw_supply (i, buf); + } + else if (i == I387_FTAG_REGNUM (tdep)) + { + gdb_byte buf[4]; + + store_unsigned_integer (buf, 4, byte_order, 0xffff); + regcache->raw_supply (i, buf); + } + else + regcache->raw_supply (i, zero); + } + /* Most of the FPU control registers occupy only 16 bits in + the xsave extended state. Give those a special treatment. */ + else if (i != I387_FIOFF_REGNUM (tdep) + && i != I387_FOOFF_REGNUM (tdep)) + { + gdb_byte val[4]; + + memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); + val[2] = val[3] = 0; + if (i == I387_FOP_REGNUM (tdep)) + val[1] &= ((1 << 3) - 1); + else if (i == I387_FTAG_REGNUM (tdep)) + { + /* The fxsave area contains a simplified version of + the tag word. We have to look at the actual 80-bit + FP data to recreate the traditional i387 tag word. */ + + unsigned long ftag = 0; + int fpreg; + int top; + + top = ((FXSAVE_ADDR (tdep, regs, + I387_FSTAT_REGNUM (tdep)))[1] >> 3); + top &= 0x7; + + for (fpreg = 7; fpreg >= 0; fpreg--) + { + int tag; + + if (val[0] & (1 << fpreg)) + { + int thisreg = (fpreg + 8 - top) % 8 + + I387_ST0_REGNUM (tdep); + tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); + } + else + tag = 3; /* Empty */ + + ftag |= tag << (2 * fpreg); + } + val[0] = ftag & 0xff; + val[1] = (ftag >> 8) & 0xff; + } + regcache->raw_supply (i, val); + } + else + regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); + } + + if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) + { + /* The MXCSR register is placed into the xsave buffer if either the + AVX or SSE features are enabled. */ + if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) + == (X86_XSTATE_AVX | X86_XSTATE_SSE)) + { + gdb_byte buf[4]; + + store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); + } + else + regcache->raw_supply (I387_MXCSR_REGNUM (tdep), + FXSAVE_MXCSR_ADDR (regs)); + } +} + +/* Similar to i387_collect_fxsave, but use XSAVE extended state. */ + +void +i387_collect_xsave (const struct regcache *regcache, int regnum, + void *xsave, int gcore) +{ + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + gdb_byte *p, *regs = (gdb_byte *) xsave; + gdb_byte raw[I386_MAX_REGISTER_SIZE]; + ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0; + unsigned int i; + /* See the comment in i387_supply_xsave(). */ + unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) + + std::min (tdep->num_zmm_regs, 16); + enum + { + x87_ctrl_or_mxcsr = 0x1, + x87 = 0x2, + sse = 0x4, + avxh = 0x8, + mpx = 0x10, + avx512_k = 0x20, + avx512_zmm_h = 0x40, + avx512_ymmh_avx512 = 0x80, + avx512_xmm_avx512 = 0x100, + pkeys = 0x200, + all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h + | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys + } regclass; + + gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); + gdb_assert (tdep->num_xmm_regs > 0); + + if (regnum == -1) + regclass = all; + else if (regnum >= I387_PKRU_REGNUM (tdep) + && regnum < I387_PKEYSEND_REGNUM (tdep)) + regclass = pkeys; + else if (regnum >= I387_ZMM0H_REGNUM (tdep) + && regnum < I387_ZMMENDH_REGNUM (tdep)) + regclass = avx512_zmm_h; + else if (regnum >= I387_K0_REGNUM (tdep) + && regnum < I387_KEND_REGNUM (tdep)) + regclass = avx512_k; + else if (regnum >= I387_YMM16H_REGNUM (tdep) + && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) + regclass = avx512_ymmh_avx512; + else if (regnum >= I387_XMM16_REGNUM (tdep) + && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) + regclass = avx512_xmm_avx512; + else if (regnum >= I387_YMM0H_REGNUM (tdep) + && regnum < I387_YMMENDH_REGNUM (tdep)) + regclass = avxh; + else if (regnum >= I387_BND0R_REGNUM (tdep) + && regnum < I387_MPXEND_REGNUM (tdep)) + regclass = mpx; + else if (regnum >= I387_XMM0_REGNUM (tdep) + && regnum < I387_MXCSR_REGNUM (tdep)) + regclass = sse; + else if (regnum >= I387_ST0_REGNUM (tdep) + && regnum < I387_FCTRL_REGNUM (tdep)) + regclass = x87; + else if ((regnum >= I387_FCTRL_REGNUM (tdep) + && regnum < I387_XMM0_REGNUM (tdep)) + || regnum == I387_MXCSR_REGNUM (tdep)) + regclass = x87_ctrl_or_mxcsr; + else + internal_error (__FILE__, __LINE__, _("invalid i387 regnum %d"), regnum); + + if (gcore) + { + /* Clear XSAVE extended state. */ + memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0)); + + /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */ + if (tdep->xsave_xcr0_offset != -1) + memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8); + memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8); + } + + /* The supported bits in `xstat_bv' are 8 bytes. */ + initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), + 8, byte_order); + clear_bv = (~(initial_xstate_bv)) & tdep->xcr0; + + /* The XSAVE buffer was filled lazily by the kernel. Only those + features that are enabled were written into the buffer, disabled + features left the buffer uninitialised. In order to identify if any + registers have changed we will be comparing the register cache + version to the version in the XSAVE buffer, it is important then that + at this point we initialise to the default values any features in + XSAVE that are not yet initialised. + + This could be made more efficient, we know which features (from + REGNUM) we will be potentially updating, and could limit ourselves to + only clearing that feature. However, the extra complexity does not + seem justified at this point. */ + if (clear_bv) + { + if ((clear_bv & X86_XSTATE_PKRU)) + for (i = I387_PKRU_REGNUM (tdep); + i < I387_PKEYSEND_REGNUM (tdep); i++) + memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4); + + if ((clear_bv & X86_XSTATE_BNDREGS)) + for (i = I387_BND0R_REGNUM (tdep); + i < I387_BNDCFGU_REGNUM (tdep); i++) + memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16); + + if ((clear_bv & X86_XSTATE_BNDCFG)) + for (i = I387_BNDCFGU_REGNUM (tdep); + i < I387_MPXEND_REGNUM (tdep); i++) + memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8); + + if ((clear_bv & X86_XSTATE_ZMM_H)) + for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) + memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); + + if ((clear_bv & X86_XSTATE_K)) + for (i = I387_K0_REGNUM (tdep); + i < I387_KEND_REGNUM (tdep); i++) + memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8); + + if ((clear_bv & X86_XSTATE_ZMM)) + { + for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) + memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); + for (i = I387_YMM16H_REGNUM (tdep); + i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) + memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16); + for (i = I387_XMM16_REGNUM (tdep); + i < I387_XMM_AVX512_END_REGNUM (tdep); i++) + memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16); + } + + if ((clear_bv & X86_XSTATE_AVX)) + for (i = I387_YMM0H_REGNUM (tdep); + i < I387_YMMENDH_REGNUM (tdep); i++) + memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16); + + if ((clear_bv & X86_XSTATE_SSE)) + for (i = I387_XMM0_REGNUM (tdep); + i < I387_MXCSR_REGNUM (tdep); i++) + memset (FXSAVE_ADDR (tdep, regs, i), 0, 16); + + /* The mxcsr register is written into the xsave buffer if either AVX + or SSE is enabled, so only clear it if both of those features + require clearing. */ + if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) + == (X86_XSTATE_AVX | X86_XSTATE_SSE)) + store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order, + I387_MXCSR_INIT_VAL); + + if ((clear_bv & X86_XSTATE_X87)) + { + for (i = I387_ST0_REGNUM (tdep); + i < I387_FCTRL_REGNUM (tdep); i++) + memset (FXSAVE_ADDR (tdep, regs, i), 0, 10); + + for (i = I387_FCTRL_REGNUM (tdep); + i < I387_XMM0_REGNUM (tdep); i++) + { + if (i == I387_FCTRL_REGNUM (tdep)) + store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2, + byte_order, I387_FCTRL_INIT_VAL); + else + memset (FXSAVE_ADDR (tdep, regs, i), 0, + regcache_register_size (regcache, i)); + } + } + } + + if (regclass == all) + { + /* Check if any PKEYS registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_PKRU)) + for (i = I387_PKRU_REGNUM (tdep); + i < I387_PKEYSEND_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_PKEYS_ADDR (tdep, regs, i); + if (memcmp (raw, p, 4) != 0) + { + xstate_bv |= X86_XSTATE_PKRU; + memcpy (p, raw, 4); + } + } + + /* Check if any ZMMH registers are changed. */ + if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) + for (i = I387_ZMM0H_REGNUM (tdep); + i < I387_ZMMENDH_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i); + if (memcmp (raw, p, 32) != 0) + { + xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); + memcpy (p, raw, 32); + } + } + + /* Check if any K registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_K)) + for (i = I387_K0_REGNUM (tdep); + i < I387_KEND_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_AVX512_K_ADDR (tdep, regs, i); + if (memcmp (raw, p, 8) != 0) + { + xstate_bv |= X86_XSTATE_K; + memcpy (p, raw, 8); + } + } + + /* Check if any XMM or upper YMM registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_ZMM)) + { + for (i = I387_YMM16H_REGNUM (tdep); + i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16) != 0) + { + xstate_bv |= X86_XSTATE_ZMM; + memcpy (p, raw, 16); + } + } + for (i = I387_XMM16_REGNUM (tdep); + i < I387_XMM_AVX512_END_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16) != 0) + { + xstate_bv |= X86_XSTATE_ZMM; + memcpy (p, raw, 16); + } + } + } + + /* Check if any upper MPX registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) + for (i = I387_BND0R_REGNUM (tdep); + i < I387_BNDCFGU_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_MPX_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_BNDREGS; + memcpy (p, raw, 16); + } + } + + /* Check if any upper MPX registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) + for (i = I387_BNDCFGU_REGNUM (tdep); + i < I387_MPXEND_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_MPX_ADDR (tdep, regs, i); + if (memcmp (raw, p, 8)) + { + xstate_bv |= X86_XSTATE_BNDCFG; + memcpy (p, raw, 8); + } + } + + /* Check if any upper YMM registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_AVX)) + for (i = I387_YMM0H_REGNUM (tdep); + i < I387_YMMENDH_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = XSAVE_AVXH_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_AVX; + memcpy (p, raw, 16); + } + } + + /* Check if any SSE registers are changed. */ + if ((tdep->xcr0 & X86_XSTATE_SSE)) + for (i = I387_XMM0_REGNUM (tdep); + i < I387_MXCSR_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = FXSAVE_ADDR (tdep, regs, i); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_SSE; + memcpy (p, raw, 16); + } + } + + if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE)) + { + i = I387_MXCSR_REGNUM (tdep); + regcache->raw_collect (i, raw); + p = FXSAVE_MXCSR_ADDR (regs); + if (memcmp (raw, p, 4)) + { + /* Now, we need to mark one of either SSE of AVX as enabled. + We could pick either. What we do is check to see if one + of the features is already enabled, if it is then we leave + it at that, otherwise we pick SSE. */ + if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0) + xstate_bv |= X86_XSTATE_SSE; + memcpy (p, raw, 4); + } + } + + /* Check if any X87 registers are changed. Only the non-control + registers are handled here, the control registers are all handled + later on in this function. */ + if ((tdep->xcr0 & X86_XSTATE_X87)) + for (i = I387_ST0_REGNUM (tdep); + i < I387_FCTRL_REGNUM (tdep); i++) + { + regcache->raw_collect (i, raw); + p = FXSAVE_ADDR (tdep, regs, i); + if (memcmp (raw, p, 10)) + { + xstate_bv |= X86_XSTATE_X87; + memcpy (p, raw, 10); + } + } + } + else + { + /* Check if REGNUM is changed. */ + regcache->raw_collect (regnum, raw); + + switch (regclass) + { + default: + internal_error (__FILE__, __LINE__, + _("invalid i387 regclass")); + + case pkeys: + /* This is a PKEYS register. */ + p = XSAVE_PKEYS_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 4) != 0) + { + xstate_bv |= X86_XSTATE_PKRU; + memcpy (p, raw, 4); + } + break; + + case avx512_zmm_h: + /* This is a ZMM register. */ + p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 32) != 0) + { + xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); + memcpy (p, raw, 32); + } + break; + case avx512_k: + /* This is a AVX512 mask register. */ + p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 8) != 0) + { + xstate_bv |= X86_XSTATE_K; + memcpy (p, raw, 8); + } + break; + + case avx512_ymmh_avx512: + /* This is an upper YMM16-31 register. */ + p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16) != 0) + { + xstate_bv |= X86_XSTATE_ZMM; + memcpy (p, raw, 16); + } + break; + + case avx512_xmm_avx512: + /* This is an upper XMM16-31 register. */ + p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16) != 0) + { + xstate_bv |= X86_XSTATE_ZMM; + memcpy (p, raw, 16); + } + break; + + case avxh: + /* This is an upper YMM register. */ + p = XSAVE_AVXH_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_AVX; + memcpy (p, raw, 16); + } + break; + + case mpx: + if (regnum < I387_BNDCFGU_REGNUM (tdep)) + { + regcache->raw_collect (regnum, raw); + p = XSAVE_MPX_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_BNDREGS; + memcpy (p, raw, 16); + } + } + else + { + p = XSAVE_MPX_ADDR (tdep, regs, regnum); + xstate_bv |= X86_XSTATE_BNDCFG; + memcpy (p, raw, 8); + } + break; + + case sse: + /* This is an SSE register. */ + p = FXSAVE_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 16)) + { + xstate_bv |= X86_XSTATE_SSE; + memcpy (p, raw, 16); + } + break; + + case x87: + /* This is an x87 register. */ + p = FXSAVE_ADDR (tdep, regs, regnum); + if (memcmp (raw, p, 10)) + { + xstate_bv |= X86_XSTATE_X87; + memcpy (p, raw, 10); + } + break; + + case x87_ctrl_or_mxcsr: + /* We only handle MXCSR here. All other x87 control registers + are handled separately below. */ + if (regnum == I387_MXCSR_REGNUM (tdep)) + { + p = FXSAVE_MXCSR_ADDR (regs); + if (memcmp (raw, p, 2)) + { + /* We're only setting MXCSR, so check the initial state + to see if either of AVX or SSE are already enabled. + If they are then we'll attribute this changed MXCSR to + that feature. If neither feature is enabled, then + we'll attribute this change to the SSE feature. */ + xstate_bv |= (initial_xstate_bv + & (X86_XSTATE_AVX | X86_XSTATE_SSE)); + if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0) + xstate_bv |= X86_XSTATE_SSE; + memcpy (p, raw, 2); + } + } + } + } + + /* Only handle x87 control registers. */ + for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) + if (regnum == -1 || regnum == i) + { + /* Most of the FPU control registers occupy only 16 bits in + the xsave extended state. Give those a special treatment. */ + if (i != I387_FIOFF_REGNUM (tdep) + && i != I387_FOOFF_REGNUM (tdep)) + { + gdb_byte buf[4]; + + regcache->raw_collect (i, buf); + + if (i == I387_FOP_REGNUM (tdep)) + { + /* The opcode occupies only 11 bits. Make sure we + don't touch the other bits. */ + buf[1] &= ((1 << 3) - 1); + buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); + } + else if (i == I387_FTAG_REGNUM (tdep)) + { + /* Converting back is much easier. */ + + unsigned short ftag; + int fpreg; + + ftag = (buf[1] << 8) | buf[0]; + buf[0] = 0; + buf[1] = 0; + + for (fpreg = 7; fpreg >= 0; fpreg--) + { + int tag = (ftag >> (fpreg * 2)) & 3; + + if (tag != 3) + buf[0] |= (1 << fpreg); + } + } + p = FXSAVE_ADDR (tdep, regs, i); + if (memcmp (p, buf, 2)) + { + xstate_bv |= X86_XSTATE_X87; + memcpy (p, buf, 2); + } + } + else + { + int regsize; + + regcache->raw_collect (i, raw); + regsize = regcache_register_size (regcache, i); + p = FXSAVE_ADDR (tdep, regs, i); + if (memcmp (raw, p, regsize)) + { + xstate_bv |= X86_XSTATE_X87; + memcpy (p, raw, regsize); + } + } + } + + /* Update the corresponding bits in `xstate_bv' if any + registers are changed. */ + if (xstate_bv) + { + /* The supported bits in `xstat_bv' are 8 bytes. */ + initial_xstate_bv |= xstate_bv; + store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), + 8, byte_order, + initial_xstate_bv); + } } /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in @@ -745,22 +1932,34 @@ i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache) struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); ULONGEST fstat; - /* Define I387_ST0_REGNUM such that we use the proper - definitions for the architecture. */ -#define I387_ST0_REGNUM tdep->st0_regnum - /* Set the top of the floating-point register stack to 7. The actual value doesn't really matter, but 7 is what a normal function return would end up with if the program started out with a freshly initialized FPU. */ - regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM, &fstat); + regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); fstat |= (7 << 11); - regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM, fstat); + regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); /* Mark %st(1) through %st(7) as empty. Since we set the top of the floating-point register stack to 7, the appropriate value for the tag word is 0x3fff. */ - regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM, 0x3fff); + regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); + +} -#undef I387_ST0_REGNUM +/* See i387-tdep.h. */ + +void +i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + if (I387_BND0R_REGNUM (tdep) > 0) + { + gdb_byte bnd_buf[16]; + + memset (bnd_buf, 0, 16); + for (int i = 0; i < I387_NUM_BND_REGS; i++) + regcache->raw_write (I387_BND0R_REGNUM (tdep) + i, bnd_buf); + } }