X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Flm32-tdep.c;h=73f8ae746f7861cadd0ffa9989fe2fe1c78ca65e;hb=refs%2Fheads%2Fconcurrent-displaced-stepping-2020-04-01;hp=1ca6c08bf2da769329301e31b7395c8ff0fd4a74;hpb=cdd238daf949385bd6ef188e24b40d9fcb83a0e8;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/lm32-tdep.c b/gdb/lm32-tdep.c index 1ca6c08bf2..73f8ae746f 100644 --- a/gdb/lm32-tdep.c +++ b/gdb/lm32-tdep.c @@ -1,7 +1,7 @@ /* Target-dependent code for Lattice Mico32 processor, for GDB. Contributed by Jon Beniston - Copyright (C) 2009-2017 Free Software Foundation, Inc. + Copyright (C) 2009-2020 Free Software Foundation, Inc. This file is part of GDB. @@ -81,7 +81,7 @@ lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum, return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM)) || (regnum == SIM_LM32_PC_REGNUM); else if (group == system_reggroup) - return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM)) + return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM)) || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM)); return default_register_reggroup_p (gdbarch, regnum, group); } @@ -228,7 +228,8 @@ static CORE_ADDR lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, - int struct_return, CORE_ADDR struct_addr) + function_call_return_method return_method, + CORE_ADDR struct_addr) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); int first_arg_reg = SIM_LM32_R1_REGNUM; @@ -240,7 +241,7 @@ lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, /* If we're returning a large struct, a pointer to the address to store it at is passed as a first hidden parameter. */ - if (struct_return) + if (return_method == return_method_struct) { regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr); first_arg_reg++; @@ -257,7 +258,7 @@ lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, ULONGEST val; /* Promote small integer types to int. */ - switch (TYPE_CODE (arg_type)) + switch (arg_type->code ()) { case TYPE_CODE_INT: case TYPE_CODE_BOOL: @@ -303,20 +304,20 @@ static void lm32_extract_return_value (struct type *type, struct regcache *regcache, gdb_byte *valbuf) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); ULONGEST l; CORE_ADDR return_buffer; - if (TYPE_CODE (type) != TYPE_CODE_STRUCT - && TYPE_CODE (type) != TYPE_CODE_UNION - && TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4) + if (type->code () != TYPE_CODE_STRUCT + && type->code () != TYPE_CODE_UNION + && type->code () != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4) { /* Return value is returned in a single register. */ regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l); } - else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8)) + else if ((type->code () == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8)) { /* 64-bit values are returned in a register pair. */ regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); @@ -340,7 +341,7 @@ static void lm32_store_return_value (struct type *type, struct regcache *regcache, const gdb_byte *valbuf) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); ULONGEST val; int len = TYPE_LENGTH (type); @@ -367,7 +368,7 @@ lm32_return_value (struct gdbarch *gdbarch, struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf) { - enum type_code code = TYPE_CODE (valtype); + enum type_code code = valtype->code (); if (code == TYPE_CODE_STRUCT || code == TYPE_CODE_UNION @@ -382,26 +383,6 @@ lm32_return_value (struct gdbarch *gdbarch, struct value *function, return RETURN_VALUE_REGISTER_CONVENTION; } -static CORE_ADDR -lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) -{ - return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM); -} - -static CORE_ADDR -lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) -{ - return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM); -} - -static struct frame_id -lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) -{ - CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM); - - return frame_id_build (sp, get_frame_pc (this_frame)); -} - /* Put here the code to store, into fi->saved_regs, the addresses of the saved registers of frame described by FRAME_INFO. This includes special registers such as pc and fp saved in special ways @@ -551,9 +532,6 @@ lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* Frame unwinding. */ set_gdbarch_frame_align (gdbarch, lm32_frame_align); frame_base_set_default (gdbarch, &lm32_frame_base); - set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc); - set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp); - set_gdbarch_dummy_id (gdbarch, lm32_dummy_id); frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind); /* Breakpoints. */ @@ -571,11 +549,9 @@ lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) return gdbarch; } -/* -Wmissing-prototypes */ -extern initialize_file_ftype _initialize_lm32_tdep; - +void _initialize_lm32_tdep (); void -_initialize_lm32_tdep (void) +_initialize_lm32_tdep () { register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init); }