X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fmips-tdep.c;h=f54f19c2ad702be0bbd7679550925b9476ff1698;hb=7bda5e4ae2bdb120b4f4c6e7a4fa18b84f108813;hp=5bc44ba180a7bc97b0f56d5d361ddce904377e68;hpb=cb1d2653f9ed49397cfb241068e44ca795e62e06;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 5bc44ba180..f54f19c2ad 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -173,6 +173,43 @@ mips_saved_regsize (void) return 4; } +/* Functions for setting and testing a bit in a minimal symbol that + marks it as 16-bit function. The MSB of the minimal symbol's + "info" field is used for this purpose. This field is already + being used to store the symbol size, so the assumption is + that the symbol size cannot exceed 2^31. + + ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", + i.e. refers to a 16-bit function, and sets a "special" bit in a + minimal symbol to mark it as a 16-bit function + + MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol + MSYMBOL_SIZE returns the size of the minimal symbol, i.e. + the "info" field with the "special" bit masked out */ + +static void +mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) +{ + if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_MIPS16) + { + MSYMBOL_INFO (msym) = (char *) + (((long) MSYMBOL_INFO (msym)) | 0x80000000); + SYMBOL_VALUE_ADDRESS (msym) |= 1; + } +} + +static int +msymbol_is_special (struct minimal_symbol *msym) +{ + return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); +} + +static long +msymbol_size (struct minimal_symbol *msym) +{ + return ((long) MSYMBOL_INFO (msym) & 0x7fffffff); +} + /* XFER a value from the big/little/left end of the register. Depending on the size of the value it might occupy the entire register or just part of it. Make an allowance for this, aligning @@ -297,7 +334,7 @@ static CORE_ADDR heuristic_proc_start (CORE_ADDR); static CORE_ADDR read_next_frame_reg (struct frame_info *, int); -int mips_set_processor_type (char *); +static int mips_set_processor_type (char *); static void mips_show_processor_type_command (char *, int); @@ -333,7 +370,7 @@ static struct cmd_list_element *showmipscmdlist = NULL; char *mips_generic_reg_names[] = MIPS_REGISTER_NAMES; char **mips_processor_reg_names = mips_generic_reg_names; -const char * +static const char * mips_register_name (int i) { return mips_processor_reg_names[i]; @@ -351,7 +388,7 @@ char *mips_r3041_reg_names[] = { "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "fsr", "fir", "fp", "", + "fsr", "fir", "",/*"fp"*/ "", "", "", "bus", "ccfg", "", "", "", "", "", "", "port", "cmp", "", "", "epc", "prid", }; @@ -368,7 +405,7 @@ char *mips_r3051_reg_names[] = { "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "fsr", "fir", "fp", "", + "fsr", "fir", ""/*"fp"*/, "", "inx", "rand", "elo", "", "ctxt", "", "", "", "", "", "ehi", "", "", "", "epc", "prid", }; @@ -385,7 +422,7 @@ char *mips_r3081_reg_names[] = { "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "fsr", "fir", "fp", "", + "fsr", "fir", ""/*"fp"*/, "", "inx", "rand", "elo", "cfg", "ctxt", "", "", "", "", "", "ehi", "", "", "", "epc", "prid", }; @@ -476,7 +513,7 @@ mips_print_extra_frame_info (struct frame_info *fi) static int mips64_transfers_32bit_regs_p = 0; -int +static int mips_register_raw_size (int reg_nr) { if (mips64_transfers_32bit_regs_p) @@ -653,19 +690,19 @@ show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) /* Should call_function allocate stack space for a struct return? */ -int +static int mips_eabi_use_struct_convention (int gcc_p, struct type *type) { return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); } -int +static int mips_n32n64_use_struct_convention (int gcc_p, struct type *type) { return (TYPE_LENGTH (type) > 2 * MIPS_SAVED_REGSIZE); } -int +static int mips_o32_use_struct_convention (int gcc_p, struct type *type) { return 1; /* Structures are returned by ref in extra arg0. */ @@ -693,7 +730,7 @@ mips_n32n64_reg_struct_has_addr (int gcc_p, struct type *type) return 0; /* Assumption: N32/N64 never passes struct by ref. */ } -int +static int mips_o32_reg_struct_has_addr (int gcc_p, struct type *type) { return 0; /* Assumption: O32/O64 never passes struct by ref. */ @@ -715,7 +752,7 @@ pc_is_mips16 (bfd_vma memaddr) MIPS16 or normal MIPS. */ sym = lookup_minimal_symbol_by_pc (memaddr); if (sym) - return MSYMBOL_IS_SPECIAL (sym); + return msymbol_is_special (sym); else return 0; } @@ -883,7 +920,7 @@ mips32_relative_offset (unsigned long inst) /* Determine whate to set a single step breakpoint while considering branch prediction */ -CORE_ADDR +static CORE_ADDR mips32_next_pc (CORE_ADDR pc) { unsigned long inst; @@ -1322,7 +1359,7 @@ extended_mips16_next_pc (CORE_ADDR pc, return pc; } -CORE_ADDR +static CORE_ADDR mips16_next_pc (CORE_ADDR pc) { unsigned int insn = fetch_mips_16 (pc); @@ -1552,21 +1589,29 @@ mips_frame_init_saved_regs (struct frame_info *frame) static CORE_ADDR read_next_frame_reg (struct frame_info *fi, int regno) { - for (; fi; fi = fi->next) + int optimized; + CORE_ADDR addr; + int realnum; + enum lval_type lval; + void *raw_buffer = alloca (MAX_REGISTER_RAW_SIZE); + frame_register_unwind (fi, regno, &optimized, &lval, &addr, &realnum, + raw_buffer); + /* FIXME: cagney/2002-09-13: This is just soooo bad. The MIPS + should have a pseudo register range that correspons to the ABI's, + rather than the ISA's, view of registers. These registers would + then implicitly describe their size and hence could be used + without the below munging. */ + if (lval == lval_memory) { - /* We have to get the saved sp from the sigcontext - if it is a signal handler frame. */ - if (regno == SP_REGNUM && !fi->signal_handler_caller) - return fi->frame; - else + if (regno < 32) { - if (fi->saved_regs == NULL) - FRAME_INIT_SAVED_REGS (fi); - if (fi->saved_regs[regno]) - return read_memory_integer (ADDR_BITS_REMOVE (fi->saved_regs[regno]), MIPS_SAVED_REGSIZE); + /* Only MIPS_SAVED_REGSIZE bytes of GP registers are + saved. */ + return read_memory_integer (addr, MIPS_SAVED_REGSIZE); } } - return read_signed_register (regno); + + return extract_signed_integer (raw_buffer, REGISTER_VIRTUAL_SIZE (regno)); } /* mips_addr_bits_remove - remove useless address bits */ @@ -1644,12 +1689,12 @@ mips_init_frame_pc_first (int fromleaf, struct frame_info *prev) pc = ((fromleaf) ? SAVED_PC_AFTER_CALL (prev->next) : prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); - tmp = mips_skip_stub (pc); + tmp = SKIP_TRAMPOLINE_CODE (pc); prev->pc = tmp ? tmp : pc; } -CORE_ADDR +static CORE_ADDR mips_frame_saved_pc (struct frame_info *frame) { CORE_ADDR saved_pc; @@ -2359,9 +2404,9 @@ get_frame_pointer (struct frame_info *frame, PROC_FRAME_ADJUST (proc_desc)); } -mips_extra_func_info_t cached_proc_desc; +static mips_extra_func_info_t cached_proc_desc; -CORE_ADDR +static CORE_ADDR mips_frame_chain (struct frame_info *frame) { mips_extra_func_info_t proc_desc; @@ -2373,7 +2418,7 @@ mips_frame_chain (struct frame_info *frame) /* Check if the PC is inside a call stub. If it is, fetch the PC of the caller of that stub. */ - if ((tmp = mips_skip_stub (saved_pc)) != 0) + if ((tmp = SKIP_TRAMPOLINE_CODE (saved_pc)) != 0) saved_pc = tmp; /* Look up the procedure descriptor for this PC. */ @@ -2392,13 +2437,13 @@ mips_frame_chain (struct frame_info *frame) and have frame size zero. */ && !frame->signal_handler_caller /* Check if this is a call dummy frame. */ - && frame->pc != mips_call_dummy_address ()) + && frame->pc != CALL_DUMMY_ADDRESS ()) return 0; else return get_frame_pointer (frame, proc_desc); } -void +static void mips_init_extra_frame_info (int fromleaf, struct frame_info *fci) { int regnum; @@ -2539,7 +2584,15 @@ mips_type_needs_double_align (struct type *type) #define ROUND_DOWN(n,a) ((n) & ~((a)-1)) #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1)) -CORE_ADDR +/* Adjust the address downward (direction of stack growth) so that it + is correctly aligned for a new stack frame. */ +static CORE_ADDR +mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) +{ + return ROUND_DOWN (addr, 16); +} + +static CORE_ADDR mips_eabi_push_arguments (int nargs, struct value **args, CORE_ADDR sp, @@ -2792,7 +2845,7 @@ mips_eabi_push_arguments (int nargs, /* N32/N64 version of push_arguments. */ -CORE_ADDR +static CORE_ADDR mips_n32n64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, @@ -2918,10 +2971,6 @@ mips_n32n64_push_arguments (int nargs, typecode == TYPE_CODE_PTR || typecode == TYPE_CODE_FLT) && len <= 4) longword_offset = MIPS_STACK_ARGSIZE - len; - else if ((typecode == TYPE_CODE_STRUCT || - typecode == TYPE_CODE_UNION) && - TYPE_LENGTH (arg_type) < MIPS_STACK_ARGSIZE) - longword_offset = MIPS_STACK_ARGSIZE - len; } if (mips_debug) @@ -3614,7 +3663,7 @@ mips_o64_push_arguments (int nargs, return sp; } -CORE_ADDR +static CORE_ADDR mips_push_return_address (CORE_ADDR pc, CORE_ADDR sp) { /* Set the return address register to point to the entry @@ -3649,7 +3698,7 @@ mips_push_register (CORE_ADDR * sp, int regno) /* MASK(i,j) == (1<saved_regs == NULL) FRAME_INIT_SAVED_REGS (frame); for (regnum = 0; regnum < NUM_REGS; regnum++) - { - if (regnum != SP_REGNUM && regnum != PC_REGNUM - && frame->saved_regs[regnum]) - write_register (regnum, - read_memory_integer (frame->saved_regs[regnum], - MIPS_SAVED_REGSIZE)); - } + if (regnum != SP_REGNUM && regnum != PC_REGNUM + && frame->saved_regs[regnum]) + { + /* Floating point registers must not be sign extended, + in case MIPS_SAVED_REGSIZE = 4 but sizeof (FP0_REGNUM) == 8. */ + + if (FP0_REGNUM <= regnum && regnum < FP0_REGNUM + 32) + write_register (regnum, + read_memory_unsigned_integer (frame->saved_regs[regnum], + MIPS_SAVED_REGSIZE)); + else + write_register (regnum, + read_memory_integer (frame->saved_regs[regnum], + MIPS_SAVED_REGSIZE)); + } + write_register (SP_REGNUM, new_sp); flush_cached_frames (); @@ -3786,6 +3844,13 @@ mips_pop_frame (void) } } +static void +mips_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, + struct value **args, struct type *type, int gcc_p) +{ + write_register(T9_REGNUM, fun); +} + /* Floating point register management. Background: MIPS1 & 2 fp registers are 32 bits wide. To support @@ -4143,15 +4208,6 @@ mips_do_registers_info (int regnum, int fpregs) } } -/* Return number of args passed to a frame. described by FIP. - Can return -1, meaning no way to tell. */ - -int -mips_frame_num_args (struct frame_info *frame) -{ - return -1; -} - /* Is this a branch with a delay slot? */ static int is_delayed (unsigned long); @@ -4390,7 +4446,7 @@ mips16_skip_prologue (CORE_ADDR pc) We must skip more in the case where part of the prologue is in the delay slot of a non-prologue instruction). */ -CORE_ADDR +static CORE_ADDR mips_skip_prologue (CORE_ADDR pc) { /* See if we can determine the end of the prologue via the symbol table. @@ -4744,7 +4800,7 @@ mips_o32_xfer_return_value (struct type *type, static void mips_o32_extract_return_value (struct type *type, struct regcache *regcache, - char *valbuf) + void *valbuf) { mips_o32_xfer_return_value (type, regcache, valbuf, NULL); } @@ -4852,7 +4908,7 @@ mips_n32n64_xfer_return_value (struct type *type, static void mips_n32n64_extract_return_value (struct type *type, struct regcache *regcache, - char *valbuf) + void *valbuf) { mips_n32n64_xfer_return_value (type, regcache, valbuf, NULL); } @@ -4863,6 +4919,24 @@ mips_n32n64_store_return_value (struct type *type, char *valbuf) mips_n32n64_xfer_return_value (type, current_regcache, NULL, valbuf); } +static void +mips_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) +{ + /* Nothing to do -- push_arguments does all the work. */ +} + +static CORE_ADDR +mips_extract_struct_value_address (struct regcache *regcache) +{ + /* FIXME: This will only work at random. The caller passes the + struct_return address in V0, but it is not preserved. It may + still be there, or this may be a random value. */ + LONGEST val; + + regcache_cooked_read_signed (regcache, V0_REGNUM, &val); + return val; +} + /* Exported procedure: Is PC in the signal trampoline code */ static int @@ -4989,7 +5063,7 @@ mips_show_processor_type_command (char *args, int from_tty) /* Modify the actual processor type. */ -int +static int mips_set_processor_type (char *str) { int i; @@ -5091,7 +5165,7 @@ gdb_print_insn_mips (bfd_vma memaddr, disassemble_info *info) (if necessary) to point to the actual memory location where the breakpoint should be inserted. */ -const unsigned char * +static const unsigned char * mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) { if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) @@ -5173,7 +5247,7 @@ mips_breakpoint_from_pc (CORE_ADDR * pcptr, int *lenptr) This function implements the SKIP_TRAMPOLINE_CODE macro. */ -CORE_ADDR +static CORE_ADDR mips_skip_stub (CORE_ADDR pc) { char *name; @@ -5256,7 +5330,7 @@ mips_skip_stub (CORE_ADDR pc) /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ -int +static int mips_in_call_stub (CORE_ADDR pc, char *name) { CORE_ADDR start_addr; @@ -5284,7 +5358,7 @@ mips_in_call_stub (CORE_ADDR pc, char *name) /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ -int +static int mips_in_return_stub (CORE_ADDR pc, char *name) { CORE_ADDR start_addr; @@ -5334,7 +5408,7 @@ mips_ignore_helper (CORE_ADDR pc) point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS whose address is the location where the breakpoint should be placed. */ -CORE_ADDR +static CORE_ADDR mips_call_dummy_address (void) { struct minimal_symbol *sym; @@ -5376,59 +5450,47 @@ mips_coerce_float_to_double (struct type *formal, struct type *actual) static void mips_get_saved_register (char *raw_buffer, - int *optimized, + int *optimizedp, CORE_ADDR *addrp, struct frame_info *frame, int regnum, - enum lval_type *lval) + enum lval_type *lvalp) { - CORE_ADDR addr; + CORE_ADDR addrx; + enum lval_type lvalx; + int optimizedx; + int realnum; if (!target_has_registers) error ("No registers."); - /* Normal systems don't optimize out things with register numbers. */ - if (optimized != NULL) - *optimized = 0; - addr = find_saved_register (frame, regnum); - if (addr != 0) + /* Make certain that all needed parameters are present. */ + if (addrp == NULL) + addrp = &addrx; + if (lvalp == NULL) + lvalp = &lvalx; + if (optimizedp == NULL) + optimizedp = &optimizedx; + frame_register_unwind (get_next_frame (frame), regnum, optimizedp, lvalp, + addrp, &realnum, raw_buffer); + /* FIXME: cagney/2002-09-13: This is just so bad. The MIPS should + have a pseudo register range that correspons to the ABI's, rather + than the ISA's, view of registers. These registers would then + implicitly describe their size and hence could be used without + the below munging. */ + if ((*lvalp) == lval_memory) { - if (lval != NULL) - *lval = lval_memory; - if (regnum == SP_REGNUM) - { - if (raw_buffer != NULL) - { - /* Put it back in target format. */ - store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), - (LONGEST) addr); - } - if (addrp != NULL) - *addrp = 0; - return; - } if (raw_buffer != NULL) { - LONGEST val; if (regnum < 32) - /* Only MIPS_SAVED_REGSIZE bytes of GP registers are - saved. */ - val = read_memory_integer (addr, MIPS_SAVED_REGSIZE); - else - val = read_memory_integer (addr, REGISTER_RAW_SIZE (regnum)); - store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); + { + /* Only MIPS_SAVED_REGSIZE bytes of GP registers are + saved. */ + LONGEST val = read_memory_integer ((*addrp), MIPS_SAVED_REGSIZE); + store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), val); + } } } - else - { - if (lval != NULL) - *lval = lval_register; - addr = REGISTER_BYTE (regnum); - if (raw_buffer != NULL) - read_register_gen (regnum, raw_buffer); - } - if (addrp != NULL) - *addrp = addr; } /* Immediately after a function call, return the saved pc. @@ -5668,11 +5730,14 @@ mips_gdbarch_init (struct gdbarch_info info, tdep->found_abi = found_abi; tdep->mips_abi = mips_abi; + set_gdbarch_elf_make_msymbol_special (gdbarch, + mips_elf_make_msymbol_special); + switch (mips_abi) { case MIPS_ABI_O32: set_gdbarch_push_arguments (gdbarch, mips_o32_push_arguments); - set_gdbarch_store_return_value (gdbarch, mips_o32_store_return_value); + set_gdbarch_deprecated_store_return_value (gdbarch, mips_o32_store_return_value); set_gdbarch_extract_return_value (gdbarch, mips_o32_extract_return_value); tdep->mips_default_saved_regsize = 4; tdep->mips_default_stack_argsize = 4; @@ -5691,7 +5756,7 @@ mips_gdbarch_init (struct gdbarch_info info, break; case MIPS_ABI_O64: set_gdbarch_push_arguments (gdbarch, mips_o64_push_arguments); - set_gdbarch_store_return_value (gdbarch, mips_o64_store_return_value); + set_gdbarch_deprecated_store_return_value (gdbarch, mips_o64_store_return_value); set_gdbarch_deprecated_extract_return_value (gdbarch, mips_o64_extract_return_value); tdep->mips_default_saved_regsize = 8; tdep->mips_default_stack_argsize = 8; @@ -5710,7 +5775,7 @@ mips_gdbarch_init (struct gdbarch_info info, break; case MIPS_ABI_EABI32: set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); - set_gdbarch_store_return_value (gdbarch, mips_eabi_store_return_value); + set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); tdep->mips_default_saved_regsize = 4; tdep->mips_default_stack_argsize = 4; @@ -5729,7 +5794,7 @@ mips_gdbarch_init (struct gdbarch_info info, break; case MIPS_ABI_EABI64: set_gdbarch_push_arguments (gdbarch, mips_eabi_push_arguments); - set_gdbarch_store_return_value (gdbarch, mips_eabi_store_return_value); + set_gdbarch_deprecated_store_return_value (gdbarch, mips_eabi_store_return_value); set_gdbarch_deprecated_extract_return_value (gdbarch, mips_eabi_extract_return_value); tdep->mips_default_saved_regsize = 8; tdep->mips_default_stack_argsize = 8; @@ -5748,7 +5813,7 @@ mips_gdbarch_init (struct gdbarch_info info, break; case MIPS_ABI_N32: set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); - set_gdbarch_store_return_value (gdbarch, mips_n32n64_store_return_value); + set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); tdep->mips_default_saved_regsize = 8; tdep->mips_default_stack_argsize = 8; @@ -5779,7 +5844,7 @@ mips_gdbarch_init (struct gdbarch_info info, break; case MIPS_ABI_N64: set_gdbarch_push_arguments (gdbarch, mips_n32n64_push_arguments); - set_gdbarch_store_return_value (gdbarch, mips_n32n64_store_return_value); + set_gdbarch_deprecated_store_return_value (gdbarch, mips_n32n64_store_return_value); set_gdbarch_extract_return_value (gdbarch, mips_n32n64_extract_return_value); tdep->mips_default_saved_regsize = 8; tdep->mips_default_stack_argsize = 8; @@ -5860,10 +5925,13 @@ mips_gdbarch_init (struct gdbarch_info info, register name management is part way between the old - #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr). Further work on it is required. */ + /* NOTE: many targets (esp. embedded) do not go thru the + gdbarch_register_name vector at all, instead bypassing it + by defining REGISTER_NAMES. */ set_gdbarch_register_name (gdbarch, mips_register_name); set_gdbarch_read_pc (gdbarch, mips_read_pc); set_gdbarch_write_pc (gdbarch, generic_target_write_pc); - set_gdbarch_read_fp (gdbarch, generic_target_read_fp); + set_gdbarch_read_fp (gdbarch, mips_read_sp); /* Draft FRAME base. */ set_gdbarch_read_sp (gdbarch, mips_read_sp); set_gdbarch_write_sp (gdbarch, generic_target_write_sp); @@ -5891,14 +5959,19 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_use_generic_dummy_frames (gdbarch, 0); set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); set_gdbarch_call_dummy_address (gdbarch, mips_call_dummy_address); + set_gdbarch_push_return_address (gdbarch, mips_push_return_address); + set_gdbarch_push_dummy_frame (gdbarch, mips_push_dummy_frame); + set_gdbarch_pop_frame (gdbarch, mips_pop_frame); set_gdbarch_call_dummy_start_offset (gdbarch, 0); set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); set_gdbarch_call_dummy_length (gdbarch, 0); + set_gdbarch_fix_call_dummy (gdbarch, mips_fix_call_dummy); set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point); set_gdbarch_call_dummy_words (gdbarch, mips_call_dummy_words); set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (mips_call_dummy_words)); set_gdbarch_push_return_address (gdbarch, mips_push_return_address); + set_gdbarch_frame_align (gdbarch, mips_frame_align); set_gdbarch_register_convertible (gdbarch, mips_register_convertible); set_gdbarch_register_convert_to_virtual (gdbarch, mips_register_convert_to_virtual); @@ -5907,7 +5980,16 @@ mips_gdbarch_init (struct gdbarch_info info, set_gdbarch_coerce_float_to_double (gdbarch, mips_coerce_float_to_double); + set_gdbarch_frame_chain (gdbarch, mips_frame_chain); set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid); + set_gdbarch_frameless_function_invocation (gdbarch, + generic_frameless_function_invocation_not); + set_gdbarch_frame_saved_pc (gdbarch, mips_frame_saved_pc); + set_gdbarch_frame_args_address (gdbarch, default_frame_address); + set_gdbarch_frame_locals_address (gdbarch, default_frame_address); + set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); + set_gdbarch_frame_args_skip (gdbarch, 0); + set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register); set_gdbarch_inner_than (gdbarch, core_addr_lessthan); @@ -5934,6 +6016,15 @@ mips_gdbarch_init (struct gdbarch_info info, /* Hook in OS ABI-specific overrides, if they have been registered. */ gdbarch_init_osabi (info, gdbarch, osabi); + set_gdbarch_store_struct_return (gdbarch, mips_store_struct_return); + set_gdbarch_extract_struct_value_address (gdbarch, + mips_extract_struct_value_address); + + set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_stub); + + set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); + set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); + return gdbarch; } @@ -6055,9 +6146,6 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) fprintf_unfiltered (file, "mips_dump_tdep: CPLUS_MARKER = %c\n", CPLUS_MARKER); - fprintf_unfiltered (file, - "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n", - DEFAULT_MIPS_TYPE); fprintf_unfiltered (file, "mips_dump_tdep: DO_REGISTERS_INFO # %s\n", XSTRING (DO_REGISTERS_INFO)); @@ -6067,9 +6155,6 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) fprintf_unfiltered (file, "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); - fprintf_unfiltered (file, - "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n", - XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM, MSYM))); fprintf_unfiltered (file, "mips_dump_tdep: FCRCS_REGNUM = %d\n", FCRCS_REGNUM); @@ -6166,11 +6251,6 @@ mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) fprintf_unfiltered (file, "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n", MIPS_SAVED_REGSIZE); - fprintf_unfiltered (file, - "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n"); - fprintf_unfiltered (file, - "mips_dump_tdep: MSYMBOL_SIZE # %s\n", - XSTRING (MSYMBOL_SIZE (MSYM))); fprintf_unfiltered (file, "mips_dump_tdep: OP_LDFPR = used?\n"); fprintf_unfiltered (file,