X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fmips-tdep.h;h=ff0b9e1f4e9b7a4ecf07c4478485b36ef4a9212d;hb=7cac64af7bc6a7f7a86f90a1465f7c3d2b6f07e8;hp=9dd45418ae90cc70f43cbbcc3b99f453d7290d2c;hpb=5a4398495b075cef77112aed5e98a6dddf3ee5b8;p=deliverable%2Fbinutils-gdb.git

diff --git a/gdb/mips-tdep.h b/gdb/mips-tdep.h
index 9dd45418ae..ff0b9e1f4e 100644
--- a/gdb/mips-tdep.h
+++ b/gdb/mips-tdep.h
@@ -1,6 +1,6 @@
 /* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
 
-   Copyright (C) 2002-2003, 2007-2012 Free Software Foundation, Inc.
+   Copyright (C) 2002-2019 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -20,6 +20,8 @@
 #ifndef MIPS_TDEP_H
 #define MIPS_TDEP_H
 
+#include "objfiles.h"
+
 struct gdbarch;
 
 /* All the possible MIPS ABIs.  */
@@ -38,6 +40,18 @@ enum mips_abi
 /* Return the MIPS ABI associated with GDBARCH.  */
 enum mips_abi mips_abi (struct gdbarch *gdbarch);
 
+/* Base and compressed MIPS ISA variations.  */
+enum mips_isa
+  {
+    ISA_MIPS = -1,		/* mips_compression_string depends on it.  */
+    ISA_MIPS16,
+    ISA_MICROMIPS
+  };
+
+/* Corresponding MSYMBOL_TARGET_FLAG aliases.  */
+#define MSYMBOL_TARGET_FLAG_MIPS16 MSYMBOL_TARGET_FLAG_1
+#define MSYMBOL_TARGET_FLAG_MICROMIPS MSYMBOL_TARGET_FLAG_2
+
 /* Return the MIPS ISA's register size.  Just a short cut to the BFD
    architecture's word size.  */
 extern int mips_isa_regsize (struct gdbarch *gdbarch);
@@ -77,6 +91,7 @@ struct gdbarch_tdep
   /* mips options */
   enum mips_abi mips_abi;
   enum mips_abi found_abi;
+  enum mips_isa mips_isa;
   enum mips_fpu_type mips_fpu_type;
   int mips_last_arg_regnum;
   int mips_last_fp_arg_regnum;
@@ -98,14 +113,6 @@ struct gdbarch_tdep
   int register_size_valid_p;
   int register_size;
 
-  /* General-purpose registers.  */
-  struct regset *gregset;
-  struct regset *gregset64;
-
-  /* Floating-point registers.  */
-  struct regset *fpregset;
-  struct regset *fpregset64;
-
   /* Return the expected next PC if FRAME is stopped at a syscall
      instruction.  */
   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
@@ -137,9 +144,6 @@ enum
   MIPS_LAST_EMBED_REGNUM = 89	/* Last one.  */
 };
 
-/* Defined in mips-tdep.c and used in remote-mips.c.  */
-extern void deprecated_mips_set_processor_regs_hack (void);
-
 /* Instruction sizes and other useful constants.  */
 enum
 {
@@ -150,11 +154,23 @@ enum
 };
 
 /* Single step based on where the current instruction will take us.  */
-extern int mips_software_single_step (struct frame_info *frame);
+extern std::vector<CORE_ADDR> mips_software_single_step
+  (struct regcache *regcache);
+
+/* Strip the ISA (compression) bit off from ADDR.  */
+extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr);
+
+/* Tell if the program counter value in MEMADDR is in a standard
+   MIPS function.  */
+extern int mips_pc_is_mips (bfd_vma memaddr);
 
 /* Tell if the program counter value in MEMADDR is in a MIPS16
    function.  */
-extern int mips_pc_is_mips16 (bfd_vma memaddr);
+extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, bfd_vma memaddr);
+
+/* Tell if the program counter value in MEMADDR is in a microMIPS
+   function.  */
+extern int mips_pc_is_micromips (struct gdbarch *gdbarch, bfd_vma memaddr);
 
 /* Return the currently configured (or set) saved register size.  */
 extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
@@ -167,4 +183,12 @@ extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc);
 extern struct target_desc *mips_tdesc_gp32;
 extern struct target_desc *mips_tdesc_gp64;
 
+/* Return non-zero if PC is in a MIPS SVR4 lazy binding stub section.  */
+
+static inline int
+in_mips_stubs_section (CORE_ADDR pc)
+{
+  return pc_in_section (pc, ".MIPS.stubs");
+}
+
 #endif /* MIPS_TDEP_H */