X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fppc-linux-nat.c;h=a56d154d3126c69431eff0717d6b4bcbe15f9d96;hb=a7785f8c797183eb363e95c201343df67d8536c6;hp=297365bfa64535034d9b81f8c91ddf8013adccf4;hpb=1dfe79e8d532f68cd4a017f17c1f9c9d5e2d835e;p=deliverable%2Fbinutils-gdb.git

diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index 297365bfa6..a56d154d31 100644
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -1,7 +1,6 @@
 /* PPC GNU/Linux native support.
 
-   Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,
-   2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+   Copyright (C) 1988-2017 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -19,27 +18,24 @@
    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 #include "defs.h"
-#include "gdb_string.h"
+#include "observer.h"
 #include "frame.h"
 #include "inferior.h"
+#include "gdbthread.h"
 #include "gdbcore.h"
 #include "regcache.h"
-#include "gdb_assert.h"
 #include "target.h"
 #include "linux-nat.h"
-
-#include <stdint.h>
 #include <sys/types.h>
-#include <sys/param.h>
 #include <signal.h>
 #include <sys/user.h>
 #include <sys/ioctl.h>
 #include "gdb_wait.h"
 #include <fcntl.h>
 #include <sys/procfs.h>
-#include <sys/ptrace.h>
+#include "nat/gdb_ptrace.h"
 
-/* Prototypes for supply_gregset etc. */
+/* Prototypes for supply_gregset etc.  */
 #include "gregset.h"
 #include "ppc-tdep.h"
 #include "ppc-linux-tdep.h"
@@ -48,56 +44,10 @@
 #include "elf/common.h"
 #include "auxv.h"
 
-/* This sometimes isn't defined.  */
-#ifndef PT_ORIG_R3
-#define PT_ORIG_R3 34
-#endif
-#ifndef PT_TRAP
-#define PT_TRAP 40
-#endif
-
-/* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
-   If they aren't, we can provide them ourselves (their values are fixed
-   because they are part of the kernel ABI).  They are used in the AT_HWCAP
-   entry of the AUXV.  */
-#ifndef PPC_FEATURE_BOOKE
-#define PPC_FEATURE_BOOKE 0x00008000
-#endif
-#ifndef PPC_FEATURE_HAS_DFP
-#define PPC_FEATURE_HAS_DFP	0x00000400  /* Decimal Floating Point.  */
-#endif
-
-/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
-   configure time check.  Some older glibc's (for instance 2.2.1)
-   don't have a specific powerpc version of ptrace.h, and fall back on
-   a generic one.  In such cases, sys/ptrace.h defines
-   PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
-   ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
-   PTRACE_SETVRREGS to be.  This also makes a configury check pretty
-   much useless.  */
-
-/* These definitions should really come from the glibc header files,
-   but Glibc doesn't know about the vrregs yet.  */
-#ifndef PTRACE_GETVRREGS
-#define PTRACE_GETVRREGS 18
-#define PTRACE_SETVRREGS 19
-#endif
-
-/* PTRACE requests for POWER7 VSX registers.  */
-#ifndef PTRACE_GETVSXREGS
-#define PTRACE_GETVSXREGS 27
-#define PTRACE_SETVSXREGS 28
-#endif
-
-/* Similarly for the ptrace requests for getting / setting the SPE
-   registers (ev0 -- ev31, acc, and spefscr).  See the description of
-   gdb_evrregset_t for details.  */
-#ifndef PTRACE_GETEVRREGS
-#define PTRACE_GETEVRREGS 20
-#define PTRACE_SETEVRREGS 21
-#endif
+#include "nat/ppc-linux.h"
 
-/* Similarly for the hardware watchpoint support.  */
+/* Similarly for the hardware watchpoint support.  These requests are used
+   when the PowerPC HWDEBUG ptrace interface is not available.  */
 #ifndef PTRACE_GET_DEBUGREG
 #define PTRACE_GET_DEBUGREG    25
 #endif
@@ -108,6 +58,77 @@
 #define PTRACE_GETSIGINFO    0x4202
 #endif
 
+/* These requests are used when the PowerPC HWDEBUG ptrace interface is
+   available.  It exposes the debug facilities of PowerPC processors, as well
+   as additional features of BookE processors, such as ranged breakpoints and
+   watchpoints and hardware-accelerated condition evaluation.  */
+#ifndef PPC_PTRACE_GETHWDBGINFO
+
+/* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG 
+   ptrace interface is not present in ptrace.h, so we'll have to pretty much
+   include it all here so that the code at least compiles on older systems.  */
+#define PPC_PTRACE_GETHWDBGINFO 0x89
+#define PPC_PTRACE_SETHWDEBUG   0x88
+#define PPC_PTRACE_DELHWDEBUG   0x87
+
+struct ppc_debug_info
+{
+        uint32_t version;               /* Only version 1 exists to date.  */
+        uint32_t num_instruction_bps;
+        uint32_t num_data_bps;
+        uint32_t num_condition_regs;
+        uint32_t data_bp_alignment;
+        uint32_t sizeof_condition;      /* size of the DVC register.  */
+        uint64_t features;
+};
+
+/* Features will have bits indicating whether there is support for:  */
+#define PPC_DEBUG_FEATURE_INSN_BP_RANGE         0x1
+#define PPC_DEBUG_FEATURE_INSN_BP_MASK          0x2
+#define PPC_DEBUG_FEATURE_DATA_BP_RANGE         0x4
+#define PPC_DEBUG_FEATURE_DATA_BP_MASK          0x8
+
+struct ppc_hw_breakpoint
+{
+        uint32_t version;               /* currently, version must be 1 */
+        uint32_t trigger_type;          /* only some combinations allowed */
+        uint32_t addr_mode;             /* address match mode */
+        uint32_t condition_mode;        /* break/watchpoint condition flags */
+        uint64_t addr;                  /* break/watchpoint address */
+        uint64_t addr2;                 /* range end or mask */
+        uint64_t condition_value;       /* contents of the DVC register */
+};
+
+/* Trigger type.  */
+#define PPC_BREAKPOINT_TRIGGER_EXECUTE  0x1
+#define PPC_BREAKPOINT_TRIGGER_READ     0x2
+#define PPC_BREAKPOINT_TRIGGER_WRITE    0x4
+#define PPC_BREAKPOINT_TRIGGER_RW       0x6
+
+/* Address mode.  */
+#define PPC_BREAKPOINT_MODE_EXACT               0x0
+#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE     0x1
+#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE     0x2
+#define PPC_BREAKPOINT_MODE_MASK                0x3
+
+/* Condition mode.  */
+#define PPC_BREAKPOINT_CONDITION_NONE   0x0
+#define PPC_BREAKPOINT_CONDITION_AND    0x1
+#define PPC_BREAKPOINT_CONDITION_EXACT  0x1
+#define PPC_BREAKPOINT_CONDITION_OR     0x2
+#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
+#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
+#define PPC_BREAKPOINT_CONDITION_BE_SHIFT       16
+#define PPC_BREAKPOINT_CONDITION_BE(n)  \
+        (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
+#endif /* PPC_PTRACE_GETHWDBGINFO */
+
+/* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
+   watchpoint (up to 512 bytes).  */
+#ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
+#define PPC_DEBUG_FEATURE_DATA_BP_DAWR	0x10
+#endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
+
 /* Similarly for the general-purpose (gp0 -- gp31)
    and floating-point registers (fp0 -- fp31).  */
 #ifndef PTRACE_GETREGS
@@ -131,7 +152,7 @@
 
    There are 32 vector registers 16 bytes longs, plus a VSCR register
    which is only 4 bytes long, but is fetched as a 16 bytes
-   quantity. Up to here we have the elf_vrregset_t structure.
+   quantity.  Up to here we have the elf_vrregset_t structure.
    Appended to this there is space for the VRSAVE register: 4 bytes.
    Even though this vrsave register is not included in the regset
    typedef, it is handled by the ptrace requests.
@@ -190,7 +211,7 @@ typedef char gdb_vrregset_t[SIZEOF_VRREGS];
 
 typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
 
-/* On PPC processors that support the the Signal Processing Extension
+/* On PPC processors that support the Signal Processing Extension
    (SPE) APU, the general-purpose registers are 64 bits long.
    However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
    ptrace calls only access the lower half of each register, to allow
@@ -201,7 +222,7 @@ typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
 
    GDB itself continues to claim the general-purpose registers are 32
    bits long.  It has unnamed raw registers that hold the upper halves
-   of the gprs, and the the full 64-bit SIMD views of the registers,
+   of the gprs, and the full 64-bit SIMD views of the registers,
    'ev0' -- 'ev31', are pseudo-registers that splice the top and
    bottom halves together.
 
@@ -251,10 +272,14 @@ PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
-PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
-PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
-PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
-PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
+PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
+PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
+PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
+PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
+PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
+PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
+PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
+PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
 /* *INDENT_ON * */
 
@@ -267,7 +292,7 @@ ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
      interface, and not the wordsize of the program's ABI.  */
   int wordsize = sizeof (long);
 
-  /* General purpose registers occupy 1 slot each in the buffer */
+  /* General purpose registers occupy 1 slot each in the buffer.  */
   if (regno >= tdep->ppc_gp0_regnum 
       && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
     u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
@@ -280,7 +305,7 @@ ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
       && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
     u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
 
-  /* UISA special purpose registers: 1 slot each */
+  /* UISA special purpose registers: 1 slot each.  */
   if (regno == gdbarch_pc_regnum (gdbarch))
     u_addr = PT_NIP * wordsize;
   if (regno == tdep->ppc_lr_regnum)
@@ -385,7 +410,8 @@ fetch_altivec_register (struct regcache *regcache, int tid, int regno)
     offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
   
   regcache_raw_supply (regcache, regno,
-		       regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
+		       regs + (regno
+			       - tdep->ppc_vr0_regnum) * vrregsize + offset);
 }
 
 /* Fetch the top 32 bits of TID's general-purpose registers and the
@@ -469,8 +495,8 @@ fetch_register (struct regcache *regcache, int tid, int regno)
   /* This isn't really an address.  But ptrace thinks of it as one.  */
   CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
   int bytes_transferred;
-  unsigned int offset;         /* Offset of registers within the u area. */
-  char buf[MAX_REGISTER_SIZE];
+  unsigned int offset;         /* Offset of registers within the u area.  */
+  gdb_byte buf[MAX_REGISTER_SIZE];
 
   if (altivec_register_p (gdbarch, regno))
     {
@@ -515,17 +541,19 @@ fetch_register (struct regcache *regcache, int tid, int regno)
        bytes_transferred < register_size (gdbarch, regno);
        bytes_transferred += sizeof (long))
     {
+      long l;
+
       errno = 0;
-      *(long *) &buf[bytes_transferred]
-        = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
+      l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
       regaddr += sizeof (long);
       if (errno != 0)
 	{
           char message[128];
-	  sprintf (message, "reading register %s (#%d)", 
-		   gdbarch_register_name (gdbarch, regno), regno);
+	  xsnprintf (message, sizeof (message), "reading register %s (#%d)",
+		     gdbarch_register_name (gdbarch, regno), regno);
 	  perror_with_name (message);
 	}
+      memcpy (&buf[bytes_transferred], &l, sizeof (l));
     }
 
   /* Now supply the register.  Keep in mind that the regcache's idea
@@ -781,12 +809,12 @@ static void
 ppc_linux_fetch_inferior_registers (struct target_ops *ops,
 				    struct regcache *regcache, int regno)
 {
-  /* Overload thread id onto process id */
-  int tid = TIDGET (inferior_ptid);
+  /* Overload thread id onto process id.  */
+  int tid = ptid_get_lwp (inferior_ptid);
 
-  /* No thread id, just use process id */
+  /* No thread id, just use process id.  */
   if (tid == 0)
-    tid = PIDGET (inferior_ptid);
+    tid = ptid_get_pid (inferior_ptid);
 
   if (regno == -1)
     fetch_ppc_registers (regcache, tid);
@@ -794,7 +822,7 @@ ppc_linux_fetch_inferior_registers (struct target_ops *ops,
     fetch_register (regcache, tid, regno);
 }
 
-/* Store one VSX register. */
+/* Store one VSX register.  */
 static void
 store_vsx_register (const struct regcache *regcache, int tid, int regno)
 {
@@ -804,7 +832,7 @@ store_vsx_register (const struct regcache *regcache, int tid, int regno)
   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
   int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
 
-  ret = ptrace (PTRACE_SETVSXREGS, tid, 0, &regs);
+  ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
   if (ret < 0)
     {
       if (errno == EIO)
@@ -823,7 +851,7 @@ store_vsx_register (const struct regcache *regcache, int tid, int regno)
     perror_with_name (_("Unable to store VSX register"));
 }
 
-/* Store one register. */
+/* Store one register.  */
 static void
 store_altivec_register (const struct regcache *regcache, int tid, int regno)
 {
@@ -851,7 +879,8 @@ store_altivec_register (const struct regcache *regcache, int tid, int regno)
     offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
 
   regcache_raw_collect (regcache, regno,
-			regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
+			regs + (regno
+				- tdep->ppc_vr0_regnum) * vrregsize + offset);
 
   ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
   if (ret < 0)
@@ -954,7 +983,7 @@ store_register (const struct regcache *regcache, int tid, int regno)
   CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
   int i;
   size_t bytes_to_transfer;
-  char buf[MAX_REGISTER_SIZE];
+  gdb_byte buf[MAX_REGISTER_SIZE];
 
   if (altivec_register_p (gdbarch, regno))
     {
@@ -994,9 +1023,11 @@ store_register (const struct regcache *regcache, int tid, int regno)
 
   for (i = 0; i < bytes_to_transfer; i += sizeof (long))
     {
+      long l;
+
+      memcpy (&l, &buf[i], sizeof (l));
       errno = 0;
-      ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr,
-	      *(long *) &buf[i]);
+      ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
       regaddr += sizeof (long);
 
       if (errno == EIO 
@@ -1012,8 +1043,8 @@ store_register (const struct regcache *regcache, int tid, int regno)
       if (errno != 0)
 	{
           char message[128];
-	  sprintf (message, "writing register %s (#%d)", 
-		   gdbarch_register_name (gdbarch, regno), regno);
+	  xsnprintf (message, sizeof (message), "writing register %s (#%d)",
+		     gdbarch_register_name (gdbarch, regno), regno);
 	  perror_with_name (message);
 	}
     }
@@ -1267,153 +1298,952 @@ store_ppc_registers (const struct regcache *regcache, int tid)
     store_spe_register (regcache, tid, -1);
 }
 
+/* Fetch the AT_HWCAP entry from the aux vector.  */
+static unsigned long
+ppc_linux_get_hwcap (void)
+{
+  CORE_ADDR field;
+
+  if (target_auxv_search (&current_target, AT_HWCAP, &field))
+    return (unsigned long) field;
+
+  return 0;
+}
+
+/* The cached DABR value, to install in new threads.
+   This variable is used when the PowerPC HWDEBUG ptrace
+   interface is not available.  */
+static long saved_dabr_value;
+
+/* Global structure that will store information about the available
+   features provided by the PowerPC HWDEBUG ptrace interface.  */
+static struct ppc_debug_info hwdebug_info;
+
+/* Global variable that holds the maximum number of slots that the
+   kernel will use.  This is only used when PowerPC HWDEBUG ptrace interface
+   is available.  */
+static size_t max_slots_number = 0;
+
+struct hw_break_tuple
+{
+  long slot;
+  struct ppc_hw_breakpoint *hw_break;
+};
+
+/* This is an internal VEC created to store information about *points inserted
+   for each thread.  This is used when PowerPC HWDEBUG ptrace interface is
+   available.  */
+typedef struct thread_points
+  {
+    /* The TID to which this *point relates.  */
+    int tid;
+    /* Information about the *point, such as its address, type, etc.
+
+       Each element inside this vector corresponds to a hardware
+       breakpoint or watchpoint in the thread represented by TID.  The maximum
+       size of these vector is MAX_SLOTS_NUMBER.  If the hw_break element of
+       the tuple is NULL, then the position in the vector is free.  */
+    struct hw_break_tuple *hw_breaks;
+  } *thread_points_p;
+DEF_VEC_P (thread_points_p);
+
+VEC(thread_points_p) *ppc_threads = NULL;
+
+/* The version of the PowerPC HWDEBUG kernel interface that we will use, if
+   available.  */
+#define PPC_DEBUG_CURRENT_VERSION 1
+
+/* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface.  */
 static int
-ppc_linux_check_watch_resources (int type, int cnt, int ot)
+have_ptrace_hwdebug_interface (void)
 {
-  int tid;
-  ptid_t ptid = inferior_ptid;
+  static int have_ptrace_hwdebug_interface = -1;
 
-  /* DABR (data address breakpoint register) is optional for PPC variants.
-     Some variants have one DABR, others have none.  So CNT can't be larger
-     than 1.  */
-  if (cnt > 1)
-    return 0;
+  if (have_ptrace_hwdebug_interface == -1)
+    {
+      int tid;
 
-  /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether
-     the target has DABR.  If either answer is no, the ptrace call will
-     return -1.  Fail in that case.  */
-  tid = TIDGET (ptid);
-  if (tid == 0)
-    tid = PIDGET (ptid);
+      tid = ptid_get_lwp (inferior_ptid);
+      if (tid == 0)
+	tid = ptid_get_pid (inferior_ptid);
 
-  if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
-    return 0;
-  return 1;
+      /* Check for kernel support for PowerPC HWDEBUG ptrace interface.  */
+      if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0)
+	{
+	  /* Check whether PowerPC HWDEBUG ptrace interface is functional and
+	     provides any supported feature.  */
+	  if (hwdebug_info.features != 0)
+	    {
+	      have_ptrace_hwdebug_interface = 1;
+	      max_slots_number = hwdebug_info.num_instruction_bps
+	        + hwdebug_info.num_data_bps
+	        + hwdebug_info.num_condition_regs;
+	      return have_ptrace_hwdebug_interface;
+	    }
+	}
+      /* Old school interface and no PowerPC HWDEBUG ptrace support.  */
+      have_ptrace_hwdebug_interface = 0;
+      memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info));
+    }
+
+  return have_ptrace_hwdebug_interface;
 }
 
-/* Fetch the AT_HWCAP entry from the aux vector.  */
-unsigned long ppc_linux_get_hwcap (void)
+static int
+ppc_linux_can_use_hw_breakpoint (struct target_ops *self,
+				 enum bptype type, int cnt, int ot)
 {
-  CORE_ADDR field;
+  int total_hw_wp, total_hw_bp;
 
-  if (target_auxv_search (&current_target, AT_HWCAP, &field))
-    return (unsigned long) field;
+  if (have_ptrace_hwdebug_interface ())
+    {
+      /* When PowerPC HWDEBUG ptrace interface is available, the number of
+	 available hardware watchpoints and breakpoints is stored at the
+	 hwdebug_info struct.  */
+      total_hw_bp = hwdebug_info.num_instruction_bps;
+      total_hw_wp = hwdebug_info.num_data_bps;
+    }
+  else
+    {
+      /* When we do not have PowerPC HWDEBUG ptrace interface, we should
+	 consider having 1 hardware watchpoint and no hardware breakpoints.  */
+      total_hw_bp = 0;
+      total_hw_wp = 1;
+    }
 
-  return 0;
+  if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
+      || type == bp_access_watchpoint || type == bp_watchpoint)
+    {
+      if (cnt + ot > total_hw_wp)
+	return -1;
+    }
+  else if (type == bp_hardware_breakpoint)
+    {
+      if (total_hw_bp == 0)
+	{
+	  /* No hardware breakpoint support. */
+	  return 0;
+	}
+      if (cnt > total_hw_bp)
+	return -1;
+    }
+
+  if (!have_ptrace_hwdebug_interface ())
+    {
+      int tid;
+      ptid_t ptid = inferior_ptid;
+
+      /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
+	 and whether the target has DABR.  If either answer is no, the
+	 ptrace call will return -1.  Fail in that case.  */
+      tid = ptid_get_lwp (ptid);
+      if (tid == 0)
+	tid = ptid_get_pid (ptid);
+
+      if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
+	return 0;
+    }
+
+  return 1;
 }
 
 static int
-ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
+ppc_linux_region_ok_for_hw_watchpoint (struct target_ops *self,
+				       CORE_ADDR addr, int len)
 {
   /* Handle sub-8-byte quantities.  */
   if (len <= 0)
     return 0;
 
+  /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
+     restrictions for watchpoints in the processors.  In that case, we use that
+     information to determine the hardcoded watchable region for
+     watchpoints.  */
+  if (have_ptrace_hwdebug_interface ())
+    {
+      int region_size;
+      /* Embedded DAC-based processors, like the PowerPC 440 have ranged
+	 watchpoints and can watch any access within an arbitrary memory
+	 region. This is useful to watch arrays and structs, for instance.  It
+         takes two hardware watchpoints though.  */
+      if (len > 1
+	  && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE
+	  && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
+	return 2;
+      /* Check if the processor provides DAWR interface.  */
+      if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR)
+	/* DAWR interface allows to watch up to 512 byte wide ranges which
+	   can't cross a 512 byte boundary.  */
+	region_size = 512;
+      else
+	region_size = hwdebug_info.data_bp_alignment;
+      /* Server processors provide one hardware watchpoint and addr+len should
+         fall in the watchable region provided by the ptrace interface.  */
+      if (region_size
+	  && (addr + len > (addr & ~(region_size - 1)) + region_size))
+	return 0;
+    }
   /* addr+len must fall in the 8 byte watchable region for DABR-based
-     processors.  DAC-based processors, like the PowerPC 440, will use
-     addresses aligned to 4-bytes due to the way the read/write flags are
-     passed at the moment.  */
-  if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
-      && (addr + len) > (addr & ~3) + 4)
-      || (addr + len) > (addr & ~7) + 8)
+     processors (i.e., server processors).  Without the new PowerPC HWDEBUG 
+     ptrace interface, DAC-based processors (i.e., embedded processors) will
+     use addresses aligned to 4-bytes due to the way the read/write flags are
+     passed in the old ptrace interface.  */
+  else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
+	   && (addr + len) > (addr & ~3) + 4)
+	   || (addr + len) > (addr & ~7) + 8)
     return 0;
 
   return 1;
 }
 
-/* The cached DABR value, to install in new threads.  */
-static long saved_dabr_value;
+/* This function compares two ppc_hw_breakpoint structs field-by-field.  */
+static int
+hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
+{
+  return (a->trigger_type == b->trigger_type
+	  && a->addr_mode == b->addr_mode
+	  && a->condition_mode == b->condition_mode
+	  && a->addr == b->addr
+	  && a->addr2 == b->addr2
+	  && a->condition_value == b->condition_value);
+}
+
+/* This function can be used to retrieve a thread_points by the TID of the
+   related process/thread.  If nothing has been found, and ALLOC_NEW is 0,
+   it returns NULL.  If ALLOC_NEW is non-zero, a new thread_points for the
+   provided TID will be created and returned.  */
+static struct thread_points *
+hwdebug_find_thread_points_by_tid (int tid, int alloc_new)
+{
+  int i;
+  struct thread_points *t;
+
+  for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
+    if (t->tid == tid)
+      return t;
+
+  t = NULL;
+
+  /* Do we need to allocate a new point_item
+     if the wanted one does not exist?  */
+  if (alloc_new)
+    {
+      t = XNEW (struct thread_points);
+      t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number);
+      t->tid = tid;
+      VEC_safe_push (thread_points_p, ppc_threads, t);
+    }
+
+  return t;
+}
+
+/* This function is a generic wrapper that is responsible for inserting a
+   *point (i.e., calling `ptrace' in order to issue the request to the
+   kernel) and registering it internally in GDB.  */
+static void
+hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid)
+{
+  int i;
+  long slot;
+  struct ppc_hw_breakpoint *p = XNEW (struct ppc_hw_breakpoint);
+  struct hw_break_tuple *hw_breaks;
+  struct cleanup *c = make_cleanup (xfree, p);
+  struct thread_points *t;
+  struct hw_break_tuple *tuple;
+
+  memcpy (p, b, sizeof (struct ppc_hw_breakpoint));
+
+  errno = 0;
+  slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p);
+  if (slot < 0)
+    perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
+
+  /* Everything went fine, so we have to register this *point.  */
+  t = hwdebug_find_thread_points_by_tid (tid, 1);
+  gdb_assert (t != NULL);
+  hw_breaks = t->hw_breaks;
+
+  /* Find a free element in the hw_breaks vector.  */
+  for (i = 0; i < max_slots_number; i++)
+    if (hw_breaks[i].hw_break == NULL)
+      {
+	hw_breaks[i].slot = slot;
+	hw_breaks[i].hw_break = p;
+	break;
+      }
+
+  gdb_assert (i != max_slots_number);
+
+  discard_cleanups (c);
+}
+
+/* This function is a generic wrapper that is responsible for removing a
+   *point (i.e., calling `ptrace' in order to issue the request to the
+   kernel), and unregistering it internally at GDB.  */
+static void
+hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid)
+{
+  int i;
+  struct hw_break_tuple *hw_breaks;
+  struct thread_points *t;
+
+  t = hwdebug_find_thread_points_by_tid (tid, 0);
+  gdb_assert (t != NULL);
+  hw_breaks = t->hw_breaks;
+
+  for (i = 0; i < max_slots_number; i++)
+    if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b))
+      break;
+
+  gdb_assert (i != max_slots_number);
+
+  /* We have to ignore ENOENT errors because the kernel implements hardware
+     breakpoints/watchpoints as "one-shot", that is, they are automatically
+     deleted when hit.  */
+  errno = 0;
+  if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
+    if (errno != ENOENT)
+      perror_with_name (_("Unexpected error deleting "
+			  "breakpoint or watchpoint"));
+
+  xfree (hw_breaks[i].hw_break);
+  hw_breaks[i].hw_break = NULL;
+}
+
+/* Return the number of registers needed for a ranged breakpoint.  */
 
-/* Set a watchpoint of type TYPE at address ADDR.  */
 static int
-ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw)
+ppc_linux_ranged_break_num_registers (struct target_ops *target)
+{
+  return ((have_ptrace_hwdebug_interface ()
+	   && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)?
+	  2 : -1);
+}
+
+/* Insert the hardware breakpoint described by BP_TGT.  Returns 0 for
+   success, 1 if hardware breakpoints are not supported or -1 for failure.  */
+
+static int
+ppc_linux_insert_hw_breakpoint (struct target_ops *self,
+				struct gdbarch *gdbarch,
+				  struct bp_target_info *bp_tgt)
 {
   struct lwp_info *lp;
-  ptid_t ptid;
-  long dabr_value;
-  long read_mode, write_mode;
+  struct ppc_hw_breakpoint p;
 
-  if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
-  {
-  /* PowerPC 440 requires only the read/write flags to be passed
-     to the kernel.  */
-    read_mode  = 1;
-    write_mode = 2;
-  }
+  if (!have_ptrace_hwdebug_interface ())
+    return -1;
+
+  p.version = PPC_DEBUG_CURRENT_VERSION;
+  p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
+  p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+  p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address);
+  p.condition_value = 0;
+
+  if (bp_tgt->length)
+    {
+      p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+
+      /* The breakpoint will trigger if the address of the instruction is
+	 within the defined range, as follows: p.addr <= address < p.addr2.  */
+      p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
+    }
   else
-  {
-  /* PowerPC 970 and other DABR-based processors are required to pass
-     the Breakpoint Translation bit together with the flags.  */
-    read_mode  = 5;
-    write_mode = 6;
-  }
-
-  dabr_value = addr & ~(read_mode | write_mode);
-  switch (rw)
-    {
-    case hw_read:
-      /* Set read and translate bits.  */
-      dabr_value |= read_mode;
-      break;
-    case hw_write:
-      /* Set write and translate bits.  */
-      dabr_value |= write_mode;
-      break;
-    case hw_access:
-      /* Set read, write and translate bits.  */
-      dabr_value |= read_mode | write_mode;
-      break;
+    {
+      p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+      p.addr2 = 0;
     }
 
-  saved_dabr_value = dabr_value;
+  ALL_LWPS (lp)
+    hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
+
+  return 0;
+}
+
+static int
+ppc_linux_remove_hw_breakpoint (struct target_ops *self,
+				struct gdbarch *gdbarch,
+				  struct bp_target_info *bp_tgt)
+{
+  struct lwp_info *lp;
+  struct ppc_hw_breakpoint p;
+
+  if (!have_ptrace_hwdebug_interface ())
+    return -1;
+
+  p.version = PPC_DEBUG_CURRENT_VERSION;
+  p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
+  p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+  p.addr = (uint64_t) bp_tgt->placed_address;
+  p.condition_value = 0;
+
+  if (bp_tgt->length)
+    {
+      p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+
+      /* The breakpoint will trigger if the address of the instruction is within
+	 the defined range, as follows: p.addr <= address < p.addr2.  */
+      p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
+    }
+  else
+    {
+      p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+      p.addr2 = 0;
+    }
 
-  ALL_LWPS (lp, ptid)
-    if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0)
-      return -1;
+  ALL_LWPS (lp)
+    hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
 
   return 0;
 }
 
 static int
-ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw)
+get_trigger_type (enum target_hw_bp_type type)
+{
+  int t;
+
+  if (type == hw_read)
+    t = PPC_BREAKPOINT_TRIGGER_READ;
+  else if (type == hw_write)
+    t = PPC_BREAKPOINT_TRIGGER_WRITE;
+  else
+    t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
+
+  return t;
+}
+
+/* Insert a new masked watchpoint at ADDR using the mask MASK.
+   RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
+   or hw_access for an access watchpoint.  Returns 0 on success and throws
+   an error on failure.  */
+
+static int
+ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
+				  CORE_ADDR mask, enum target_hw_bp_type rw)
 {
   struct lwp_info *lp;
-  ptid_t ptid;
-  long dabr_value = 0;
+  struct ppc_hw_breakpoint p;
+
+  gdb_assert (have_ptrace_hwdebug_interface ());
+
+  p.version = PPC_DEBUG_CURRENT_VERSION;
+  p.trigger_type = get_trigger_type (rw);
+  p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
+  p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+  p.addr = addr;
+  p.addr2 = mask;
+  p.condition_value = 0;
+
+  ALL_LWPS (lp)
+    hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
 
-  saved_dabr_value = 0;
-  ALL_LWPS (lp, ptid)
-    if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value) < 0)
-      return -1;
   return 0;
 }
 
+/* Remove a masked watchpoint at ADDR with the mask MASK.
+   RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
+   or hw_access for an access watchpoint.  Returns 0 on success and throws
+   an error on failure.  */
+
+static int
+ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
+				  CORE_ADDR mask, enum target_hw_bp_type rw)
+{
+  struct lwp_info *lp;
+  struct ppc_hw_breakpoint p;
+
+  gdb_assert (have_ptrace_hwdebug_interface ());
+
+  p.version = PPC_DEBUG_CURRENT_VERSION;
+  p.trigger_type = get_trigger_type (rw);
+  p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
+  p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+  p.addr = addr;
+  p.addr2 = mask;
+  p.condition_value = 0;
+
+  ALL_LWPS (lp)
+    hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
+
+  return 0;
+}
+
+/* Check whether we have at least one free DVC register.  */
+static int
+can_use_watchpoint_cond_accel (void)
+{
+  struct thread_points *p;
+  int tid = ptid_get_lwp (inferior_ptid);
+  int cnt = hwdebug_info.num_condition_regs, i;
+  CORE_ADDR tmp_value;
+
+  if (!have_ptrace_hwdebug_interface () || cnt == 0)
+    return 0;
+
+  p = hwdebug_find_thread_points_by_tid (tid, 0);
+
+  if (p)
+    {
+      for (i = 0; i < max_slots_number; i++)
+	if (p->hw_breaks[i].hw_break != NULL
+	    && (p->hw_breaks[i].hw_break->condition_mode
+		!= PPC_BREAKPOINT_CONDITION_NONE))
+	  cnt--;
+
+      /* There are no available slots now.  */
+      if (cnt <= 0)
+	return 0;
+    }
+
+  return 1;
+}
+
+/* Calculate the enable bits and the contents of the Data Value Compare
+   debug register present in BookE processors.
+
+   ADDR is the address to be watched, LEN is the length of watched data
+   and DATA_VALUE is the value which will trigger the watchpoint.
+   On exit, CONDITION_MODE will hold the enable bits for the DVC, and
+   CONDITION_VALUE will hold the value which should be put in the
+   DVC register.  */
+static void
+calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
+	       uint32_t *condition_mode, uint64_t *condition_value)
+{
+  int i, num_byte_enable, align_offset, num_bytes_off_dvc,
+      rightmost_enabled_byte;
+  CORE_ADDR addr_end_data, addr_end_dvc;
+
+  /* The DVC register compares bytes within fixed-length windows which
+     are word-aligned, with length equal to that of the DVC register.
+     We need to calculate where our watch region is relative to that
+     window and enable comparison of the bytes which fall within it.  */
+
+  align_offset = addr % hwdebug_info.sizeof_condition;
+  addr_end_data = addr + len;
+  addr_end_dvc = (addr - align_offset
+		  + hwdebug_info.sizeof_condition);
+  num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
+			 addr_end_data - addr_end_dvc : 0;
+  num_byte_enable = len - num_bytes_off_dvc;
+  /* Here, bytes are numbered from right to left.  */
+  rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
+			      addr_end_dvc - addr_end_data : 0;
+
+  *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
+  for (i = 0; i < num_byte_enable; i++)
+    *condition_mode
+      |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
+
+  /* Now we need to match the position within the DVC of the comparison
+     value with where the watch region is relative to the window
+     (i.e., the ALIGN_OFFSET).  */
+
+  *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
+		      << rightmost_enabled_byte * 8);
+}
+
+/* Return the number of memory locations that need to be accessed to
+   evaluate the expression which generated the given value chain.
+   Returns -1 if there's any register access involved, or if there are
+   other kinds of values which are not acceptable in a condition
+   expression (e.g., lval_computed or lval_internalvar).  */
+static int
+num_memory_accesses (struct value *v)
+{
+  int found_memory_cnt = 0;
+  struct value *head = v;
+
+  /* The idea here is that evaluating an expression generates a series
+     of values, one holding the value of every subexpression.  (The
+     expression a*b+c has five subexpressions: a, b, a*b, c, and
+     a*b+c.)  GDB's values hold almost enough information to establish
+     the criteria given above --- they identify memory lvalues,
+     register lvalues, computed values, etcetera.  So we can evaluate
+     the expression, and then scan the chain of values that leaves
+     behind to determine the memory locations involved in the evaluation
+     of an expression.
+
+     However, I don't think that the values returned by inferior
+     function calls are special in any way.  So this function may not
+     notice that an expression contains an inferior function call.
+     FIXME.  */
+
+  for (; v; v = value_next (v))
+    {
+      /* Constants and values from the history are fine.  */
+      if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
+	continue;
+      else if (VALUE_LVAL (v) == lval_memory)
+	{
+	  /* A lazy memory lvalue is one that GDB never needed to fetch;
+	     we either just used its address (e.g., `a' in `a.b') or
+	     we never needed it at all (e.g., `a' in `a,b').  */
+	  if (!value_lazy (v))
+	    found_memory_cnt++;
+	}
+      /* Other kinds of values are not fine.  */
+      else
+	return -1;
+    }
+
+  return found_memory_cnt;
+}
+
+/* Verifies whether the expression COND can be implemented using the
+   DVC (Data Value Compare) register in BookE processors.  The expression
+   must test the watch value for equality with a constant expression.
+   If the function returns 1, DATA_VALUE will contain the constant against
+   which the watch value should be compared and LEN will contain the size
+   of the constant.  */
+static int
+check_condition (CORE_ADDR watch_addr, struct expression *cond,
+		 CORE_ADDR *data_value, int *len)
+{
+  int pc = 1, num_accesses_left, num_accesses_right;
+  struct value *left_val, *right_val, *left_chain, *right_chain;
+
+  if (cond->elts[0].opcode != BINOP_EQUAL)
+    return 0;
+
+  fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
+  num_accesses_left = num_memory_accesses (left_chain);
+
+  if (left_val == NULL || num_accesses_left < 0)
+    {
+      free_value_chain (left_chain);
+
+      return 0;
+    }
+
+  fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
+  num_accesses_right = num_memory_accesses (right_chain);
+
+  if (right_val == NULL || num_accesses_right < 0)
+    {
+      free_value_chain (left_chain);
+      free_value_chain (right_chain);
+
+      return 0;
+    }
+
+  if (num_accesses_left == 1 && num_accesses_right == 0
+      && VALUE_LVAL (left_val) == lval_memory
+      && value_address (left_val) == watch_addr)
+    {
+      *data_value = value_as_long (right_val);
+
+      /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
+	 the same type as the memory region referenced by LEFT_VAL.  */
+      *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
+    }
+  else if (num_accesses_left == 0 && num_accesses_right == 1
+	   && VALUE_LVAL (right_val) == lval_memory
+	   && value_address (right_val) == watch_addr)
+    {
+      *data_value = value_as_long (left_val);
+
+      /* DATA_VALUE is the constant in LEFT_VAL, but actually has
+	 the same type as the memory region referenced by RIGHT_VAL.  */
+      *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
+    }
+  else
+    {
+      free_value_chain (left_chain);
+      free_value_chain (right_chain);
+
+      return 0;
+    }
+
+  free_value_chain (left_chain);
+  free_value_chain (right_chain);
+
+  return 1;
+}
+
+/* Return non-zero if the target is capable of using hardware to evaluate
+   the condition expression, thus only triggering the watchpoint when it is
+   true.  */
+static int
+ppc_linux_can_accel_watchpoint_condition (struct target_ops *self,
+					  CORE_ADDR addr, int len, int rw,
+					  struct expression *cond)
+{
+  CORE_ADDR data_value;
+
+  return (have_ptrace_hwdebug_interface ()
+	  && hwdebug_info.num_condition_regs > 0
+	  && check_condition (addr, cond, &data_value, &len));
+}
+
+/* Set up P with the parameters necessary to request a watchpoint covering
+   LEN bytes starting at ADDR and if possible with condition expression COND
+   evaluated by hardware.  INSERT tells if we are creating a request for
+   inserting or removing the watchpoint.  */
+
+static void
+create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
+			   int len, enum target_hw_bp_type type,
+			   struct expression *cond, int insert)
+{
+  if (len == 1
+      || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
+    {
+      int use_condition;
+      CORE_ADDR data_value;
+
+      use_condition = (insert? can_use_watchpoint_cond_accel ()
+			: hwdebug_info.num_condition_regs > 0);
+      if (cond && use_condition && check_condition (addr, cond,
+						    &data_value, &len))
+	calculate_dvc (addr, len, data_value, &p->condition_mode,
+		       &p->condition_value);
+      else
+	{
+	  p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+	  p->condition_value = 0;
+	}
+
+      p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+      p->addr2 = 0;
+    }
+  else
+    {
+      p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+      p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+      p->condition_value = 0;
+
+      /* The watchpoint will trigger if the address of the memory access is
+	 within the defined range, as follows: p->addr <= address < p->addr2.
+
+	 Note that the above sentence just documents how ptrace interprets
+	 its arguments; the watchpoint is set to watch the range defined by
+	 the user _inclusively_, as specified by the user interface.  */
+      p->addr2 = (uint64_t) addr + len;
+    }
+
+  p->version = PPC_DEBUG_CURRENT_VERSION;
+  p->trigger_type = get_trigger_type (type);
+  p->addr = (uint64_t) addr;
+}
+
+static int
+ppc_linux_insert_watchpoint (struct target_ops *self, CORE_ADDR addr, int len,
+			     enum target_hw_bp_type type,
+			     struct expression *cond)
+{
+  struct lwp_info *lp;
+  int ret = -1;
+
+  if (have_ptrace_hwdebug_interface ())
+    {
+      struct ppc_hw_breakpoint p;
+
+      create_watchpoint_request (&p, addr, len, type, cond, 1);
+
+      ALL_LWPS (lp)
+	hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
+
+      ret = 0;
+    }
+  else
+    {
+      long dabr_value;
+      long read_mode, write_mode;
+
+      if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
+	{
+	  /* PowerPC 440 requires only the read/write flags to be passed
+	     to the kernel.  */
+	  read_mode = 1;
+	  write_mode = 2;
+	}
+      else
+	{
+	  /* PowerPC 970 and other DABR-based processors are required to pass
+	     the Breakpoint Translation bit together with the flags.  */
+	  read_mode = 5;
+	  write_mode = 6;
+	}
+
+      dabr_value = addr & ~(read_mode | write_mode);
+      switch (type)
+	{
+	  case hw_read:
+	    /* Set read and translate bits.  */
+	    dabr_value |= read_mode;
+	    break;
+	  case hw_write:
+	    /* Set write and translate bits.  */
+	    dabr_value |= write_mode;
+	    break;
+	  case hw_access:
+	    /* Set read, write and translate bits.  */
+	    dabr_value |= read_mode | write_mode;
+	    break;
+	}
+
+      saved_dabr_value = dabr_value;
+
+      ALL_LWPS (lp)
+	if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
+		    saved_dabr_value) < 0)
+	  return -1;
+
+      ret = 0;
+    }
+
+  return ret;
+}
+
+static int
+ppc_linux_remove_watchpoint (struct target_ops *self, CORE_ADDR addr, int len,
+			     enum target_hw_bp_type type,
+			     struct expression *cond)
+{
+  struct lwp_info *lp;
+  int ret = -1;
+
+  if (have_ptrace_hwdebug_interface ())
+    {
+      struct ppc_hw_breakpoint p;
+
+      create_watchpoint_request (&p, addr, len, type, cond, 0);
+
+      ALL_LWPS (lp)
+	hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
+
+      ret = 0;
+    }
+  else
+    {
+      saved_dabr_value = 0;
+      ALL_LWPS (lp)
+	if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
+		    saved_dabr_value) < 0)
+	  return -1;
+
+      ret = 0;
+    }
+
+  return ret;
+}
+
 static void
-ppc_linux_new_thread (ptid_t ptid)
+ppc_linux_new_thread (struct lwp_info *lp)
 {
-  ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0, saved_dabr_value);
+  int tid = ptid_get_lwp (lp->ptid);
+
+  if (have_ptrace_hwdebug_interface ())
+    {
+      int i;
+      struct thread_points *p;
+      struct hw_break_tuple *hw_breaks;
+
+      if (VEC_empty (thread_points_p, ppc_threads))
+	return;
+
+      /* Get a list of breakpoints from any thread.  */
+      p = VEC_last (thread_points_p, ppc_threads);
+      hw_breaks = p->hw_breaks;
+
+      /* Copy that thread's breakpoints and watchpoints to the new thread.  */
+      for (i = 0; i < max_slots_number; i++)
+	if (hw_breaks[i].hw_break)
+	  {
+	    /* Older kernels did not make new threads inherit their parent
+	       thread's debug state, so we always clear the slot and replicate
+	       the debug state ourselves, ensuring compatibility with all
+	       kernels.  */
+
+	    /* The ppc debug resource accounting is done through "slots".
+	       Ask the kernel the deallocate this specific *point's slot.  */
+	    ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
+
+	    hwdebug_insert_point (hw_breaks[i].hw_break, tid);
+	  }
+    }
+  else
+    ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
+}
+
+static void
+ppc_linux_thread_exit (struct thread_info *tp, int silent)
+{
+  int i;
+  int tid = ptid_get_lwp (tp->ptid);
+  struct hw_break_tuple *hw_breaks;
+  struct thread_points *t = NULL, *p;
+
+  if (!have_ptrace_hwdebug_interface ())
+    return;
+
+  for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
+    if (p->tid == tid)
+      {
+	t = p;
+	break;
+      }
+
+  if (t == NULL)
+    return;
+
+  VEC_unordered_remove (thread_points_p, ppc_threads, i);
+
+  hw_breaks = t->hw_breaks;
+
+  for (i = 0; i < max_slots_number; i++)
+    if (hw_breaks[i].hw_break)
+      xfree (hw_breaks[i].hw_break);
+
+  xfree (t->hw_breaks);
+  xfree (t);
 }
 
 static int
 ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
 {
-  struct siginfo *siginfo_p;
+  siginfo_t siginfo;
 
-  siginfo_p = linux_nat_get_siginfo (inferior_ptid);
+  if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
+    return 0;
 
-  if (siginfo_p->si_signo != SIGTRAP
-      || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
+  if (siginfo.si_signo != SIGTRAP
+      || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
     return 0;
 
-  *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr;
+  if (have_ptrace_hwdebug_interface ())
+    {
+      int i;
+      struct thread_points *t;
+      struct hw_break_tuple *hw_breaks;
+      /* The index (or slot) of the *point is passed in the si_errno field.  */
+      int slot = siginfo.si_errno;
+
+      t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0);
+
+      /* Find out if this *point is a hardware breakpoint.
+	 If so, we should return 0.  */
+      if (t)
+	{
+	  hw_breaks = t->hw_breaks;
+	  for (i = 0; i < max_slots_number; i++)
+	   if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
+	       && hw_breaks[i].hw_break->trigger_type
+		    == PPC_BREAKPOINT_TRIGGER_EXECUTE)
+	     return 0;
+	}
+    }
+
+  *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
   return 1;
 }
 
 static int
-ppc_linux_stopped_by_watchpoint (void)
+ppc_linux_stopped_by_watchpoint (struct target_ops *ops)
 {
   CORE_ADDR addr;
-  return ppc_linux_stopped_data_address (&current_target, &addr);
+  return ppc_linux_stopped_data_address (ops, &addr);
 }
 
 static int
@@ -1423,27 +2253,50 @@ ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
 {
   int mask;
 
-  if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
+  if (have_ptrace_hwdebug_interface ()
+      && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
+    return start <= addr && start + length >= addr;
+  else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
     mask = 3;
   else
     mask = 7;
 
   addr &= ~mask;
 
-  /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
+  /* Check whether [start, start+length-1] intersects [addr, addr+mask].  */
   return start <= addr + mask && start + length - 1 >= addr;
 }
 
+/* Return the number of registers needed for a masked hardware watchpoint.  */
+
+static int
+ppc_linux_masked_watch_num_registers (struct target_ops *target,
+				      CORE_ADDR addr, CORE_ADDR mask)
+{
+  if (!have_ptrace_hwdebug_interface ()
+	   || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0)
+    return -1;
+  else if ((mask & 0xC0000000) != 0xC0000000)
+    {
+      warning (_("The given mask covers kernel address space "
+		 "and cannot be used.\n"));
+
+      return -2;
+    }
+  else
+    return 2;
+}
+
 static void
 ppc_linux_store_inferior_registers (struct target_ops *ops,
 				    struct regcache *regcache, int regno)
 {
-  /* Overload thread id onto process id */
-  int tid = TIDGET (inferior_ptid);
+  /* Overload thread id onto process id.  */
+  int tid = ptid_get_lwp (inferior_ptid);
 
-  /* No thread id, just use process id */
+  /* No thread id, just use process id.  */
   if (tid == 0)
-    tid = PIDGET (inferior_ptid);
+    tid = ptid_get_pid (inferior_ptid);
 
   if (regno >= 0)
     store_register (regcache, tid, regno);
@@ -1453,7 +2306,7 @@ ppc_linux_store_inferior_registers (struct target_ops *ops,
 
 /* Functions for transferring registers between a gregset_t or fpregset_t
    (see sys/ucontext.h) and gdb's regcache.  The word size is that used
-   by the ptrace interface, not the current program's ABI.  eg. If a
+   by the ptrace interface, not the current program's ABI.  Eg. if a
    powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
    read or write 64-bit gregsets.  This is to suit the host libthread_db.  */
 
@@ -1505,13 +2358,13 @@ ppc_linux_target_wordsize (void)
 #ifdef __powerpc64__
   long msr;
 
-  int tid = TIDGET (inferior_ptid);
+  int tid = ptid_get_lwp (inferior_ptid);
   if (tid == 0)
-    tid = PIDGET (inferior_ptid);
+    tid = ptid_get_pid (inferior_ptid);
 
   errno = 0;
   msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
-  if (errno == 0 && msr < 0)
+  if (errno == 0 && ppc64_64bit_inferior_p (msr))
     wordsize = 8;
 #endif
 
@@ -1523,6 +2376,7 @@ ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
                       gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
 {
   int sizeof_auxv_field = ppc_linux_target_wordsize ();
+  enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
   gdb_byte *ptr = *readptr;
 
   if (endptr == ptr)
@@ -1531,9 +2385,9 @@ ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
   if (endptr - ptr < sizeof_auxv_field * 2)
     return -1;
 
-  *typep = extract_unsigned_integer (ptr, sizeof_auxv_field);
+  *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
   ptr += sizeof_auxv_field;
-  *valp = extract_unsigned_integer (ptr, sizeof_auxv_field);
+  *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
   ptr += sizeof_auxv_field;
 
   *readptr = ptr;
@@ -1546,10 +2400,11 @@ ppc_linux_read_description (struct target_ops *ops)
   int altivec = 0;
   int vsx = 0;
   int isa205 = 0;
+  int cell = 0;
 
-  int tid = TIDGET (inferior_ptid);
+  int tid = ptid_get_lwp (inferior_ptid);
   if (tid == 0)
-    tid = PIDGET (inferior_ptid);
+    tid = ptid_get_pid (inferior_ptid);
 
   if (have_ptrace_getsetevrregs)
     {
@@ -1564,7 +2419,8 @@ ppc_linux_read_description (struct target_ops *ops)
 	perror_with_name (_("Unable to fetch SPE registers"));
     }
 
-  if (have_ptrace_getsetvsxregs)
+  if (have_ptrace_getsetvsxregs
+      && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_VSX))
     {
       gdb_vsxregset_t vsxregset;
 
@@ -1577,7 +2433,8 @@ ppc_linux_read_description (struct target_ops *ops)
 	perror_with_name (_("Unable to fetch VSX registers"));
     }
 
-  if (have_ptrace_getvrregs)
+  if (have_ptrace_getvrregs
+      && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_ALTIVEC))
     {
       gdb_vrregset_t vrregset;
 
@@ -1591,7 +2448,7 @@ ppc_linux_read_description (struct target_ops *ops)
     }
 
   /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
-     the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
+     the FPSCR from 32 bits to 64 bits.  Even though Power 7 supports this
      ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
      PPC_FEATURE_ARCH_2_06.  Since for now the only bits used in the higher
      half of the register are for Decimal Floating Point, we check if that
@@ -1599,17 +2456,25 @@ ppc_linux_read_description (struct target_ops *ops)
   if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP)
     isa205 = 1;
 
+  if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL)
+    cell = 1;
+
   if (ppc_linux_target_wordsize () == 8)
     {
-      if (vsx)
+      if (cell)
+	return tdesc_powerpc_cell64l;
+      else if (vsx)
 	return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
       else if (altivec)
-	return isa205? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
+	return isa205
+	  ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
 
       return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
     }
 
-  if (vsx)
+  if (cell)
+    return tdesc_powerpc_cell32l;
+  else if (vsx)
     return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
   else if (altivec)
     return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
@@ -1631,18 +2496,28 @@ _initialize_ppc_linux_nat (void)
   t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
   t->to_store_registers = ppc_linux_store_inferior_registers;
 
-  /* Add our watchpoint methods.  */
-  t->to_can_use_hw_breakpoint = ppc_linux_check_watch_resources;
+  /* Add our breakpoint/watchpoint methods.  */
+  t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint;
+  t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint;
+  t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint;
   t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
   t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
   t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
+  t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint;
+  t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint;
   t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
   t->to_stopped_data_address = ppc_linux_stopped_data_address;
   t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
+  t->to_can_accel_watchpoint_condition
+    = ppc_linux_can_accel_watchpoint_condition;
+  t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers;
+  t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers;
 
   t->to_read_description = ppc_linux_read_description;
   t->to_auxv_parse = ppc_linux_auxv_parse;
 
+  observer_attach_thread_exit (ppc_linux_thread_exit);
+
   /* Register the target.  */
   linux_nat_add_target (t);
   linux_nat_set_new_thread (t, ppc_linux_new_thread);