X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fppc-linux-nat.c;h=c8c9376310c1f1d93870dec49418f61618efa592;hb=24b06219744627c597d799c1aafb2b2322ac3c3e;hp=460d48abf30bc3d63bd5a720f2534a82e0ce8282;hpb=383f0f5b9a5fa97db053fb6506e07f5e73eb4993;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c index 460d48abf3..c8c9376310 100644 --- a/gdb/ppc-linux-nat.c +++ b/gdb/ppc-linux-nat.c @@ -1,7 +1,7 @@ /* PPC GNU/Linux native support. - Copyright 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, - 2003 Free Software Foundation, Inc. + Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, + 2003, 2004, 2005 Free Software Foundation, Inc. This file is part of GDB. @@ -17,8 +17,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, - Boston, MA 02111-1307, USA. */ + Foundation, Inc., 51 Franklin Street, Fifth Floor, + Boston, MA 02110-1301, USA. */ #include "defs.h" #include "gdb_string.h" @@ -27,6 +27,8 @@ #include "gdbcore.h" #include "regcache.h" #include "gdb_assert.h" +#include "target.h" +#include "linux-nat.h" #include #include @@ -70,6 +72,16 @@ #define PTRACE_SETVRREGS 19 #endif + +/* Similarly for the ptrace requests for getting / setting the SPE + registers (ev0 -- ev31, acc, and spefscr). See the description of + gdb_evrregset_t for details. */ +#ifndef PTRACE_GETEVRREGS +#define PTRACE_GETEVRREGS 20 +#define PTRACE_SETEVRREGS 21 +#endif + + /* This oddity is because the Linux kernel defines elf_vrregset_t as an array of 33 16 bytes long elements. I.e. it leaves out vrsave. However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return @@ -101,9 +113,47 @@ typedef char gdb_vrregset_t[SIZEOF_VRREGS]; -/* For runtime check of ptrace support for VRREGS. */ + +/* On PPC processors that support the the Signal Processing Extension + (SPE) APU, the general-purpose registers are 64 bits long. + However, the ordinary Linux kernel PTRACE_PEEKUSR / PTRACE_POKEUSR + / PT_READ_U / PT_WRITE_U ptrace calls only access the lower half of + each register, to allow them to behave the same way they do on + non-SPE systems. There's a separate pair of calls, + PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that read and write the top + halves of all the general-purpose registers at once, along with + some SPE-specific registers. + + GDB itself continues to claim the general-purpose registers are 32 + bits long. It has unnamed raw registers that hold the upper halves + of the gprs, and the the full 64-bit SIMD views of the registers, + 'ev0' -- 'ev31', are pseudo-registers that splice the top and + bottom halves together. + + This is the structure filled in by PTRACE_GETEVRREGS and written to + the inferior's registers by PTRACE_SETEVRREGS. */ +struct gdb_evrregset_t +{ + unsigned long evr[32]; + unsigned long long acc; + unsigned long spefscr; +}; + + +/* Non-zero if our kernel may support the PTRACE_GETVRREGS and + PTRACE_SETVRREGS requests, for reading and writing the Altivec + registers. Zero if we've tried one of them and gotten an + error. */ int have_ptrace_getvrregs = 1; + +/* Non-zero if our kernel may support the PTRACE_GETEVRREGS and + PTRACE_SETEVRREGS requests, for reading and writing the SPE + registers. Zero if we've tried one of them and gotten an + error. */ +int have_ptrace_getsetevrregs = 1; + + int kernel_u_size (void) { @@ -164,8 +214,19 @@ ppc_register_u_addr (int regno) u_addr = PT_MSR * wordsize; if (tdep->ppc_fpscr_regnum >= 0 && regno == tdep->ppc_fpscr_regnum) - u_addr = PT_FPSCR * wordsize; - + { + /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the + kernel headers incorrectly contained the 32-bit definition of + PT_FPSCR. For the 32-bit definition, floating-point + registers occupy two 32-bit "slots", and the FPSCR lives in + the secondhalf of such a slot-pair (hence +1). For 64-bit, + the FPSCR instead occupies the full 64-bit 2-word-slot and + hence no adjustment is necessary. Hack around this. */ + if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) + u_addr = (48 + 32) * wordsize; + else + u_addr = PT_FPSCR * wordsize; + } return u_addr; } @@ -179,7 +240,7 @@ fetch_altivec_register (int tid, int regno) int offset = 0; gdb_vrregset_t regs; struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); - int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); + int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); if (ret < 0) @@ -189,7 +250,7 @@ fetch_altivec_register (int tid, int regno) have_ptrace_getvrregs = 0; return; } - perror_with_name ("Unable to fetch AltiVec register"); + perror_with_name (_("Unable to fetch AltiVec register")); } /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes @@ -197,10 +258,82 @@ fetch_altivec_register (int tid, int regno) vector. VRSAVE is at the end of the array in a 4 bytes slot, so there is no need to define an offset for it. */ if (regno == (tdep->ppc_vrsave_regnum - 1)) - offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); + offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); - supply_register (regno, - regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); + regcache_raw_supply (current_regcache, regno, + regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); +} + +/* Fetch the top 32 bits of TID's general-purpose registers and the + SPE-specific registers, and place the results in EVRREGSET. If we + don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with + zeros. + + All the logic to deal with whether or not the PTRACE_GETEVRREGS and + PTRACE_SETEVRREGS requests are supported is isolated here, and in + set_spe_registers. */ +static void +get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) +{ + if (have_ptrace_getsetevrregs) + { + if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) + return; + else + { + /* EIO means that the PTRACE_GETEVRREGS request isn't supported; + we just return zeros. */ + if (errno == EIO) + have_ptrace_getsetevrregs = 0; + else + /* Anything else needs to be reported. */ + perror_with_name (_("Unable to fetch SPE registers")); + } + } + + memset (evrregset, 0, sizeof (*evrregset)); +} + +/* Supply values from TID for SPE-specific raw registers: the upper + halves of the GPRs, the accumulator, and the spefscr. REGNO must + be the number of an upper half register, acc, spefscr, or -1 to + supply the values of all registers. */ +static void +fetch_spe_register (int tid, int regno) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); + struct gdb_evrregset_t evrregs; + + gdb_assert (sizeof (evrregs.evr[0]) + == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum)); + gdb_assert (sizeof (evrregs.acc) + == register_size (current_gdbarch, tdep->ppc_acc_regnum)); + gdb_assert (sizeof (evrregs.spefscr) + == register_size (current_gdbarch, tdep->ppc_spefscr_regnum)); + + get_spe_registers (tid, &evrregs); + + if (regno == -1) + { + int i; + + for (i = 0; i < ppc_num_gprs; i++) + regcache_raw_supply (current_regcache, tdep->ppc_ev0_upper_regnum + i, + &evrregs.evr[i]); + } + else if (tdep->ppc_ev0_upper_regnum <= regno + && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) + regcache_raw_supply (current_regcache, regno, + &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); + + if (regno == -1 + || regno == tdep->ppc_acc_regnum) + regcache_raw_supply (current_regcache, tdep->ppc_acc_regnum, &evrregs.acc); + + if (regno == -1 + || regno == tdep->ppc_spefscr_regnum) + regcache_raw_supply (current_regcache, tdep->ppc_spefscr_regnum, + &evrregs.spefscr); } static void @@ -208,11 +341,10 @@ fetch_register (int tid, int regno) { struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); /* This isn't really an address. But ptrace thinks of it as one. */ - char mess[128]; /* For messages */ - int i; + CORE_ADDR regaddr = ppc_register_u_addr (regno); + int bytes_transferred; unsigned int offset; /* Offset of registers within the u area. */ char buf[MAX_REGISTER_SIZE]; - CORE_ADDR regaddr = ppc_register_u_addr (regno); if (altivec_register_p (regno)) { @@ -229,49 +361,60 @@ fetch_register (int tid, int regno) AltiVec registers, fall through and return zeroes, because regaddr will be -1 in this case. */ } + else if (spe_register_p (regno)) + { + fetch_spe_register (tid, regno); + return; + } if (regaddr == -1) { - memset (buf, '\0', DEPRECATED_REGISTER_RAW_SIZE (regno)); /* Supply zeroes */ - supply_register (regno, buf); + memset (buf, '\0', register_size (current_gdbarch, regno)); /* Supply zeroes */ + regcache_raw_supply (current_regcache, regno, buf); return; } - /* If the current architecture has no floating-point registers, we - should never reach this point: ppc_register_u_addr should have - returned -1, and we should have caught that above. */ - gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); - /* Read the raw register using PTRACE_XFER_TYPE sized chunks. On a 32-bit platform, 64-bit floating-point registers will require two transfers. */ - for (i = 0; i < DEPRECATED_REGISTER_RAW_SIZE (regno); i += sizeof (PTRACE_XFER_TYPE)) + for (bytes_transferred = 0; + bytes_transferred < register_size (current_gdbarch, regno); + bytes_transferred += sizeof (PTRACE_XFER_TYPE)) { errno = 0; - *(PTRACE_XFER_TYPE *) & buf[i] = ptrace (PT_READ_U, tid, - (PTRACE_ARG3_TYPE) regaddr, 0); + *(PTRACE_XFER_TYPE *) & buf[bytes_transferred] + = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) regaddr, 0); regaddr += sizeof (PTRACE_XFER_TYPE); if (errno != 0) { - sprintf (mess, "reading register %s (#%d)", + char message[128]; + sprintf (message, "reading register %s (#%d)", REGISTER_NAME (regno), regno); - perror_with_name (mess); + perror_with_name (message); } } - /* Now supply the register. Be careful to map between ptrace's and - the current_regcache's idea of the current wordsize. */ - if ((regno >= tdep->ppc_fp0_regnum - && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) - || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) - /* FPs are always 64 bits. Little endian values are always found - at the left-hand end of the register. */ - regcache_raw_supply (current_regcache, regno, buf); - else - /* Big endian register, need to fetch the right-hand end. */ - regcache_raw_supply (current_regcache, regno, - (buf + sizeof (PTRACE_XFER_TYPE) - - register_size (current_gdbarch, regno))); + /* Now supply the register. Keep in mind that the regcache's idea + of the register's size may not be a multiple of sizeof + (PTRACE_XFER_TYPE). */ + if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) + { + /* Little-endian values are always found at the left end of the + bytes transferred. */ + regcache_raw_supply (current_regcache, regno, buf); + } + else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) + { + /* Big-endian values are found at the right end of the bytes + transferred. */ + size_t padding = (bytes_transferred + - register_size (current_gdbarch, regno)); + regcache_raw_supply (current_regcache, regno, buf + padding); + } + else + internal_error (__FILE__, __LINE__, + _("fetch_register: unexpected byte order: %d"), + gdbarch_byte_order (current_gdbarch)); } static void @@ -280,8 +423,8 @@ supply_vrregset (gdb_vrregset_t *vrregsetp) int i; struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; - int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); - int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); + int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); + int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); for (i = 0; i < num_of_vrregs; i++) { @@ -290,10 +433,11 @@ supply_vrregset (gdb_vrregset_t *vrregsetp) occupies a whole vector, while VRSAVE occupies a full 4 bytes slot. */ if (i == (num_of_vrregs - 2)) - supply_register (tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize + offset); + regcache_raw_supply (current_regcache, tdep->ppc_vr0_regnum + i, + *vrregsetp + i * vrregsize + offset); else - supply_register (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize); + regcache_raw_supply (current_regcache, tdep->ppc_vr0_regnum + i, + *vrregsetp + i * vrregsize); } } @@ -311,7 +455,7 @@ fetch_altivec_registers (int tid) have_ptrace_getvrregs = 0; return; } - perror_with_name ("Unable to fetch AltiVec registers"); + perror_with_name (_("Unable to fetch AltiVec registers")); } supply_vrregset (®s); } @@ -345,13 +489,15 @@ fetch_ppc_registers (int tid) if (have_ptrace_getvrregs) if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) fetch_altivec_registers (tid); + if (tdep->ppc_ev0_upper_regnum >= 0) + fetch_spe_register (tid, -1); } /* Fetch registers from the child process. Fetch all registers if regno == -1, otherwise fetch all general registers or all floating point registers depending upon the value of regno. */ -void -fetch_inferior_registers (int regno) +static void +ppc_linux_fetch_inferior_registers (int regno) { /* Overload thread id onto process id */ int tid = TIDGET (inferior_ptid); @@ -374,7 +520,7 @@ store_altivec_register (int tid, int regno) int offset = 0; gdb_vrregset_t regs; struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); - int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); + int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); if (ret < 0) @@ -384,20 +530,106 @@ store_altivec_register (int tid, int regno) have_ptrace_getvrregs = 0; return; } - perror_with_name ("Unable to fetch AltiVec register"); + perror_with_name (_("Unable to fetch AltiVec register")); } /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes long on the hardware. */ if (regno == (tdep->ppc_vrsave_regnum - 1)) - offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); + offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); - regcache_collect (regno, - regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); + regcache_raw_collect (current_regcache, regno, + regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset); ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); if (ret < 0) - perror_with_name ("Unable to store AltiVec register"); + perror_with_name (_("Unable to store AltiVec register")); +} + +/* Assuming TID referrs to an SPE process, set the top halves of TID's + general-purpose registers and its SPE-specific registers to the + values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do + nothing. + + All the logic to deal with whether or not the PTRACE_GETEVRREGS and + PTRACE_SETEVRREGS requests are supported is isolated here, and in + get_spe_registers. */ +static void +set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) +{ + if (have_ptrace_getsetevrregs) + { + if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) + return; + else + { + /* EIO means that the PTRACE_SETEVRREGS request isn't + supported; we fail silently, and don't try the call + again. */ + if (errno == EIO) + have_ptrace_getsetevrregs = 0; + else + /* Anything else needs to be reported. */ + perror_with_name (_("Unable to set SPE registers")); + } + } +} + +/* Write GDB's value for the SPE-specific raw register REGNO to TID. + If REGNO is -1, write the values of all the SPE-specific + registers. */ +static void +store_spe_register (int tid, int regno) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); + struct gdb_evrregset_t evrregs; + + gdb_assert (sizeof (evrregs.evr[0]) + == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum)); + gdb_assert (sizeof (evrregs.acc) + == register_size (current_gdbarch, tdep->ppc_acc_regnum)); + gdb_assert (sizeof (evrregs.spefscr) + == register_size (current_gdbarch, tdep->ppc_spefscr_regnum)); + + if (regno == -1) + /* Since we're going to write out every register, the code below + should store to every field of evrregs; if that doesn't happen, + make it obvious by initializing it with suspicious values. */ + memset (&evrregs, 42, sizeof (evrregs)); + else + /* We can only read and write the entire EVR register set at a + time, so to write just a single register, we do a + read-modify-write maneuver. */ + get_spe_registers (tid, &evrregs); + + if (regno == -1) + { + int i; + + for (i = 0; i < ppc_num_gprs; i++) + regcache_raw_collect (current_regcache, + tdep->ppc_ev0_upper_regnum + i, + &evrregs.evr[i]); + } + else if (tdep->ppc_ev0_upper_regnum <= regno + && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) + regcache_raw_collect (current_regcache, regno, + &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); + + if (regno == -1 + || regno == tdep->ppc_acc_regnum) + regcache_raw_collect (current_regcache, + tdep->ppc_acc_regnum, + &evrregs.acc); + + if (regno == -1 + || regno == tdep->ppc_spefscr_regnum) + regcache_raw_collect (current_regcache, + tdep->ppc_spefscr_regnum, + &evrregs.spefscr); + + /* Write back the modified register set. */ + set_spe_registers (tid, &evrregs); } static void @@ -406,9 +638,8 @@ store_register (int tid, int regno) struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); /* This isn't really an address. But ptrace thinks of it as one. */ CORE_ADDR regaddr = ppc_register_u_addr (regno); - char mess[128]; /* For messages */ int i; - unsigned int offset; /* Offset of registers within the u area. */ + size_t bytes_to_transfer; char buf[MAX_REGISTER_SIZE]; if (altivec_register_p (regno)) @@ -416,32 +647,35 @@ store_register (int tid, int regno) store_altivec_register (tid, regno); return; } + else if (spe_register_p (regno)) + { + store_spe_register (tid, regno); + return; + } if (regaddr == -1) return; - /* If the current architecture has no floating-point registers, we - should never reach this point: ppc_register_u_addr should have - returned -1, and we should have caught that above. */ - gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); - - /* First collect the register value from the regcache. Be careful - to to convert the regcache's wordsize into ptrace's wordsize. */ + /* First collect the register. Keep in mind that the regcache's + idea of the register's size may not be a multiple of sizeof + (PTRACE_XFER_TYPE). */ memset (buf, 0, sizeof buf); - if ((regno >= tdep->ppc_fp0_regnum - && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) - || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) - /* Floats are always 64-bit. Little endian registers are always - at the left-hand end of the register cache. */ - regcache_raw_collect (current_regcache, regno, buf); - else - /* Big-endian registers belong at the right-hand end of the - buffer. */ - regcache_raw_collect (current_regcache, regno, - (buf + sizeof (PTRACE_XFER_TYPE) - - register_size (current_gdbarch, regno))); + bytes_to_transfer = align_up (register_size (current_gdbarch, regno), + sizeof (PTRACE_XFER_TYPE)); + if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) + { + /* Little-endian values always sit at the left end of the buffer. */ + regcache_raw_collect (current_regcache, regno, buf); + } + else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + /* Big-endian values sit at the right end of the buffer. */ + size_t padding = (bytes_to_transfer + - register_size (current_gdbarch, regno)); + regcache_raw_collect (current_regcache, regno, buf + padding); + } - for (i = 0; i < DEPRECATED_REGISTER_RAW_SIZE (regno); i += sizeof (PTRACE_XFER_TYPE)) + for (i = 0; i < bytes_to_transfer; i += sizeof (PTRACE_XFER_TYPE)) { errno = 0; ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) regaddr, @@ -457,9 +691,10 @@ store_register (int tid, int regno) if (errno != 0) { - sprintf (mess, "writing register %s (#%d)", + char message[128]; + sprintf (message, "writing register %s (#%d)", REGISTER_NAME (regno), regno); - perror_with_name (mess); + perror_with_name (message); } } } @@ -470,18 +705,19 @@ fill_vrregset (gdb_vrregset_t *vrregsetp) int i; struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; - int vrregsize = DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); - int offset = vrregsize - DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vrsave_regnum); + int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum); + int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum); for (i = 0; i < num_of_vrregs; i++) { /* The last 2 registers of this set are only 32 bit long, not 128, but only VSCR is fetched as a 16 bytes quantity. */ if (i == (num_of_vrregs - 2)) - regcache_collect (tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize + offset); + regcache_raw_collect (current_regcache, tdep->ppc_vr0_regnum + i, + *vrregsetp + i * vrregsize + offset); else - regcache_collect (tdep->ppc_vr0_regnum + i, *vrregsetp + i * vrregsize); + regcache_raw_collect (current_regcache, tdep->ppc_vr0_regnum + i, + *vrregsetp + i * vrregsize); } } @@ -499,13 +735,13 @@ store_altivec_registers (int tid) have_ptrace_getvrregs = 0; return; } - perror_with_name ("Couldn't get AltiVec registers"); + perror_with_name (_("Couldn't get AltiVec registers")); } fill_vrregset (®s); if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) - perror_with_name ("Couldn't write AltiVec registers"); + perror_with_name (_("Couldn't write AltiVec registers")); } static void @@ -537,10 +773,12 @@ store_ppc_registers (int tid) if (have_ptrace_getvrregs) if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) store_altivec_registers (tid); + if (tdep->ppc_ev0_upper_regnum >= 0) + store_spe_register (tid, -1); } -void -store_inferior_registers (int regno) +static void +ppc_linux_store_inferior_registers (int regno) { /* Overload thread id onto process id */ int tid = TIDGET (inferior_ptid); @@ -590,10 +828,10 @@ fill_gregset (gdb_gregset_t *gregsetp, int regno) /* Start with zeros. */ memset (regp, 0, elf_ngreg * sizeof (*regp)); - for (regi = 0; regi < 32; regi++) + for (regi = 0; regi < ppc_num_gprs; regi++) { - if ((regno == -1) || regno == regi) - right_fill_reg (regi, (regp + PT_R0 + regi)); + if ((regno == -1) || regno == tdep->ppc_gp0_regnum + regi) + right_fill_reg (tdep->ppc_gp0_regnum + regi, (regp + PT_R0 + regi)); } if ((regno == -1) || regno == PC_REGNUM) @@ -601,9 +839,11 @@ fill_gregset (gdb_gregset_t *gregsetp, int regno) if ((regno == -1) || regno == tdep->ppc_lr_regnum) right_fill_reg (tdep->ppc_lr_regnum, regp + PT_LNK); if ((regno == -1) || regno == tdep->ppc_cr_regnum) - regcache_collect (tdep->ppc_cr_regnum, regp + PT_CCR); + regcache_raw_collect (current_regcache, tdep->ppc_cr_regnum, + regp + PT_CCR); if ((regno == -1) || regno == tdep->ppc_xer_regnum) - regcache_collect (tdep->ppc_xer_regnum, regp + PT_XER); + regcache_raw_collect (current_regcache, tdep->ppc_xer_regnum, + regp + PT_XER); if ((regno == -1) || regno == tdep->ppc_ctr_regnum) right_fill_reg (tdep->ppc_ctr_regnum, regp + PT_CTR); #ifdef PT_MQ @@ -638,9 +878,28 @@ fill_fpregset (gdb_fpregset_t *fpregsetp, int regno) for (regi = 0; regi < ppc_num_fprs; regi++) { if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi)) - regcache_collect (tdep->ppc_fp0_regnum + regi, fpp + 8 * regi); + regcache_raw_collect (current_regcache, tdep->ppc_fp0_regnum + regi, + fpp + 8 * regi); } if (regno == -1 || regno == tdep->ppc_fpscr_regnum) right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32)); } } + +void _initialize_ppc_linux_nat (void); + +void +_initialize_ppc_linux_nat (void) +{ + struct target_ops *t; + + /* Fill in the generic GNU/Linux methods. */ + t = linux_target (); + + /* Add our register access methods. */ + t->to_fetch_registers = ppc_linux_fetch_inferior_registers; + t->to_store_registers = ppc_linux_store_inferior_registers; + + /* Register the target. */ + add_target (t); +}