X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fppc-linux-nat.c;h=d619971a001d225ea278c776e09fb5297074c6a7;hb=456e800a63def18484f69a51f59c2338a5cc4568;hp=c9f0f9d48da733a004bf7b5d2543b53fe58747c6;hpb=f6ac5f3d63e03a81c4ff3749aba234961cc9090e;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c index c9f0f9d48d..d619971a00 100644 --- a/gdb/ppc-linux-nat.c +++ b/gdb/ppc-linux-nat.c @@ -1,6 +1,6 @@ /* PPC GNU/Linux native support. - Copyright (C) 1988-2018 Free Software Foundation, Inc. + Copyright (C) 1988-2020 Free Software Foundation, Inc. This file is part of GDB. @@ -24,16 +24,19 @@ #include "gdbthread.h" #include "gdbcore.h" #include "regcache.h" +#include "regset.h" #include "target.h" #include "linux-nat.h" #include #include #include #include -#include "gdb_wait.h" +#include +#include "gdbsupport/gdb_wait.h" #include #include #include "nat/gdb_ptrace.h" +#include "nat/linux-ptrace.h" #include "inf-ptrace.h" /* Prototypes for supply_gregset etc. */ @@ -45,7 +48,10 @@ #include "elf/common.h" #include "auxv.h" +#include "arch/ppc-linux-common.h" +#include "arch/ppc-linux-tdesc.h" #include "nat/ppc-linux.h" +#include "linux-tdep.h" /* Similarly for the hardware watchpoint support. These requests are used when the PowerPC HWDEBUG ptrace interface is not available. */ @@ -158,23 +164,22 @@ struct ppc_hw_breakpoint Even though this vrsave register is not included in the regset typedef, it is handled by the ptrace requests. - Note that GNU/Linux doesn't support little endian PPC hardware, - therefore the offset at which the real value of the VSCR register - is located will be always 12 bytes. - The layout is like this (where x is the actual value of the vscr reg): */ /* *INDENT-OFF* */ /* +Big-Endian: |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| <-------> <-------><-------><-> VR0 VR31 VSCR VRSAVE +Little-Endian: + |.|.|.|.|.....|.|.|.|.||X|.|.|.||.| + <-------> <-------><-------><-> + VR0 VR31 VSCR VRSAVE */ /* *INDENT-ON* */ -#define SIZEOF_VRREGS 33*16+4 - -typedef char gdb_vrregset_t[SIZEOF_VRREGS]; +typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET]; /* This is the layout of the POWER7 VSX registers and the way they overlap with the existing FPR and VMX registers. @@ -208,9 +213,7 @@ typedef char gdb_vrregset_t[SIZEOF_VRREGS]; the FP registers (doubleword 0) and hence extend them with additional 64 bits (doubleword 1). The other 32 regs overlap with the VMX registers. */ -#define SIZEOF_VSXREGS 32*8 - -typedef char gdb_vsxregset_t[SIZEOF_VSXREGS]; +typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET]; /* On PPC processors that support the Signal Processing Extension (SPE) APU, the general-purpose registers are 64 bits long. @@ -296,13 +299,13 @@ struct ppc_linux_nat_target final : public linux_nat_target int remove_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) override; - int stopped_by_watchpoint () override; + bool stopped_by_watchpoint () override; - int stopped_data_address (CORE_ADDR *) override; + bool stopped_data_address (CORE_ADDR *) override; - int watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; + bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; - int can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *) + bool can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *) override; int masked_watch_num_registers (CORE_ADDR, CORE_ADDR) override; @@ -314,6 +317,9 @@ struct ppc_linux_nat_target final : public linux_nat_target int auxv_parse (gdb_byte **readptr, gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) override; + + /* Override linux_nat_target low methods. */ + void low_new_thread (struct lwp_info *lp) override; }; static ppc_linux_nat_target the_ppc_linux_nat_target; @@ -406,13 +412,11 @@ ppc_register_u_addr (struct gdbarch *gdbarch, int regno) registers set mechanism, as opposed to the interface for all the other registers, that stores/fetches each register individually. */ static void -fetch_vsx_register (struct regcache *regcache, int tid, int regno) +fetch_vsx_registers (struct regcache *regcache, int tid, int regno) { int ret; gdb_vsxregset_t regs; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + const struct regset *vsxregset = ppc_linux_vsxregset (); ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); if (ret < 0) @@ -422,26 +426,24 @@ fetch_vsx_register (struct regcache *regcache, int tid, int regno) have_ptrace_getsetvsxregs = 0; return; } - perror_with_name (_("Unable to fetch VSX register")); + perror_with_name (_("Unable to fetch VSX registers")); } - regcache_raw_supply (regcache, regno, - regs + (regno - tdep->ppc_vsr0_upper_regnum) - * vsxregsize); + vsxregset->supply_regset (vsxregset, regcache, regno, ®s, + PPC_LINUX_SIZEOF_VSXREGSET); } /* The Linux kernel ptrace interface for AltiVec registers uses the registers set mechanism, as opposed to the interface for all the other registers, that stores/fetches each register individually. */ static void -fetch_altivec_register (struct regcache *regcache, int tid, int regno) +fetch_altivec_registers (struct regcache *regcache, int tid, + int regno) { int ret; - int offset = 0; gdb_vrregset_t regs; struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); + const struct regset *vrregset = ppc_linux_vrregset (gdbarch); ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); if (ret < 0) @@ -451,19 +453,11 @@ fetch_altivec_register (struct regcache *regcache, int tid, int regno) have_ptrace_getvrregs = 0; return; } - perror_with_name (_("Unable to fetch AltiVec register")); + perror_with_name (_("Unable to fetch AltiVec registers")); } - - /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes - long on the hardware. We deal only with the lower 4 bytes of the - vector. VRSAVE is at the end of the array in a 4 bytes slot, so - there is no need to define an offset for it. */ - if (regno == (tdep->ppc_vrsave_regnum - 1)) - offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); - - regcache_raw_supply (regcache, regno, - regs + (regno - - tdep->ppc_vr0_regnum) * vrregsize + offset); + + vrregset->supply_regset (vrregset, regcache, regno, ®s, + PPC_LINUX_SIZEOF_VRREGSET); } /* Fetch the top 32 bits of TID's general-purpose registers and the @@ -521,22 +515,92 @@ fetch_spe_register (struct regcache *regcache, int tid, int regno) int i; for (i = 0; i < ppc_num_gprs; i++) - regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i, - &evrregs.evr[i]); + regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]); } else if (tdep->ppc_ev0_upper_regnum <= regno && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) - regcache_raw_supply (regcache, regno, - &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); + regcache->raw_supply (regno, + &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); if (regno == -1 || regno == tdep->ppc_acc_regnum) - regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc); + regcache->raw_supply (tdep->ppc_acc_regnum, &evrregs.acc); if (regno == -1 || regno == tdep->ppc_spefscr_regnum) - regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum, - &evrregs.spefscr); + regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr); +} + +/* Use ptrace to fetch all registers from the register set with note + type REGSET_ID, size REGSIZE, and layout described by REGSET, from + process/thread TID and supply their values to REGCACHE. If ptrace + returns ENODATA to indicate the regset is unavailable, mark the + registers as unavailable in REGCACHE. */ + +static void +fetch_regset (struct regcache *regcache, int tid, + int regset_id, int regsetsize, const struct regset *regset) +{ + void *buf = alloca (regsetsize); + struct iovec iov; + + iov.iov_base = buf; + iov.iov_len = regsetsize; + + if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) + { + if (errno == ENODATA) + regset->supply_regset (regset, regcache, -1, NULL, regsetsize); + else + perror_with_name (_("Couldn't get register set")); + } + else + regset->supply_regset (regset, regcache, -1, buf, regsetsize); +} + +/* Use ptrace to store register REGNUM of the regset with note type + REGSET_ID, size REGSETSIZE, and layout described by REGSET, from + REGCACHE back to process/thread TID. If REGNUM is -1 all registers + in the set are collected and stored. */ + +static void +store_regset (const struct regcache *regcache, int tid, int regnum, + int regset_id, int regsetsize, const struct regset *regset) +{ + void *buf = alloca (regsetsize); + struct iovec iov; + + iov.iov_base = buf; + iov.iov_len = regsetsize; + + /* Make sure that the buffer that will be stored has up to date values + for the registers that won't be collected. */ + if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) + perror_with_name (_("Couldn't get register set")); + + regset->collect_regset (regset, regcache, regnum, buf, regsetsize); + + if (ptrace (PTRACE_SETREGSET, tid, regset_id, &iov) < 0) + perror_with_name (_("Couldn't set register set")); +} + +/* Check whether the kernel provides a register set with number + REGSET_ID of size REGSETSIZE for process/thread TID. */ + +static bool +check_regset (int tid, int regset_id, int regsetsize) +{ + void *buf = alloca (regsetsize); + struct iovec iov; + + iov.iov_base = buf; + iov.iov_len = regsetsize; + + if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0 + || errno == ENODATA) + return true; + else + return false; } static void @@ -547,29 +611,28 @@ fetch_register (struct regcache *regcache, int tid, int regno) /* This isn't really an address. But ptrace thinks of it as one. */ CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); int bytes_transferred; - unsigned int offset; /* Offset of registers within the u area. */ gdb_byte buf[PPC_MAX_REGISTER_SIZE]; if (altivec_register_p (gdbarch, regno)) { /* If this is the first time through, or if it is not the first - time through, and we have comfirmed that there is kernel + time through, and we have confirmed that there is kernel support for such a ptrace request, then go and fetch the register. */ if (have_ptrace_getvrregs) { - fetch_altivec_register (regcache, tid, regno); + fetch_altivec_registers (regcache, tid, regno); return; } /* If we have discovered that there is no ptrace support for AltiVec registers, fall through and return zeroes, because regaddr will be -1 in this case. */ } - if (vsx_register_p (gdbarch, regno)) + else if (vsx_register_p (gdbarch, regno)) { if (have_ptrace_getsetvsxregs) { - fetch_vsx_register (regcache, tid, regno); + fetch_vsx_registers (regcache, tid, regno); return; } } @@ -578,11 +641,132 @@ fetch_register (struct regcache *regcache, int tid, int regno) fetch_spe_register (regcache, tid, regno); return; } + else if (regno == PPC_DSCR_REGNUM) + { + gdb_assert (tdep->ppc_dscr_regnum != -1); + + fetch_regset (regcache, tid, NT_PPC_DSCR, + PPC_LINUX_SIZEOF_DSCRREGSET, + &ppc32_linux_dscrregset); + return; + } + else if (regno == PPC_PPR_REGNUM) + { + gdb_assert (tdep->ppc_ppr_regnum != -1); + + fetch_regset (regcache, tid, NT_PPC_PPR, + PPC_LINUX_SIZEOF_PPRREGSET, + &ppc32_linux_pprregset); + return; + } + else if (regno == PPC_TAR_REGNUM) + { + gdb_assert (tdep->ppc_tar_regnum != -1); + + fetch_regset (regcache, tid, NT_PPC_TAR, + PPC_LINUX_SIZEOF_TARREGSET, + &ppc32_linux_tarregset); + return; + } + else if (PPC_IS_EBB_REGNUM (regno)) + { + gdb_assert (tdep->have_ebb); + + fetch_regset (regcache, tid, NT_PPC_EBB, + PPC_LINUX_SIZEOF_EBBREGSET, + &ppc32_linux_ebbregset); + return; + } + else if (PPC_IS_PMU_REGNUM (regno)) + { + gdb_assert (tdep->ppc_mmcr0_regnum != -1); + + fetch_regset (regcache, tid, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset); + return; + } + else if (PPC_IS_TMSPR_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_spr); + + fetch_regset (regcache, tid, NT_PPC_TM_SPR, + PPC_LINUX_SIZEOF_TM_SPRREGSET, + &ppc32_linux_tm_sprregset); + return; + } + else if (PPC_IS_CKPTGP_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_core); + + const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); + fetch_regset (regcache, tid, NT_PPC_TM_CGPR, + (tdep->wordsize == 4? + PPC32_LINUX_SIZEOF_CGPRREGSET + : PPC64_LINUX_SIZEOF_CGPRREGSET), + cgprregset); + return; + } + else if (PPC_IS_CKPTFP_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_fpu); + + fetch_regset (regcache, tid, NT_PPC_TM_CFPR, + PPC_LINUX_SIZEOF_CFPRREGSET, + &ppc32_linux_cfprregset); + return; + } + else if (PPC_IS_CKPTVMX_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_altivec); + + const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); + fetch_regset (regcache, tid, NT_PPC_TM_CVMX, + PPC_LINUX_SIZEOF_CVMXREGSET, + cvmxregset); + return; + } + else if (PPC_IS_CKPTVSX_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_vsx); + + fetch_regset (regcache, tid, NT_PPC_TM_CVSX, + PPC_LINUX_SIZEOF_CVSXREGSET, + &ppc32_linux_cvsxregset); + return; + } + else if (regno == PPC_CPPR_REGNUM) + { + gdb_assert (tdep->ppc_cppr_regnum != -1); + + fetch_regset (regcache, tid, NT_PPC_TM_CPPR, + PPC_LINUX_SIZEOF_CPPRREGSET, + &ppc32_linux_cpprregset); + return; + } + else if (regno == PPC_CDSCR_REGNUM) + { + gdb_assert (tdep->ppc_cdscr_regnum != -1); + + fetch_regset (regcache, tid, NT_PPC_TM_CDSCR, + PPC_LINUX_SIZEOF_CDSCRREGSET, + &ppc32_linux_cdscrregset); + return; + } + else if (regno == PPC_CTAR_REGNUM) + { + gdb_assert (tdep->ppc_ctar_regnum != -1); + + fetch_regset (regcache, tid, NT_PPC_TM_CTAR, + PPC_LINUX_SIZEOF_CTARREGSET, + &ppc32_linux_ctarregset); + return; + } if (regaddr == -1) { memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ - regcache_raw_supply (regcache, regno, buf); + regcache->raw_supply (regno, buf); return; } @@ -615,14 +799,14 @@ fetch_register (struct regcache *regcache, int tid, int regno) { /* Little-endian values are always found at the left end of the bytes transferred. */ - regcache_raw_supply (regcache, regno, buf); + regcache->raw_supply (regno, buf); } else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) { /* Big-endian values are found at the right end of the bytes transferred. */ size_t padding = (bytes_transferred - register_size (gdbarch, regno)); - regcache_raw_supply (regcache, regno, buf + padding); + regcache->raw_supply (regno, buf + padding); } else internal_error (__FILE__, __LINE__, @@ -630,84 +814,6 @@ fetch_register (struct regcache *regcache, int tid, int regno) gdbarch_byte_order (gdbarch)); } -static void -supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) -{ - int i; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); - - for (i = 0; i < ppc_num_vshrs; i++) - { - regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i, - *vsxregsetp + i * vsxregsize); - } -} - -static void -supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp) -{ - int i; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; - int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); - int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); - - for (i = 0; i < num_of_vrregs; i++) - { - /* The last 2 registers of this set are only 32 bit long, not - 128. However an offset is necessary only for VSCR because it - occupies a whole vector, while VRSAVE occupies a full 4 bytes - slot. */ - if (i == (num_of_vrregs - 2)) - regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize + offset); - else - regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize); - } -} - -static void -fetch_vsx_registers (struct regcache *regcache, int tid) -{ - int ret; - gdb_vsxregset_t regs; - - ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); - if (ret < 0) - { - if (errno == EIO) - { - have_ptrace_getsetvsxregs = 0; - return; - } - perror_with_name (_("Unable to fetch VSX registers")); - } - supply_vsxregset (regcache, ®s); -} - -static void -fetch_altivec_registers (struct regcache *regcache, int tid) -{ - int ret; - gdb_vrregset_t regs; - - ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); - if (ret < 0) - { - if (errno == EIO) - { - have_ptrace_getvrregs = 0; - return; - } - perror_with_name (_("Unable to fetch AltiVec registers")); - } - supply_vrregset (regcache, ®s); -} - /* This function actually issues the request to ptrace, telling it to get all general-purpose registers and put them into the specified regset. @@ -719,8 +825,6 @@ fetch_altivec_registers (struct regcache *regcache, int tid) static int fetch_all_gp_regs (struct regcache *regcache, int tid) { - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); gdb_gregset_t gregset; if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) @@ -817,7 +921,6 @@ fetch_fp_regs (struct regcache *regcache, int tid) static void fetch_ppc_registers (struct regcache *regcache, int tid) { - int i; struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -846,12 +949,72 @@ fetch_ppc_registers (struct regcache *regcache, int tid) fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); if (have_ptrace_getvrregs) if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) - fetch_altivec_registers (regcache, tid); + fetch_altivec_registers (regcache, tid, -1); if (have_ptrace_getsetvsxregs) if (tdep->ppc_vsr0_upper_regnum != -1) - fetch_vsx_registers (regcache, tid); + fetch_vsx_registers (regcache, tid, -1); if (tdep->ppc_ev0_upper_regnum >= 0) fetch_spe_register (regcache, tid, -1); + if (tdep->ppc_ppr_regnum != -1) + fetch_regset (regcache, tid, NT_PPC_PPR, + PPC_LINUX_SIZEOF_PPRREGSET, + &ppc32_linux_pprregset); + if (tdep->ppc_dscr_regnum != -1) + fetch_regset (regcache, tid, NT_PPC_DSCR, + PPC_LINUX_SIZEOF_DSCRREGSET, + &ppc32_linux_dscrregset); + if (tdep->ppc_tar_regnum != -1) + fetch_regset (regcache, tid, NT_PPC_TAR, + PPC_LINUX_SIZEOF_TARREGSET, + &ppc32_linux_tarregset); + if (tdep->have_ebb) + fetch_regset (regcache, tid, NT_PPC_EBB, + PPC_LINUX_SIZEOF_EBBREGSET, + &ppc32_linux_ebbregset); + if (tdep->ppc_mmcr0_regnum != -1) + fetch_regset (regcache, tid, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset); + if (tdep->have_htm_spr) + fetch_regset (regcache, tid, NT_PPC_TM_SPR, + PPC_LINUX_SIZEOF_TM_SPRREGSET, + &ppc32_linux_tm_sprregset); + if (tdep->have_htm_core) + { + const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); + fetch_regset (regcache, tid, NT_PPC_TM_CGPR, + (tdep->wordsize == 4? + PPC32_LINUX_SIZEOF_CGPRREGSET + : PPC64_LINUX_SIZEOF_CGPRREGSET), + cgprregset); + } + if (tdep->have_htm_fpu) + fetch_regset (regcache, tid, NT_PPC_TM_CFPR, + PPC_LINUX_SIZEOF_CFPRREGSET, + &ppc32_linux_cfprregset); + if (tdep->have_htm_altivec) + { + const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); + fetch_regset (regcache, tid, NT_PPC_TM_CVMX, + PPC_LINUX_SIZEOF_CVMXREGSET, + cvmxregset); + } + if (tdep->have_htm_vsx) + fetch_regset (regcache, tid, NT_PPC_TM_CVSX, + PPC_LINUX_SIZEOF_CVSXREGSET, + &ppc32_linux_cvsxregset); + if (tdep->ppc_cppr_regnum != -1) + fetch_regset (regcache, tid, NT_PPC_TM_CPPR, + PPC_LINUX_SIZEOF_CPPRREGSET, + &ppc32_linux_cpprregset); + if (tdep->ppc_cdscr_regnum != -1) + fetch_regset (regcache, tid, NT_PPC_TM_CDSCR, + PPC_LINUX_SIZEOF_CDSCRREGSET, + &ppc32_linux_cdscrregset); + if (tdep->ppc_ctar_regnum != -1) + fetch_regset (regcache, tid, NT_PPC_TM_CTAR, + PPC_LINUX_SIZEOF_CTARREGSET, + &ppc32_linux_ctarregset); } /* Fetch registers from the child process. Fetch all registers if @@ -860,7 +1023,7 @@ fetch_ppc_registers (struct regcache *regcache, int tid) void ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) { - pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache)); + pid_t tid = get_ptrace_pid (regcache->ptid ()); if (regno == -1) fetch_ppc_registers (regcache, tid); @@ -868,15 +1031,12 @@ ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) fetch_register (regcache, tid, regno); } -/* Store one VSX register. */ static void -store_vsx_register (const struct regcache *regcache, int tid, int regno) +store_vsx_registers (const struct regcache *regcache, int tid, int regno) { int ret; gdb_vsxregset_t regs; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); + const struct regset *vsxregset = ppc_linux_vsxregset (); ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); if (ret < 0) @@ -886,27 +1046,25 @@ store_vsx_register (const struct regcache *regcache, int tid, int regno) have_ptrace_getsetvsxregs = 0; return; } - perror_with_name (_("Unable to fetch VSX register")); + perror_with_name (_("Unable to fetch VSX registers")); } - regcache_raw_collect (regcache, regno, regs + - (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize); + vsxregset->collect_regset (vsxregset, regcache, regno, ®s, + PPC_LINUX_SIZEOF_VSXREGSET); ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); if (ret < 0) - perror_with_name (_("Unable to store VSX register")); + perror_with_name (_("Unable to store VSX registers")); } -/* Store one register. */ static void -store_altivec_register (const struct regcache *regcache, int tid, int regno) +store_altivec_registers (const struct regcache *regcache, int tid, + int regno) { int ret; - int offset = 0; gdb_vrregset_t regs; struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); + const struct regset *vrregset = ppc_linux_vrregset (gdbarch); ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); if (ret < 0) @@ -916,24 +1074,18 @@ store_altivec_register (const struct regcache *regcache, int tid, int regno) have_ptrace_getvrregs = 0; return; } - perror_with_name (_("Unable to fetch AltiVec register")); + perror_with_name (_("Unable to fetch AltiVec registers")); } - /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes - long on the hardware. */ - if (regno == (tdep->ppc_vrsave_regnum - 1)) - offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); - - regcache_raw_collect (regcache, regno, - regs + (regno - - tdep->ppc_vr0_regnum) * vrregsize + offset); + vrregset->collect_regset (vrregset, regcache, regno, ®s, + PPC_LINUX_SIZEOF_VRREGSET); ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); if (ret < 0) - perror_with_name (_("Unable to store AltiVec register")); + perror_with_name (_("Unable to store AltiVec registers")); } -/* Assuming TID referrs to an SPE process, set the top halves of TID's +/* Assuming TID refers to an SPE process, set the top halves of TID's general-purpose registers and its SPE-specific registers to the values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do nothing. @@ -995,26 +1147,23 @@ store_spe_register (const struct regcache *regcache, int tid, int regno) int i; for (i = 0; i < ppc_num_gprs; i++) - regcache_raw_collect (regcache, - tdep->ppc_ev0_upper_regnum + i, - &evrregs.evr[i]); + regcache->raw_collect (tdep->ppc_ev0_upper_regnum + i, + &evrregs.evr[i]); } else if (tdep->ppc_ev0_upper_regnum <= regno && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) - regcache_raw_collect (regcache, regno, - &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); + regcache->raw_collect (regno, + &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); if (regno == -1 || regno == tdep->ppc_acc_regnum) - regcache_raw_collect (regcache, - tdep->ppc_acc_regnum, - &evrregs.acc); + regcache->raw_collect (tdep->ppc_acc_regnum, + &evrregs.acc); if (regno == -1 || regno == tdep->ppc_spefscr_regnum) - regcache_raw_collect (regcache, - tdep->ppc_spefscr_regnum, - &evrregs.spefscr); + regcache->raw_collect (tdep->ppc_spefscr_regnum, + &evrregs.spefscr); /* Write back the modified register set. */ set_spe_registers (tid, &evrregs); @@ -1033,12 +1182,12 @@ store_register (const struct regcache *regcache, int tid, int regno) if (altivec_register_p (gdbarch, regno)) { - store_altivec_register (regcache, tid, regno); + store_altivec_registers (regcache, tid, regno); return; } - if (vsx_register_p (gdbarch, regno)) + else if (vsx_register_p (gdbarch, regno)) { - store_vsx_register (regcache, tid, regno); + store_vsx_registers (regcache, tid, regno); return; } else if (spe_register_p (gdbarch, regno)) @@ -1046,6 +1195,127 @@ store_register (const struct regcache *regcache, int tid, int regno) store_spe_register (regcache, tid, regno); return; } + else if (regno == PPC_DSCR_REGNUM) + { + gdb_assert (tdep->ppc_dscr_regnum != -1); + + store_regset (regcache, tid, regno, NT_PPC_DSCR, + PPC_LINUX_SIZEOF_DSCRREGSET, + &ppc32_linux_dscrregset); + return; + } + else if (regno == PPC_PPR_REGNUM) + { + gdb_assert (tdep->ppc_ppr_regnum != -1); + + store_regset (regcache, tid, regno, NT_PPC_PPR, + PPC_LINUX_SIZEOF_PPRREGSET, + &ppc32_linux_pprregset); + return; + } + else if (regno == PPC_TAR_REGNUM) + { + gdb_assert (tdep->ppc_tar_regnum != -1); + + store_regset (regcache, tid, regno, NT_PPC_TAR, + PPC_LINUX_SIZEOF_TARREGSET, + &ppc32_linux_tarregset); + return; + } + else if (PPC_IS_EBB_REGNUM (regno)) + { + gdb_assert (tdep->have_ebb); + + store_regset (regcache, tid, regno, NT_PPC_EBB, + PPC_LINUX_SIZEOF_EBBREGSET, + &ppc32_linux_ebbregset); + return; + } + else if (PPC_IS_PMU_REGNUM (regno)) + { + gdb_assert (tdep->ppc_mmcr0_regnum != -1); + + store_regset (regcache, tid, regno, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset); + return; + } + else if (PPC_IS_TMSPR_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_spr); + + store_regset (regcache, tid, regno, NT_PPC_TM_SPR, + PPC_LINUX_SIZEOF_TM_SPRREGSET, + &ppc32_linux_tm_sprregset); + return; + } + else if (PPC_IS_CKPTGP_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_core); + + const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); + store_regset (regcache, tid, regno, NT_PPC_TM_CGPR, + (tdep->wordsize == 4? + PPC32_LINUX_SIZEOF_CGPRREGSET + : PPC64_LINUX_SIZEOF_CGPRREGSET), + cgprregset); + return; + } + else if (PPC_IS_CKPTFP_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_fpu); + + store_regset (regcache, tid, regno, NT_PPC_TM_CFPR, + PPC_LINUX_SIZEOF_CFPRREGSET, + &ppc32_linux_cfprregset); + return; + } + else if (PPC_IS_CKPTVMX_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_altivec); + + const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); + store_regset (regcache, tid, regno, NT_PPC_TM_CVMX, + PPC_LINUX_SIZEOF_CVMXREGSET, + cvmxregset); + return; + } + else if (PPC_IS_CKPTVSX_REGNUM (regno)) + { + gdb_assert (tdep->have_htm_vsx); + + store_regset (regcache, tid, regno, NT_PPC_TM_CVSX, + PPC_LINUX_SIZEOF_CVSXREGSET, + &ppc32_linux_cvsxregset); + return; + } + else if (regno == PPC_CPPR_REGNUM) + { + gdb_assert (tdep->ppc_cppr_regnum != -1); + + store_regset (regcache, tid, regno, NT_PPC_TM_CPPR, + PPC_LINUX_SIZEOF_CPPRREGSET, + &ppc32_linux_cpprregset); + return; + } + else if (regno == PPC_CDSCR_REGNUM) + { + gdb_assert (tdep->ppc_cdscr_regnum != -1); + + store_regset (regcache, tid, regno, NT_PPC_TM_CDSCR, + PPC_LINUX_SIZEOF_CDSCRREGSET, + &ppc32_linux_cdscrregset); + return; + } + else if (regno == PPC_CTAR_REGNUM) + { + gdb_assert (tdep->ppc_ctar_regnum != -1); + + store_regset (regcache, tid, regno, NT_PPC_TM_CTAR, + PPC_LINUX_SIZEOF_CTARREGSET, + &ppc32_linux_ctarregset); + return; + } if (regaddr == -1) return; @@ -1058,13 +1328,13 @@ store_register (const struct regcache *regcache, int tid, int regno) if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) { /* Little-endian values always sit at the left end of the buffer. */ - regcache_raw_collect (regcache, regno, buf); + regcache->raw_collect (regno, buf); } else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) { /* Big-endian values sit at the right end of the buffer. */ size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); - regcache_raw_collect (regcache, regno, buf + padding); + regcache->raw_collect (regno, buf + padding); } for (i = 0; i < bytes_to_transfer; i += sizeof (long)) @@ -1096,88 +1366,6 @@ store_register (const struct regcache *regcache, int tid, int regno) } } -static void -fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp) -{ - int i; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum); - - for (i = 0; i < ppc_num_vshrs; i++) - regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i, - *vsxregsetp + i * vsxregsize); -} - -static void -fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp) -{ - int i; - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1; - int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum); - int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum); - - for (i = 0; i < num_of_vrregs; i++) - { - /* The last 2 registers of this set are only 32 bit long, not - 128, but only VSCR is fetched as a 16 bytes quantity. */ - if (i == (num_of_vrregs - 2)) - regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize + offset); - else - regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i, - *vrregsetp + i * vrregsize); - } -} - -static void -store_vsx_registers (const struct regcache *regcache, int tid) -{ - int ret; - gdb_vsxregset_t regs; - - ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); - if (ret < 0) - { - if (errno == EIO) - { - have_ptrace_getsetvsxregs = 0; - return; - } - perror_with_name (_("Couldn't get VSX registers")); - } - - fill_vsxregset (regcache, ®s); - - if (ptrace (PTRACE_SETVSXREGS, tid, 0, ®s) < 0) - perror_with_name (_("Couldn't write VSX registers")); -} - -static void -store_altivec_registers (const struct regcache *regcache, int tid) -{ - int ret; - gdb_vrregset_t regs; - - ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); - if (ret < 0) - { - if (errno == EIO) - { - have_ptrace_getvrregs = 0; - return; - } - perror_with_name (_("Couldn't get AltiVec registers")); - } - - fill_vrregset (regcache, ®s); - - if (ptrace (PTRACE_SETVRREGS, tid, 0, ®s) < 0) - perror_with_name (_("Couldn't write AltiVec registers")); -} - /* This function actually issues the request to ptrace, telling it to store all general-purpose registers present in the specified regset. @@ -1189,8 +1377,6 @@ store_altivec_registers (const struct regcache *regcache, int tid) static int store_all_gp_regs (const struct regcache *regcache, int tid, int regno) { - struct gdbarch *gdbarch = regcache->arch (); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); gdb_gregset_t gregset; if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) @@ -1307,7 +1493,6 @@ store_fp_regs (const struct regcache *regcache, int tid, int regno) static void store_ppc_registers (const struct regcache *regcache, int tid) { - int i; struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -1336,24 +1521,38 @@ store_ppc_registers (const struct regcache *regcache, int tid) } if (have_ptrace_getvrregs) if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) - store_altivec_registers (regcache, tid); + store_altivec_registers (regcache, tid, -1); if (have_ptrace_getsetvsxregs) if (tdep->ppc_vsr0_upper_regnum != -1) - store_vsx_registers (regcache, tid); + store_vsx_registers (regcache, tid, -1); if (tdep->ppc_ev0_upper_regnum >= 0) store_spe_register (regcache, tid, -1); -} - -/* Fetch the AT_HWCAP entry from the aux vector. */ -static unsigned long -ppc_linux_get_hwcap (void) -{ - CORE_ADDR field; - - if (target_auxv_search (target_stack, AT_HWCAP, &field)) - return (unsigned long) field; - - return 0; + if (tdep->ppc_ppr_regnum != -1) + store_regset (regcache, tid, -1, NT_PPC_PPR, + PPC_LINUX_SIZEOF_PPRREGSET, + &ppc32_linux_pprregset); + if (tdep->ppc_dscr_regnum != -1) + store_regset (regcache, tid, -1, NT_PPC_DSCR, + PPC_LINUX_SIZEOF_DSCRREGSET, + &ppc32_linux_dscrregset); + if (tdep->ppc_tar_regnum != -1) + store_regset (regcache, tid, -1, NT_PPC_TAR, + PPC_LINUX_SIZEOF_TARREGSET, + &ppc32_linux_tarregset); + + if (tdep->ppc_mmcr0_regnum != -1) + store_regset (regcache, tid, -1, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset); + + if (tdep->have_htm_spr) + store_regset (regcache, tid, -1, NT_PPC_TM_SPR, + PPC_LINUX_SIZEOF_TM_SPRREGSET, + &ppc32_linux_tm_sprregset); + + /* Because the EBB and checkpointed HTM registers can be + unavailable, attempts to store them here would cause this + function to fail most of the time, so we ignore them. */ } /* The cached DABR value, to install in new threads. @@ -1376,10 +1575,10 @@ struct hw_break_tuple struct ppc_hw_breakpoint *hw_break; }; -/* This is an internal VEC created to store information about *points inserted - for each thread. This is used when PowerPC HWDEBUG ptrace interface is - available. */ -typedef struct thread_points +/* This is an internal vector created to store information about *points + inserted for each thread. This is used when PowerPC HWDEBUG ptrace + interface is available. */ +struct thread_points { /* The TID to which this *point relates. */ int tid; @@ -1390,10 +1589,9 @@ typedef struct thread_points size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of the tuple is NULL, then the position in the vector is free. */ struct hw_break_tuple *hw_breaks; - } *thread_points_p; -DEF_VEC_P (thread_points_p); + }; -VEC(thread_points_p) *ppc_threads = NULL; +static std::vector ppc_threads; /* The version of the PowerPC HWDEBUG kernel interface that we will use, if available. */ @@ -1409,9 +1607,9 @@ have_ptrace_hwdebug_interface (void) { int tid; - tid = ptid_get_lwp (inferior_ptid); + tid = inferior_ptid.lwp (); if (tid == 0) - tid = ptid_get_pid (inferior_ptid); + tid = inferior_ptid.pid (); /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */ if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0) @@ -1481,9 +1679,9 @@ ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, int ot) /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG and whether the target has DABR. If either answer is no, the ptrace call will return -1. Fail in that case. */ - tid = ptid_get_lwp (ptid); + tid = ptid.lwp (); if (tid == 0) - tid = ptid_get_pid (ptid); + tid = ptid.pid (); if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1) return 0; @@ -1512,7 +1710,7 @@ ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) takes two hardware watchpoints though. */ if (len > 1 && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE - && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) + && linux_get_hwcap (current_top_target ()) & PPC_FEATURE_BOOKE) return 2; /* Check if the processor provides DAWR interface. */ if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) @@ -1532,7 +1730,7 @@ ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) ptrace interface, DAC-based processors (i.e., embedded processors) will use addresses aligned to 4-bytes due to the way the read/write flags are passed in the old ptrace interface. */ - else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) + else if (((linux_get_hwcap (current_top_target ()) & PPC_FEATURE_BOOKE) && (addr + len) > (addr & ~3) + 4) || (addr + len) > (addr & ~7) + 8) return 0; @@ -1559,14 +1757,13 @@ hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b) static struct thread_points * hwdebug_find_thread_points_by_tid (int tid, int alloc_new) { - int i; - struct thread_points *t; - - for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++) - if (t->tid == tid) - return t; + for (thread_points *t : ppc_threads) + { + if (t->tid == tid) + return t; + } - t = NULL; + struct thread_points *t = NULL; /* Do we need to allocate a new point_item if the wanted one does not exist? */ @@ -1575,7 +1772,7 @@ hwdebug_find_thread_points_by_tid (int tid, int alloc_new) t = XNEW (struct thread_points); t->hw_breaks = XCNEWVEC (struct hw_break_tuple, max_slots_number); t->tid = tid; - VEC_safe_push (thread_points_p, ppc_threads, t); + ppc_threads.push_back (t); } return t; @@ -1592,7 +1789,6 @@ hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) gdb::unique_xmalloc_ptr p (XDUP (ppc_hw_breakpoint, b)); struct hw_break_tuple *hw_breaks; struct thread_points *t; - struct hw_break_tuple *tuple; errno = 0; slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p.get ()); @@ -1606,12 +1802,14 @@ hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid) /* Find a free element in the hw_breaks vector. */ for (i = 0; i < max_slots_number; i++) - if (hw_breaks[i].hw_break == NULL) - { - hw_breaks[i].slot = slot; - hw_breaks[i].hw_break = p.release (); - break; - } + { + if (hw_breaks[i].hw_break == NULL) + { + hw_breaks[i].slot = slot; + hw_breaks[i].hw_break = p.release (); + break; + } + } gdb_assert (i != max_slots_number); } @@ -1693,7 +1891,7 @@ ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, } ALL_LWPS (lp) - hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_insert_point (&p, lp->ptid.lwp ()); return 0; } @@ -1729,7 +1927,7 @@ ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, } ALL_LWPS (lp) - hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_remove_point (&p, lp->ptid.lwp ()); return 0; } @@ -1772,7 +1970,7 @@ ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, p.condition_value = 0; ALL_LWPS (lp) - hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_insert_point (&p, lp->ptid.lwp ()); return 0; } @@ -1800,7 +1998,7 @@ ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, p.condition_value = 0; ALL_LWPS (lp) - hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_remove_point (&p, lp->ptid.lwp ()); return 0; } @@ -1810,9 +2008,8 @@ static int can_use_watchpoint_cond_accel (void) { struct thread_points *p; - int tid = ptid_get_lwp (inferior_ptid); + int tid = inferior_ptid.lwp (); int cnt = hwdebug_info.num_condition_regs, i; - CORE_ADDR tmp_value; if (!have_ptrace_hwdebug_interface () || cnt == 0) return 0; @@ -1986,7 +2183,7 @@ check_condition (CORE_ADDR watch_addr, struct expression *cond, /* Return non-zero if the target is capable of using hardware to evaluate the condition expression, thus only triggering the watchpoint when it is true. */ -int +bool ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len, int rw, struct expression *cond) @@ -2064,7 +2261,7 @@ ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, create_watchpoint_request (&p, addr, len, type, cond, 1); ALL_LWPS (lp) - hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_insert_point (&p, lp->ptid.lwp ()); ret = 0; } @@ -2073,7 +2270,7 @@ ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, long dabr_value; long read_mode, write_mode; - if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) + if (linux_get_hwcap (current_top_target ()) & PPC_FEATURE_BOOKE) { /* PowerPC 440 requires only the read/write flags to be passed to the kernel. */ @@ -2108,7 +2305,7 @@ ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, saved_dabr_value = dabr_value; ALL_LWPS (lp) - if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, + if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, saved_dabr_value) < 0) return -1; @@ -2133,7 +2330,7 @@ ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, create_watchpoint_request (&p, addr, len, type, cond, 0); ALL_LWPS (lp) - hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid)); + hwdebug_remove_point (&p, lp->ptid.lwp ()); ret = 0; } @@ -2141,7 +2338,7 @@ ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, { saved_dabr_value = 0; ALL_LWPS (lp) - if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0, + if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, saved_dabr_value) < 0) return -1; @@ -2151,10 +2348,10 @@ ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, return ret; } -static void -ppc_linux_new_thread (struct lwp_info *lp) +void +ppc_linux_nat_target::low_new_thread (struct lwp_info *lp) { - int tid = ptid_get_lwp (lp->ptid); + int tid = lp->ptid.lwp (); if (have_ptrace_hwdebug_interface ()) { @@ -2162,11 +2359,11 @@ ppc_linux_new_thread (struct lwp_info *lp) struct thread_points *p; struct hw_break_tuple *hw_breaks; - if (VEC_empty (thread_points_p, ppc_threads)) + if (ppc_threads.empty ()) return; /* Get a list of breakpoints from any thread. */ - p = VEC_last (thread_points_p, ppc_threads); + p = ppc_threads.back (); hw_breaks = p->hw_breaks; /* Copy that thread's breakpoints and watchpoints to the new thread. */ @@ -2193,24 +2390,26 @@ static void ppc_linux_thread_exit (struct thread_info *tp, int silent) { int i; - int tid = ptid_get_lwp (tp->ptid); + int tid = tp->ptid.lwp (); struct hw_break_tuple *hw_breaks; - struct thread_points *t = NULL, *p; + struct thread_points *t = NULL; if (!have_ptrace_hwdebug_interface ()) return; - for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++) - if (p->tid == tid) - { - t = p; - break; - } + for (i = 0; i < ppc_threads.size (); i++) + { + if (ppc_threads[i]->tid == tid) + { + t = ppc_threads[i]; + break; + } + } if (t == NULL) return; - VEC_unordered_remove (thread_points_p, ppc_threads, i); + unordered_remove (ppc_threads, i); hw_breaks = t->hw_breaks; @@ -2222,17 +2421,17 @@ ppc_linux_thread_exit (struct thread_info *tp, int silent) xfree (t); } -int +bool ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) { siginfo_t siginfo; if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) - return 0; + return false; if (siginfo.si_signo != SIGTRAP || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) - return 0; + return false; if (have_ptrace_hwdebug_interface ()) { @@ -2242,7 +2441,7 @@ ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) /* The index (or slot) of the *point is passed in the si_errno field. */ int slot = siginfo.si_errno; - t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0); + t = hwdebug_find_thread_points_by_tid (inferior_ptid.lwp (), 0); /* Find out if this *point is a hardware breakpoint. If so, we should return 0. */ @@ -2253,22 +2452,22 @@ ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot && hw_breaks[i].hw_break->trigger_type == PPC_BREAKPOINT_TRIGGER_EXECUTE) - return 0; + return false; } } *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; - return 1; + return true; } -int +bool ppc_linux_nat_target::stopped_by_watchpoint () { CORE_ADDR addr; return stopped_data_address (&addr); } -int +bool ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, CORE_ADDR start, int length) @@ -2276,9 +2475,9 @@ ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, int mask; if (have_ptrace_hwdebug_interface () - && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) + && linux_get_hwcap (current_top_target ()) & PPC_FEATURE_BOOKE) return start <= addr && start + length >= addr; - else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE) + else if (linux_get_hwcap (current_top_target ()) & PPC_FEATURE_BOOKE) mask = 3; else mask = 7; @@ -2311,7 +2510,7 @@ ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, CORE_ADDR mask void ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno) { - pid_t tid = get_ptrace_pid (regcache_get_ptid (regcache)); + pid_t tid = get_ptrace_pid (regcache->ptid ()); if (regno >= 0) store_register (regcache, tid, regno); @@ -2363,35 +2562,17 @@ fill_fpregset (const struct regcache *regcache, fpregsetp, sizeof (*fpregsetp)); } -static int -ppc_linux_target_wordsize (void) -{ - int wordsize = 4; - - /* Check for 64-bit inferior process. This is the case when the host is - 64-bit, and in addition the top bit of the MSR register is set. */ -#ifdef __powerpc64__ - long msr; - - int tid = ptid_get_lwp (inferior_ptid); - if (tid == 0) - tid = ptid_get_pid (inferior_ptid); - - errno = 0; - msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0); - if (errno == 0 && ppc64_64bit_inferior_p (msr)) - wordsize = 8; -#endif - - return wordsize; -} - int ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) { - int sizeof_auxv_field = ppc_linux_target_wordsize (); + int tid = inferior_ptid.lwp (); + if (tid == 0) + tid = inferior_ptid.pid (); + + int sizeof_auxv_field = ppc_linux_target_wordsize (tid); + enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); gdb_byte *ptr = *readptr; @@ -2413,14 +2594,9 @@ ppc_linux_nat_target::auxv_parse (gdb_byte **readptr, const struct target_desc * ppc_linux_nat_target::read_description () { - int altivec = 0; - int vsx = 0; - int isa205 = 0; - int cell = 0; - - int tid = ptid_get_lwp (inferior_ptid); + int tid = inferior_ptid.lwp (); if (tid == 0) - tid = ptid_get_pid (inferior_ptid); + tid = inferior_ptid.pid (); if (have_ptrace_getsetevrregs) { @@ -2435,13 +2611,20 @@ ppc_linux_nat_target::read_description () perror_with_name (_("Unable to fetch SPE registers")); } + struct ppc_linux_features features = ppc_linux_no_features; + + features.wordsize = ppc_linux_target_wordsize (tid); + + CORE_ADDR hwcap = linux_get_hwcap (current_top_target ()); + CORE_ADDR hwcap2 = linux_get_hwcap2 (current_top_target ()); + if (have_ptrace_getsetvsxregs - && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_VSX)) + && (hwcap & PPC_FEATURE_HAS_VSX)) { gdb_vsxregset_t vsxregset; if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) - vsx = 1; + features.vsx = true; /* EIO means that the PTRACE_GETVSXREGS request isn't supported. Anything else needs to be reported. */ @@ -2450,12 +2633,12 @@ ppc_linux_nat_target::read_description () } if (have_ptrace_getvrregs - && (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_ALTIVEC)) + && (hwcap & PPC_FEATURE_HAS_ALTIVEC)) { gdb_vrregset_t vrregset; if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) - altivec = 1; + features.altivec = true; /* EIO means that the PTRACE_GETVRREGS request isn't supported. Anything else needs to be reported. */ @@ -2463,39 +2646,29 @@ ppc_linux_nat_target::read_description () perror_with_name (_("Unable to fetch AltiVec registers")); } - /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases - the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this - ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only - PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher - half of the register are for Decimal Floating Point, we check if that - feature is available to decide the size of the FPSCR. */ - if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP) - isa205 = 1; + features.isa205 = ppc_linux_has_isa205 (hwcap); - if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL) - cell = 1; - - if (ppc_linux_target_wordsize () == 8) + if ((hwcap2 & PPC_FEATURE2_DSCR) + && check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET) + && check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)) { - if (cell) - return tdesc_powerpc_cell64l; - else if (vsx) - return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l; - else if (altivec) - return isa205 - ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l; - - return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l; + features.ppr_dscr = true; + if ((hwcap2 & PPC_FEATURE2_ARCH_2_07) + && (hwcap2 & PPC_FEATURE2_TAR) + && (hwcap2 & PPC_FEATURE2_EBB) + && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET) + && check_regset (tid, NT_PPC_EBB, PPC_LINUX_SIZEOF_EBBREGSET) + && check_regset (tid, NT_PPC_PMU, PPC_LINUX_SIZEOF_PMUREGSET)) + { + features.isa207 = true; + if ((hwcap2 & PPC_FEATURE2_HTM) + && check_regset (tid, NT_PPC_TM_SPR, + PPC_LINUX_SIZEOF_TM_SPRREGSET)) + features.htm = true; + } } - if (cell) - return tdesc_powerpc_cell32l; - else if (vsx) - return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l; - else if (altivec) - return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l; - - return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l; + return ppc_linux_match_description (features); } void @@ -2506,7 +2679,5 @@ _initialize_ppc_linux_nat (void) gdb::observers::thread_exit.attach (ppc_linux_thread_exit); /* Register the target. */ - add_target (linux_target); - - linux_nat_set_new_thread (linux_target, ppc_linux_new_thread); + add_inf_child_target (linux_target); }