X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Friscv-linux-nat.c;h=2f95cb3951ad98037e40aa87ce035f6941113ff6;hb=f5a7c406b1975cde626efed526960f2cf1bdaceb;hp=7dbfe651f2c77a86d126a47685cbd5162d5ff9e5;hpb=4d3928d7e0a141e0fb16405d33b375cbe2f13123;p=deliverable%2Fbinutils-gdb.git

diff --git a/gdb/riscv-linux-nat.c b/gdb/riscv-linux-nat.c
index 7dbfe651f2..2f95cb3951 100644
--- a/gdb/riscv-linux-nat.c
+++ b/gdb/riscv-linux-nat.c
@@ -1,5 +1,5 @@
 /* Native-dependent code for GNU/Linux RISC-V.
-   Copyright (C) 2018 Free Software Foundation, Inc.
+   Copyright (C) 2018-2020 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -21,6 +21,8 @@
 #include "gregset.h"
 #include "linux-nat.h"
 #include "riscv-tdep.h"
+#include "inferior.h"
+#include "target-descriptions.h"
 
 #include "elf/common.h"
 
@@ -34,6 +36,9 @@ public:
   /* Add our register access methods.  */
   void fetch_registers (struct regcache *regcache, int regnum) override;
   void store_registers (struct regcache *regcache, int regnum) override;
+
+  /* Read suitable target description.  */
+  const struct target_desc *read_description () override;
 };
 
 static riscv_linux_nat_target the_riscv_linux_nat_target;
@@ -155,6 +160,39 @@ fill_fpregset (const struct regcache *regcache, prfpregset_t *fpregs,
     regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, &fpregs->__d.__fcsr);
 }
 
+/* Return a target description for the current target.  */
+
+const struct target_desc *
+riscv_linux_nat_target::read_description ()
+{
+  struct riscv_gdbarch_features features;
+  struct iovec iov;
+  elf_fpregset_t regs;
+  int tid;
+
+  /* Figuring out xlen is easy.  */
+  features.xlen = sizeof (elf_greg_t);
+
+  tid = inferior_ptid.lwp ();
+
+  iov.iov_base = &regs;
+  iov.iov_len = sizeof (regs);
+
+  /* Can we fetch the f-registers?  */
+  if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
+	      (PTRACE_TYPE_ARG3) &iov) == -1)
+    features.flen = 0;		/* No f-registers.  */
+  else
+    {
+      /* TODO: We need a way to figure out the actual length of the
+	 f-registers.  We could have 64-bit x-registers, with 32-bit
+	 f-registers.  For now, just assumed xlen and flen match.  */
+      features.flen = features.xlen;
+    }
+
+  return riscv_create_target_description (features);
+}
+
 /* Fetch REGNUM (or all registers if REGNUM == -1) from the target
    into REGCACHE using PTRACE_GETREGSET.  */
 
@@ -203,7 +241,7 @@ riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
       || (regnum == -1))
     {
       /* TODO: Need to add a ptrace call for this.  */
-      regcache->raw_supply_zeroed (regnum);
+      regcache->raw_supply_zeroed (RISCV_CSR_MISA_REGNUM);
     }
 
   /* Access to other CSRs has potential security issues, don't support them for