X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Frs6000-tdep.c;h=7f37d3e4514856e63fabce26821f2a59a49caa44;hb=43259571aca0944565543698d044240ecfef4689;hp=1302066a35366eac420c71e5073d3f448cca4952;hpb=61ce229a503d78b03e3ba1d8adc5f8ebfb6542f3;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index 1302066a35..7f37d3e451 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -1,7 +1,7 @@ /* Target-dependent code for GDB, the GNU debugger. Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, - 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software + 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This file is part of GDB. @@ -37,6 +37,9 @@ #include "parser-defs.h" #include "osabi.h" #include "infcall.h" +#include "sim-regno.h" +#include "gdb/sim-ppc.h" +#include "reggroups.h" #include "libbfd.h" /* for bfd_default_set_arch_mach */ #include "coff/internal.h" /* for libcoff.h */ @@ -56,6 +59,8 @@ #include "frame-unwind.h" #include "frame-base.h" +#include "reggroups.h" + /* If the kernel has to deliver a signal, it pushes a sigcontext structure on the stack and then calls the signal handler, passing the address of the sigcontext in an argument register. Usually @@ -99,17 +104,20 @@ struct reg unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ unsigned char fpr; /* whether register is floating-point */ unsigned char pseudo; /* whether register is pseudo */ + int spr_num; /* PowerPC SPR number, or -1 if not an SPR. + This is an ISA SPR number, not a GDB + register number. */ }; /* Breakpoint shadows for the single step instructions will be kept here. */ static struct sstep_breaks - { - /* Address, or 0 if this is not in use. */ - CORE_ADDR address; - /* Shadow contents. */ - char data[4]; - } +{ + /* Address, or 0 if this is not in use. */ + CORE_ADDR address; + /* Shadow contents. */ + gdb_byte data[4]; +} stepBreaks[2]; /* Hook for determining the TOC address when calling functions in the @@ -154,6 +162,12 @@ spe_register_p (int regno) && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) return 1; + /* Is it a reference to one of the raw upper GPR halves? */ + if (tdep->ppc_ev0_upper_regnum >= 0 + && tdep->ppc_ev0_upper_regnum <= regno + && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) + return 1; + /* Is it a reference to the 64-bit accumulator, and do we have that? */ if (tdep->ppc_acc_regnum >= 0 && tdep->ppc_acc_regnum == regno) @@ -179,13 +193,133 @@ ppc_floating_point_unit_p (struct gdbarch *gdbarch) return (tdep->ppc_fp0_regnum >= 0 && tdep->ppc_fpscr_regnum >= 0); } + + +/* Check that TABLE[GDB_REGNO] is not already initialized, and then + set it to SIM_REGNO. + + This is a helper function for init_sim_regno_table, constructing + the table mapping GDB register numbers to sim register numbers; we + initialize every element in that table to -1 before we start + filling it in. */ +static void +set_sim_regno (int *table, int gdb_regno, int sim_regno) +{ + /* Make sure we don't try to assign any given GDB register a sim + register number more than once. */ + gdb_assert (table[gdb_regno] == -1); + table[gdb_regno] = sim_regno; +} + + +/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register + numbers to simulator register numbers, based on the values placed + in the ARCH->tdep->ppc_foo_regnum members. */ +static void +init_sim_regno_table (struct gdbarch *arch) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (arch); + int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch); + const struct reg *regs = tdep->regs; + int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); + int i; + + /* Presume that all registers not explicitly mentioned below are + unavailable from the sim. */ + for (i = 0; i < total_regs; i++) + sim_regno[i] = -1; + + /* General-purpose registers. */ + for (i = 0; i < ppc_num_gprs; i++) + set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); + + /* Floating-point registers. */ + if (tdep->ppc_fp0_regnum >= 0) + for (i = 0; i < ppc_num_fprs; i++) + set_sim_regno (sim_regno, + tdep->ppc_fp0_regnum + i, + sim_ppc_f0_regnum + i); + if (tdep->ppc_fpscr_regnum >= 0) + set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); + + set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); + set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); + set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); + + /* Segment registers. */ + if (tdep->ppc_sr0_regnum >= 0) + for (i = 0; i < ppc_num_srs; i++) + set_sim_regno (sim_regno, + tdep->ppc_sr0_regnum + i, + sim_ppc_sr0_regnum + i); + + /* Altivec registers. */ + if (tdep->ppc_vr0_regnum >= 0) + { + for (i = 0; i < ppc_num_vrs; i++) + set_sim_regno (sim_regno, + tdep->ppc_vr0_regnum + i, + sim_ppc_vr0_regnum + i); + + /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, + we can treat this more like the other cases. */ + set_sim_regno (sim_regno, + tdep->ppc_vr0_regnum + ppc_num_vrs, + sim_ppc_vscr_regnum); + } + /* vsave is a special-purpose register, so the code below handles it. */ + + /* SPE APU (E500) registers. */ + if (tdep->ppc_ev0_regnum >= 0) + for (i = 0; i < ppc_num_gprs; i++) + set_sim_regno (sim_regno, + tdep->ppc_ev0_regnum + i, + sim_ppc_ev0_regnum + i); + if (tdep->ppc_ev0_upper_regnum >= 0) + for (i = 0; i < ppc_num_gprs; i++) + set_sim_regno (sim_regno, + tdep->ppc_ev0_upper_regnum + i, + sim_ppc_rh0_regnum + i); + if (tdep->ppc_acc_regnum >= 0) + set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); + /* spefscr is a special-purpose register, so the code below handles it. */ + + /* Now handle all special-purpose registers. Verify that they + haven't mistakenly been assigned numbers by any of the above + code). */ + for (i = 0; i < total_regs; i++) + if (regs[i].spr_num >= 0) + set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum); + + /* Drop the initialized array into place. */ + tdep->sim_regno = sim_regno; +} + + +/* Given a GDB register number REG, return the corresponding SIM + register number. */ +static int +rs6000_register_sim_regno (int reg) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); + int sim_regno; + + gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS); + sim_regno = tdep->sim_regno[reg]; + + if (sim_regno >= 0) + return sim_regno; + else + return LEGACY_SIM_REGNO_IGNORE; +} + /* Register set support functions. */ static void ppc_supply_reg (struct regcache *regcache, int regnum, - const char *regs, size_t offset) + const gdb_byte *regs, size_t offset) { if (regnum != -1 && offset != -1) regcache_raw_supply (regcache, regnum, regs + offset); @@ -193,7 +327,7 @@ ppc_supply_reg (struct regcache *regcache, int regnum, static void ppc_collect_reg (const struct regcache *regcache, int regnum, - char *regs, size_t offset) + gdb_byte *regs, size_t offset) { if (regnum != -1 && offset != -1) regcache_raw_collect (regcache, regnum, regs + offset); @@ -261,7 +395,7 @@ ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, offset = offsets->f0_offset; for (i = tdep->ppc_fp0_regnum; i < tdep->ppc_fp0_regnum + ppc_num_fprs; - i++, offset += 4) + i++, offset += 8) { if (regnum == -1 || regnum == i) ppc_supply_reg (regcache, i, fpregs, offset); @@ -340,10 +474,10 @@ ppc_collect_fpregset (const struct regset *regset, offset = offsets->f0_offset; for (i = tdep->ppc_fp0_regnum; i <= tdep->ppc_fp0_regnum + ppc_num_fprs; - i++, offset += 4) + i++, offset += 8) { if (regnum == -1 || regnum == i) - ppc_collect_reg (regcache, regnum, fpregs, offset); + ppc_collect_reg (regcache, i, fpregs, offset); } if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) @@ -386,9 +520,7 @@ static CORE_ADDR rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, struct type *type) { - CORE_ADDR addr; - get_frame_register (frame, 3 + argi, &addr); - return addr; + return get_frame_register_unsigned (frame, 3 + argi); } /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ @@ -487,7 +619,7 @@ rs6000_software_single_step (enum target_signal signal, { CORE_ADDR dummy; int breakp_sz; - const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); + const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); int ii, insn; CORE_ADDR loc; CORE_ADDR breaks[2]; @@ -697,7 +829,7 @@ skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) CORE_ADDR orig_pc = pc; CORE_ADDR last_prologue_pc = pc; CORE_ADDR li_found_pc = 0; - char buf[4]; + gdb_byte buf[4]; unsigned long op; long offset = 0; long vr_saved_offset = 0; @@ -849,7 +981,7 @@ skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) continue; } - else if (lr_reg != -1 && + else if (lr_reg >= 0 && /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || /* stw Rx, NUM(r1) */ @@ -859,7 +991,9 @@ skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) { /* where Rx == lr */ fdata->lr_offset = offset; fdata->nosavedpc = 0; - lr_reg = 0; + /* Invalidate lr_reg, but don't set it to -1. + That would mean that it had never been set. */ + lr_reg = -2; if ((op & 0xfc000003) == 0xf8000000 || /* std */ (op & 0xfc000000) == 0x90000000) /* stw */ { @@ -869,7 +1003,7 @@ skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) continue; } - else if (cr_reg != -1 && + else if (cr_reg >= 0 && /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || /* stw Rx, NUM(r1) */ @@ -878,7 +1012,9 @@ skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) ((op & 0xffff0000) == (cr_reg | 0x94010000)))) { /* where Rx == cr */ fdata->cr_offset = offset; - cr_reg = 0; + /* Invalidate cr_reg, but don't set it to -1. + That would mean that it had never been set. */ + cr_reg = -2; if ((op & 0xfc000003) == 0xf8000000 || (op & 0xfc000000) == 0x90000000) { @@ -912,9 +1048,18 @@ skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) fdata->frameless = 0; /* Don't skip over the subroutine call if it is not within - the first three instructions of the prologue. */ + the first three instructions of the prologue and either + we have no line table information or the line info tells + us that the subroutine call is not part of the line + associated with the prologue. */ if ((pc - orig_pc) > 8) - break; + { + struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); + struct symtab_and_line this_sal = find_pc_line (pc, 0); + + if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line)) + break; + } op = read_memory_integer (pc + 4, 4); @@ -1282,7 +1427,7 @@ rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, int len = 0; int argno; /* current argument number */ int argbytes; /* current argument byte */ - char tmp_buffer[50]; + gdb_byte tmp_buffer[50]; int f_argno = 0; /* current floating point argno */ int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; CORE_ADDR func_addr = find_function_addr (function, NULL); @@ -1333,10 +1478,10 @@ rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) { - int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3); + int reg_size = register_size (current_gdbarch, ii + 3); arg = args[argno]; - type = check_typedef (VALUE_TYPE (arg)); + type = check_typedef (value_type (arg)); len = TYPE_LENGTH (type); if (TYPE_CODE (type) == TYPE_CODE_FLT) @@ -1346,14 +1491,11 @@ rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, There are 13 fpr's reserved for passing parameters. At this point there is no way we would run out of them. */ - if (len > 8) - printf_unfiltered ("Fatal Error: a floating point parameter " - "#%d with a size > 8 is found!\n", argno); + gdb_assert (len <= 8); - memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE - (tdep->ppc_fp0_regnum + 1 + f_argno)], - VALUE_CONTENTS (arg), - len); + regcache_cooked_write (regcache, + tdep->ppc_fp0_regnum + 1 + f_argno, + value_contents (arg)); ++f_argno; } @@ -1363,12 +1505,15 @@ rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, /* Argument takes more than one register. */ while (argbytes < len) { - memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, - reg_size); - memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], - ((char *) VALUE_CONTENTS (arg)) + argbytes, + gdb_byte word[MAX_REGISTER_SIZE]; + memset (word, 0, reg_size); + memcpy (word, + ((char *) value_contents (arg)) + argbytes, (len - argbytes) > reg_size ? reg_size : len - argbytes); + regcache_cooked_write (regcache, + tdep->ppc_gp0_regnum + 3 + ii, + word); ++ii, argbytes += reg_size; if (ii >= 8) @@ -1381,9 +1526,11 @@ rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, { /* Argument can fit in one register. No problem. */ int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; - memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size); - memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, - VALUE_CONTENTS (arg), len); + gdb_byte word[MAX_REGISTER_SIZE]; + + memset (word, 0, reg_size); + memcpy (word, value_contents (arg), len); + regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word); } ++argno; } @@ -1419,7 +1566,7 @@ ran_out_of_registers_for_arguments: for (; jj < nargs; ++jj) { struct value *val = args[jj]; - space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; + space += ((TYPE_LENGTH (value_type (val))) + 3) & -4; } /* Add location required for the rest of the parameters. */ @@ -1440,7 +1587,7 @@ ran_out_of_registers_for_arguments: if (argbytes) { write_memory (sp + 24 + (ii * 4), - ((char *) VALUE_CONTENTS (arg)) + argbytes, + value_contents (arg) + argbytes, len - argbytes); ++argno; ii += ((len - argbytes + 3) & -4) / 4; @@ -1451,7 +1598,7 @@ ran_out_of_registers_for_arguments: { arg = args[argno]; - type = check_typedef (VALUE_TYPE (arg)); + type = check_typedef (value_type (arg)); len = TYPE_LENGTH (type); @@ -1460,21 +1607,15 @@ ran_out_of_registers_for_arguments: if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) { - if (len > 8) - printf_unfiltered ("Fatal Error: a floating point parameter" - " #%d with a size > 8 is found!\n", argno); + gdb_assert (len <= 8); - memcpy (&(deprecated_registers - [DEPRECATED_REGISTER_BYTE - (tdep->ppc_fp0_regnum + 1 + f_argno)]), - VALUE_CONTENTS (arg), - len); + regcache_cooked_write (regcache, + tdep->ppc_fp0_regnum + 1 + f_argno, + value_contents (arg)); ++f_argno; } - write_memory (sp + 24 + (ii * 4), - (char *) VALUE_CONTENTS (arg), - len); + write_memory (sp + 24 + (ii * 4), value_contents (arg), len); ii += ((len + 3) & -4) / 4; } } @@ -1520,7 +1661,8 @@ rs6000_use_struct_convention (int gcc_p, struct type *value_type) } static void -rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) +rs6000_extract_return_value (struct type *valtype, gdb_byte *regbuf, + gdb_byte *valbuf) { int offset = 0; struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); @@ -1554,8 +1696,8 @@ rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) { /* return value is copied starting from r3. */ if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG - && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3)) - offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); + && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3)) + offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype); memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, @@ -1578,12 +1720,13 @@ rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) back to where execution should continue. GDB should silently step over @FIX code, just like AIX dbx does. - Unfortunately, the linker uses the "b" instruction for the branches, - meaning that the link register doesn't get set. Therefore, GDB's usual - step_over_function() mechanism won't work. + Unfortunately, the linker uses the "b" instruction for the + branches, meaning that the link register doesn't get set. + Therefore, GDB's usual step_over_function () mechanism won't work. - Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks - in handle_inferior_event() to skip past @FIX code. */ + Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and + SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past + @FIX code. */ int rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) @@ -1627,7 +1770,9 @@ rs6000_skip_trampoline_code (CORE_ADDR pc) /* Check for bigtoc fixup code. */ msymbol = lookup_minimal_symbol_by_pc (pc); - if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) + if (msymbol + && rs6000_in_solib_return_trampoline (pc, + DEPRECATED_SYMBOL_NAME (msymbol))) { /* Double-check that the third instruction from PC is relative "b". */ op = read_memory_integer (pc + 8, 4); @@ -1709,12 +1854,64 @@ rs6000_register_type (struct gdbarch *gdbarch, int n) return builtin_type_vec128; break; default: - internal_error (__FILE__, __LINE__, "Register %d size %d unknown", + internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"), n, size); } } } +/* Is REGNUM a member of REGGROUP? */ +static int +rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum, + struct reggroup *group) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + int float_p; + int vector_p; + int general_p; + + if (REGISTER_NAME (regnum) == NULL + || *REGISTER_NAME (regnum) == '\0') + return 0; + if (group == all_reggroup) + return 1; + + float_p = (regnum == tdep->ppc_fpscr_regnum + || (regnum >= tdep->ppc_fp0_regnum + && regnum < tdep->ppc_fp0_regnum + 32)); + if (group == float_reggroup) + return float_p; + + vector_p = ((regnum >= tdep->ppc_vr0_regnum + && regnum < tdep->ppc_vr0_regnum + 32) + || (regnum >= tdep->ppc_ev0_regnum + && regnum < tdep->ppc_ev0_regnum + 32) + || regnum == tdep->ppc_vrsave_regnum + || regnum == tdep->ppc_acc_regnum + || regnum == tdep->ppc_spefscr_regnum); + if (group == vector_reggroup) + return vector_p; + + /* Note that PS aka MSR isn't included - it's a system register (and + besides, due to GCC's CFI foobar you do not want to restore + it). */ + general_p = ((regnum >= tdep->ppc_gp0_regnum + && regnum < tdep->ppc_gp0_regnum + 32) + || regnum == tdep->ppc_toc_regnum + || regnum == tdep->ppc_cr_regnum + || regnum == tdep->ppc_lr_regnum + || regnum == tdep->ppc_ctr_regnum + || regnum == tdep->ppc_xer_regnum + || regnum == PC_REGNUM); + if (group == general_reggroup) + return general_p; + + if (group == save_reggroup || group == restore_reggroup) + return general_p || vector_p || float_p; + + return 0; +} + /* The register format for RS/6000 floating point registers is always double, we need a conversion if the memory format is float. */ @@ -1732,10 +1929,10 @@ static void rs6000_register_to_value (struct frame_info *frame, int regnum, struct type *type, - void *to) + gdb_byte *to) { const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; - char from[MAX_REGISTER_SIZE]; + gdb_byte from[MAX_REGISTER_SIZE]; gdb_assert (reg->fpr); gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); @@ -1748,10 +1945,10 @@ static void rs6000_value_to_register (struct frame_info *frame, int regnum, struct type *type, - const void *from) + const gdb_byte *from) { const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; - char to[MAX_REGISTER_SIZE]; + gdb_byte to[MAX_REGISTER_SIZE]; gdb_assert (reg->fpr); gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); @@ -1760,55 +1957,117 @@ rs6000_value_to_register (struct frame_info *frame, put_frame_register (frame, regnum, to); } +/* Move SPE vector register values between a 64-bit buffer and the two + 32-bit raw register halves in a regcache. This function handles + both splitting a 64-bit value into two 32-bit halves, and joining + two halves into a whole 64-bit value, depending on the function + passed as the MOVE argument. + + EV_REG must be the number of an SPE evN vector register --- a + pseudoregister. REGCACHE must be a regcache, and BUFFER must be a + 64-bit buffer. + + Call MOVE once for each 32-bit half of that register, passing + REGCACHE, the number of the raw register corresponding to that + half, and the address of the appropriate half of BUFFER. + + For example, passing 'regcache_raw_read' as the MOVE function will + fill BUFFER with the full 64-bit contents of EV_REG. Or, passing + 'regcache_raw_supply' will supply the contents of BUFFER to the + appropriate pair of raw registers in REGCACHE. + + You may need to cast away some 'const' qualifiers when passing + MOVE, since this function can't tell at compile-time which of + REGCACHE or BUFFER is acting as the source of the data. If C had + co-variant type qualifiers, ... */ static void -e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, - int reg_nr, void *buffer) +e500_move_ev_register (void (*move) (struct regcache *regcache, + int regnum, gdb_byte *buf), + struct regcache *regcache, int ev_reg, + gdb_byte *buffer) { - int base_regnum; - int offset = 0; - char temp_buffer[MAX_REGISTER_SIZE]; - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + struct gdbarch *arch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (arch); + int reg_index; + gdb_byte *byte_buffer = buffer; + + gdb_assert (tdep->ppc_ev0_regnum <= ev_reg + && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); - if (reg_nr >= tdep->ppc_gp0_regnum - && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs) + reg_index = ev_reg - tdep->ppc_ev0_regnum; + + if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) + { + move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); + move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); + } + else { - base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; - - /* Build the value in the provided buffer. */ - /* Read the raw register of which this one is the lower portion. */ - regcache_raw_read (regcache, base_regnum, temp_buffer); - if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) - offset = 4; - memcpy ((char *) buffer, temp_buffer + offset, 4); + move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); + move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); } } +static void +e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, + int reg_nr, gdb_byte *buffer) +{ + struct gdbarch *regcache_arch = get_regcache_arch (regcache); + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + gdb_assert (regcache_arch == gdbarch); + + if (tdep->ppc_ev0_regnum <= reg_nr + && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) + e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); + else + internal_error (__FILE__, __LINE__, + _("e500_pseudo_register_read: " + "called on unexpected register '%s' (%d)"), + gdbarch_register_name (gdbarch, reg_nr), reg_nr); +} + static void e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, - int reg_nr, const void *buffer) + int reg_nr, const gdb_byte *buffer) { - int base_regnum; - int offset = 0; - char temp_buffer[MAX_REGISTER_SIZE]; + struct gdbarch *regcache_arch = get_regcache_arch (regcache); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - if (reg_nr >= tdep->ppc_gp0_regnum - && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs) - { - base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; - /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ - if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) - offset = 4; - - /* Let's read the value of the base register into a temporary - buffer, so that overwriting the last four bytes with the new - value of the pseudo will leave the upper 4 bytes unchanged. */ - regcache_raw_read (regcache, base_regnum, temp_buffer); - - /* Write as an 8 byte quantity. */ - memcpy (temp_buffer + offset, (char *) buffer, 4); - regcache_raw_write (regcache, base_regnum, temp_buffer); - } + gdb_assert (regcache_arch == gdbarch); + + if (tdep->ppc_ev0_regnum <= reg_nr + && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) + e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *)) + regcache_raw_write, + regcache, reg_nr, (gdb_byte *) buffer); + else + internal_error (__FILE__, __LINE__, + _("e500_pseudo_register_read: " + "called on unexpected register '%s' (%d)"), + gdbarch_register_name (gdbarch, reg_nr), reg_nr); +} + +/* The E500 needs a custom reggroup function: it has anonymous raw + registers, and default_register_reggroup_p assumes that anonymous + registers are not members of any reggroup. */ +static int +e500_register_reggroup_p (struct gdbarch *gdbarch, + int regnum, + struct reggroup *group) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + /* The save and restore register groups need to include the + upper-half registers, even though they're anonymous. */ + if ((group == save_reggroup + || group == restore_reggroup) + && (tdep->ppc_ev0_upper_regnum <= regnum + && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)) + return 1; + + /* In all other regards, the default reggroup definition is fine. */ + return default_register_reggroup_p (gdbarch, regnum, group); } /* Convert a DBX STABS register number to a GDB register number. */ @@ -1898,7 +2157,7 @@ rs6000_dwarf2_reg_to_regnum (int num) static void rs6000_store_return_value (struct type *type, struct regcache *regcache, - const void *valbuf) + const gdb_byte *valbuf) { struct gdbarch *gdbarch = get_regcache_arch (regcache); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -1920,7 +2179,9 @@ rs6000_store_return_value (struct type *type, && TYPE_VECTOR (type)) regnum = tdep->ppc_vr0_regnum + 2; else - gdb_assert (0); + internal_error (__FILE__, __LINE__, + _("rs6000_store_return_value: " + "unexpected array return type")); } else /* Everything else is returned in GPR3 and up. */ @@ -1936,7 +2197,7 @@ rs6000_store_return_value (struct type *type, register_size (gdbarch, regnum)); regcache_cooked_write_part (regcache, regnum, 0, bytes_to_write, - (char *) valbuf + bytes_written); + valbuf + bytes_written); regnum++; bytes_written += bytes_to_write; } @@ -2054,37 +2315,58 @@ rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems and 64 bits on 64-bit systems. */ -#define R(name) { STR(name), 4, 8, 0, 0 } +#define R(name) { STR(name), 4, 8, 0, 0, -1 } /* Return a struct reg defining register NAME that's 32 bits on all systems. */ -#define R4(name) { STR(name), 4, 4, 0, 0 } +#define R4(name) { STR(name), 4, 4, 0, 0, -1 } /* Return a struct reg defining register NAME that's 64 bits on all systems. */ -#define R8(name) { STR(name), 8, 8, 0, 0 } +#define R8(name) { STR(name), 8, 8, 0, 0, -1 } /* Return a struct reg defining register NAME that's 128 bits on all systems. */ -#define R16(name) { STR(name), 16, 16, 0, 0 } +#define R16(name) { STR(name), 16, 16, 0, 0, -1 } /* Return a struct reg defining floating-point register NAME. */ -#define F(name) { STR(name), 8, 8, 1, 0 } +#define F(name) { STR(name), 8, 8, 1, 0, -1 } -/* Return a struct reg defining a pseudo register NAME. */ -#define P(name) { STR(name), 4, 8, 0, 1} +/* Return a struct reg defining a pseudo register NAME that is 64 bits + long on all systems. */ +#define P8(name) { STR(name), 8, 8, 0, 1, -1 } /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems and that doesn't exist on 64-bit systems. */ -#define R32(name) { STR(name), 4, 0, 0, 0 } +#define R32(name) { STR(name), 4, 0, 0, 0, -1 } /* Return a struct reg defining register NAME that's 64 bits on 64-bit systems and that doesn't exist on 32-bit systems. */ -#define R64(name) { STR(name), 0, 8, 0, 0 } +#define R64(name) { STR(name), 0, 8, 0, 0, -1 } /* Return a struct reg placeholder for a register that doesn't exist. */ -#define R0 { 0, 0, 0, 0, 0 } +#define R0 { 0, 0, 0, 0, 0, -1 } + +/* Return a struct reg defining an anonymous raw register that's 32 + bits on all systems. */ +#define A4 { 0, 4, 4, 0, 0, -1 } +/* Return a struct reg defining an SPR named NAME that is 32 bits on + 32-bit systems and 64 bits on 64-bit systems. */ +#define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name } + +/* Return a struct reg defining an SPR named NAME that is 32 bits on + all systems. */ +#define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name } + +/* Return a struct reg defining an SPR named NAME that is 32 bits on + all systems, and whose SPR number is NUMBER. */ +#define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) } + +/* Return a struct reg defining an SPR named NAME that's 64 bits on + 64-bit systems and that doesn't exist on 32-bit systems. */ +#define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name } + /* UISA registers common across all architectures, including POWER. */ #define COMMON_UISA_REGS \ @@ -2098,24 +2380,13 @@ rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ /* 64 */ R(pc), R(ps) -#define COMMON_UISA_NOFP_REGS \ - /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ - /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ - /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ - /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ - /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ - /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ - /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ - /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ - /* 64 */ R(pc), R(ps) - /* UISA-level SPRs for PowerPC. */ #define PPC_UISA_SPRS \ - /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) + /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr) /* UISA-level SPRs for PowerPC without floating point support. */ #define PPC_UISA_NOFP_SPRS \ - /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 + /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0 /* Segment registers, for PowerPC. */ #define PPC_SEGMENT_REGS \ @@ -2126,15 +2397,15 @@ rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, /* OEA SPRs for PowerPC. */ #define PPC_OEA_SPRS \ - /* 87 */ R4(pvr), \ - /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ - /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ - /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ - /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ - /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ - /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ - /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ - /* 116 */ R4(dec), R(dabr), R4(ear) + /* 87 */ S4(pvr), \ + /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \ + /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \ + /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \ + /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \ + /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \ + /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \ + /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \ + /* 116 */ S4(dec), S(dabr), S4(ear) /* AltiVec registers. */ #define PPC_ALTIVEC_REGS \ @@ -2144,26 +2415,45 @@ rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ /*151*/R4(vscr), R4(vrsave) -/* Vectors of hi-lo general purpose registers. */ -#define PPC_EV_REGS \ - /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ - /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ - /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ - /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) -/* Lower half of the EV registers. */ -#define PPC_GPRS_PSEUDO_REGS \ - /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ - /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ - /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ - /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31) +/* On machines supporting the SPE APU, the general-purpose registers + are 64 bits long. There are SIMD vector instructions to treat them + as pairs of floats, but the rest of the instruction set treats them + as 32-bit registers, and only operates on their lower halves. + + In the GDB regcache, we treat their high and low halves as separate + registers. The low halves we present as the general-purpose + registers, and then we have pseudo-registers that stitch together + the upper and lower halves and present them as pseudo-registers. */ + +/* SPE GPR lower halves --- raw registers. */ +#define PPC_SPE_GP_REGS \ + /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \ + /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \ + /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \ + /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31) + +/* SPE GPR upper halves --- anonymous raw registers. */ +#define PPC_SPE_UPPER_GP_REGS \ + /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \ + /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \ + /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \ + /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4 + +/* SPE GPR vector registers --- pseudo registers based on underlying + gprs and the anonymous upper half raw registers. */ +#define PPC_EV_PSEUDO_REGS \ +/* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \ +/* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\ +/*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\ +/*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31) /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover user-level SPR's. */ static const struct reg registers_power[] = { COMMON_UISA_REGS, - /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), + /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq), /* 71 */ R4(fpscr) }; @@ -2176,36 +2466,49 @@ static const struct reg registers_powerpc[] = PPC_ALTIVEC_REGS }; -/* IBM PowerPC 403. */ +/* IBM PowerPC 403. + + Some notes about the "tcr" special-purpose register: + - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the + 403's programmable interval timer, fixed interval timer, and + watchdog timer. + - On the 602, SPR 984 is named "tcr", and it controls the 602's + watchdog timer, and nothing else. + + Some of the fields are similar between the two, but they're not + compatible with each other. Since the two variants have different + registers, with different numbers, but the same name, we can't + splice the register name to get the SPR number. */ static const struct reg registers_403[] = { COMMON_UISA_REGS, PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), - /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), - /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), - /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), - /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), - /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) + /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), + /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), + /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), + /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), + /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), + /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2) }; -/* IBM PowerPC 403GC. */ +/* IBM PowerPC 403GC. + See the comments about 'tcr' for the 403, above. */ static const struct reg registers_403GC[] = { COMMON_UISA_REGS, PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), - /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), - /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), - /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), - /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), - /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), - /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), - /* 147 */ R(tbhu), R(tblu) + /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), + /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), + /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), + /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), + /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), + /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2), + /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr), + /* 147 */ S(tbhu), S(tblu) }; /* Motorola PowerPC 505. */ @@ -2215,7 +2518,7 @@ static const struct reg registers_505[] = PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(eie), R(eid), R(nri) + /* 119 */ S(eie), S(eid), S(nri) }; /* Motorola PowerPC 860 or 850. */ @@ -2225,18 +2528,18 @@ static const struct reg registers_860[] = PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(eie), R(eid), R(nri), R(cmpa), - /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), - /* 127 */ R(der), R(counta), R(countb), R(cmpe), - /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), - /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), - /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), - /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), - /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), - /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), - /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), - /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), - /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) + /* 119 */ S(eie), S(eid), S(nri), S(cmpa), + /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr), + /* 127 */ S(der), S(counta), S(countb), S(cmpe), + /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1), + /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst), + /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr), + /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr), + /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc), + /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap), + /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn), + /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1), + /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1) }; /* Motorola PowerPC 601. Note that the 601 has different register numbers @@ -2248,20 +2551,21 @@ static const struct reg registers_601[] = PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), - /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) + /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), + /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl) }; -/* Motorola PowerPC 602. */ +/* Motorola PowerPC 602. + See the notes under the 403 about 'tcr'. */ static const struct reg registers_602[] = { COMMON_UISA_REGS, PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(hid0), R(hid1), R(iabr), R0, - /* 123 */ R0, R(tcr), R(ibr), R(esassr), - /* 127 */ R(sebr), R(ser), R(sp), R(lt) + /* 119 */ S(hid0), S(hid1), S(iabr), R0, + /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr), + /* 127 */ S(sebr), S(ser), S(sp), S(lt) }; /* Motorola/IBM PowerPC 603 or 603e. */ @@ -2271,9 +2575,9 @@ static const struct reg registers_603[] = PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(hid0), R(hid1), R(iabr), R0, - /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), - /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) + /* 119 */ S(hid0), S(hid1), S(iabr), R0, + /* 123 */ R0, S(dmiss), S(dcmp), S(hash1), + /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa) }; /* Motorola PowerPC 604 or 604e. */ @@ -2283,9 +2587,9 @@ static const struct reg registers_604[] = PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), - /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), - /* 127 */ R(sia), R(sda) + /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), + /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2), + /* 127 */ S(sia), S(sda) }; /* Motorola/IBM PowerPC 750 or 740. */ @@ -2295,12 +2599,12 @@ static const struct reg registers_750[] = PPC_UISA_SPRS, PPC_SEGMENT_REGS, PPC_OEA_SPRS, - /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), - /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), - /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), - /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), - /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), - /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) + /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), + /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2), + /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4), + /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia), + /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr), + /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3) }; @@ -2322,16 +2626,14 @@ static const struct reg registers_7400[] = /* Motorola e500. */ static const struct reg registers_e500[] = { - R(pc), R(ps), - /* cr, lr, ctr, xer, "" */ - PPC_UISA_NOFP_SPRS, - /* 7...38 */ - PPC_EV_REGS, - R8(acc), R(spefscr), + /* 0 .. 31 */ PPC_SPE_GP_REGS, + /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS, + /* 64 .. 65 */ R(pc), R(ps), + /* 66 .. 70 */ PPC_UISA_NOFP_SPRS, + /* 71 .. 72 */ R8(acc), S4(spefscr), /* NOTE: Add new registers here the end of the raw register list and just before the first pseudo register. */ - /* 41...72 */ - PPC_GPRS_PSEUDO_REGS + /* 73 .. 104 */ PPC_EV_PSEUDO_REGS }; /* Information about a particular processor variant. */ @@ -2695,12 +2997,12 @@ rs6000_frame_prev_register (struct frame_info *next_frame, void **this_cache, int regnum, int *optimizedp, enum lval_type *lvalp, CORE_ADDR *addrp, - int *realnump, void *valuep) + int *realnump, gdb_byte *valuep) { struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, this_cache); - trad_frame_prev_register (next_frame, info->saved_regs, regnum, - optimizedp, lvalp, addrp, realnump, valuep); + trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, + optimizedp, lvalp, addrp, realnump, valuep); } static const struct frame_unwind rs6000_frame_unwind = @@ -2752,7 +3054,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) { struct gdbarch *gdbarch; struct gdbarch_tdep *tdep; - int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; + int wordsize, from_xcoff_exec, from_elf_exec, i, off; struct reg *regs; const struct variant *v; enum bfd_architecture arch; @@ -2851,7 +3153,6 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) } gdbarch = gdbarch_alloc (&info, tdep); - power = arch == bfd_arch_rs6000; /* Initialize the number of real and pseudo registers in each variant. */ init_variants (); @@ -2864,7 +3165,6 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->regs = v->regs; tdep->ppc_gp0_regnum = 0; - tdep->ppc_gprs_pseudo_p = 0; tdep->ppc_toc_regnum = 2; tdep->ppc_ps_regnum = 65; tdep->ppc_cr_regnum = 66; @@ -2873,14 +3173,16 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->ppc_xer_regnum = 69; if (v->mach == bfd_mach_ppc_601) tdep->ppc_mq_regnum = 124; - else if (power) + else if (arch == bfd_arch_rs6000) tdep->ppc_mq_regnum = 70; else tdep->ppc_mq_regnum = -1; tdep->ppc_fp0_regnum = 32; - tdep->ppc_fpscr_regnum = power ? 71 : 70; + tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70; + tdep->ppc_sr0_regnum = 71; tdep->ppc_vr0_regnum = -1; tdep->ppc_vrsave_regnum = -1; + tdep->ppc_ev0_upper_regnum = -1; tdep->ppc_ev0_regnum = -1; tdep->ppc_ev31_regnum = -1; tdep->ppc_acc_regnum = -1; @@ -2889,6 +3191,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_pc_regnum (gdbarch, 64); set_gdbarch_sp_regnum (gdbarch, 1); set_gdbarch_deprecated_fp_regnum (gdbarch, 1); + set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); if (sysv_abi && wordsize == 8) set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); else if (sysv_abi && wordsize == 4) @@ -2907,10 +3210,13 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) else tdep->lr_frame_offset = 8; - if (v->arch == bfd_arch_powerpc) + if (v->arch == bfd_arch_rs6000) + tdep->ppc_sr0_regnum = -1; + else if (v->arch == bfd_arch_powerpc) switch (v->mach) { case bfd_mach_ppc: + tdep->ppc_sr0_regnum = -1; tdep->ppc_vr0_regnum = 71; tdep->ppc_vrsave_regnum = 104; break; @@ -2919,33 +3225,40 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->ppc_vrsave_regnum = 152; break; case bfd_mach_ppc_e500: - tdep->ppc_gp0_regnum = 41; - tdep->ppc_gprs_pseudo_p = 1; tdep->ppc_toc_regnum = -1; - tdep->ppc_ps_regnum = 1; - tdep->ppc_cr_regnum = 2; - tdep->ppc_lr_regnum = 3; - tdep->ppc_ctr_regnum = 4; - tdep->ppc_xer_regnum = 5; - tdep->ppc_ev0_regnum = 7; - tdep->ppc_ev31_regnum = 38; + tdep->ppc_ev0_upper_regnum = 32; + tdep->ppc_ev0_regnum = 73; + tdep->ppc_ev31_regnum = 104; + tdep->ppc_acc_regnum = 71; + tdep->ppc_spefscr_regnum = 72; tdep->ppc_fp0_regnum = -1; tdep->ppc_fpscr_regnum = -1; - tdep->ppc_acc_regnum = 39; - tdep->ppc_spefscr_regnum = 40; - set_gdbarch_pc_regnum (gdbarch, 0); - set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); - set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); + tdep->ppc_sr0_regnum = -1; set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); + set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p); break; + + case bfd_mach_ppc64: + case bfd_mach_ppc_620: + case bfd_mach_ppc_630: + case bfd_mach_ppc_a35: + case bfd_mach_ppc_rs64ii: + case bfd_mach_ppc_rs64iii: + /* These processor's register sets don't have segment registers. */ + tdep->ppc_sr0_regnum = -1; + break; } + else + internal_error (__FILE__, __LINE__, + _("rs6000_gdbarch_init: " + "received unexpected BFD 'arch' value")); /* Sanity check on registers. */ gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); /* Select instruction printer. */ - if (arch == power) + if (arch == bfd_arch_rs6000) set_gdbarch_print_insn (gdbarch, print_insn_rs6000); else set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); @@ -2956,6 +3269,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); set_gdbarch_register_name (gdbarch, rs6000_register_name); set_gdbarch_register_type (gdbarch, rs6000_register_type); + set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p); set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); @@ -3066,6 +3380,8 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); } + init_sim_regno_table (gdbarch); + return gdbarch; } @@ -3100,6 +3416,6 @@ _initialize_rs6000_tdep (void) /* Add root prefix command for "info powerpc" commands */ add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, - "Various POWERPC info specific commands.", + _("Various POWERPC info specific commands."), &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); }