X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fxtensa-tdep.h;h=b99f8c9df2166876cebe5c4106ff22511db86544;hb=3061113bf336048d538241282c39baf684de31bf;hp=5b28cab417ea02d5ea51b3ff372cafb092a4b9c1;hpb=40045d91812b25c88c8275b8c08d27c234b68ba8;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/xtensa-tdep.h b/gdb/xtensa-tdep.h index 5b28cab417..b99f8c9df2 100644 --- a/gdb/xtensa-tdep.h +++ b/gdb/xtensa-tdep.h @@ -1,6 +1,6 @@ /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2020 Free Software Foundation, Inc. This file is part of GDB. @@ -17,6 +17,8 @@ You should have received a copy of the GNU General Public License along with this program. If not, see . */ +#ifndef XTENSA_TDEP_H +#define XTENSA_TDEP_H #include "arch/xtensa.h" @@ -103,7 +105,7 @@ typedef struct typedef struct { - char* name; /* Register name. */ + const char *name; /* Register name. */ int offset; /* Offset. */ xtensa_register_type_t type; /* Register type. */ xtensa_register_group_t group;/* Register group. */ @@ -124,9 +126,13 @@ typedef struct /* For xtensa-config.c to expand to the structure above. */ #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \ - {#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \ + {#name, ofs, (xtensa_register_type_t) (ty), \ + ((xtensa_register_group_t) \ + ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2)))), \ ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto}, -#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0}, +#define XTREG_END \ + {0, 0, (xtensa_register_type_t) 0, (xtensa_register_group_t) 0, \ + 0, 0, 0, 0, (unsigned) -1, 0, 0, 0, 0, 0}, #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002 @@ -200,6 +206,7 @@ struct gdbarch_tdep int lcount_regnum; int sar_regnum; /* Register number of SAR. */ int litbase_regnum; /* Register number of LITBASE. */ + int threadptr_regnum; /* Register number of THREADPTR. */ int interrupt_regnum; /* Register number for interrupt. */ int interrupt2_regnum; /* Register number for interrupt2. */ @@ -220,53 +227,55 @@ struct gdbarch_tdep /* Macro to instantiate a gdbarch_tdep structure. */ -#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \ - { \ - .target_flags = 0, \ - .spill_location = -1, \ - .spill_size = (spillsz), \ - .unused = 0, \ - .call_abi = CallAbiDefault, \ - .debug_interrupt_level = XCHAL_DEBUGLEVEL, \ - .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \ - .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ - .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \ - .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \ - .isa_use_density_instructions = XCHAL_HAVE_DENSITY, \ - .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \ - .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \ - .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \ - .debug_num_ibreaks = XCHAL_NUM_IBREAK, \ - .debug_num_dbreaks = XCHAL_NUM_DBREAK, \ - .regmap = rmap, \ - .num_regs = 0, \ - .num_nopriv_regs = 0, \ - .num_pseudo_regs = 0, \ - .num_aregs = XCHAL_NUM_AREGS, \ - .num_contexts = XCHAL_NUM_CONTEXTS, \ - .ar_base = -1, \ - .a0_base = -1, \ - .wb_regnum = -1, \ - .ws_regnum = -1, \ - .pc_regnum = -1, \ - .ps_regnum = -1, \ - .lbeg_regnum = -1, \ - .lend_regnum = -1, \ - .lcount_regnum = -1, \ - .sar_regnum = -1, \ - .litbase_regnum = -1, \ - .interrupt_regnum = -1, \ - .interrupt2_regnum = -1, \ - .cpenable_regnum = -1, \ - .debugcause_regnum = -1, \ - .exccause_regnum = -1, \ - .excvaddr_regnum = -1, \ - .max_register_raw_size = 0, \ - .max_register_virtual_size = 0, \ - .fp_layout = 0, \ - .fp_layout_bytes = 0, \ - .gregmap = 0, \ - } +#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \ + { \ + 0, /* target_flags */ \ + (unsigned) -1, /* spill_location */ \ + (spillsz), /* spill_size */ \ + 0, /* unused */ \ + (XSHAL_ABI == XTHAL_ABI_CALL0 \ + ? CallAbiCall0Only \ + : CallAbiDefault), /* call_abi */ \ + XCHAL_DEBUGLEVEL, /* debug_interrupt_level */ \ + XCHAL_ICACHE_LINESIZE, /* icache_line_bytes */ \ + XCHAL_DCACHE_LINESIZE, /* dcache_line_bytes */ \ + XCHAL_DCACHE_IS_WRITEBACK, /* dcache_writeback */ \ + (XSHAL_ABI != XTHAL_ABI_CALL0), /* isa_use_windowed_registers */ \ + XCHAL_HAVE_DENSITY, /* isa_use_density_instructions */ \ + XCHAL_HAVE_EXCEPTIONS, /* isa_use_exceptions */ \ + XSHAL_USE_ABSOLUTE_LITERALS, /* isa_use_ext_l32r */ \ + XCHAL_MAX_INSTRUCTION_SIZE, /* isa_max_insn_size */ \ + XCHAL_NUM_IBREAK, /* debug_num_ibreaks */ \ + XCHAL_NUM_DBREAK, /* debug_num_dbreaks */ \ + rmap, /* regmap */ \ + 0, /* num_regs */ \ + 0, /* num_nopriv_regs */ \ + 0, /* num_pseudo_regs */ \ + XCHAL_NUM_AREGS, /* num_aregs */ \ + XCHAL_NUM_CONTEXTS, /* num_contexts */ \ + -1, /* ar_base */ \ + -1, /* a0_base */ \ + -1, /* wb_regnum */ \ + -1, /* ws_regnum */ \ + -1, /* pc_regnum */ \ + -1, /* ps_regnum */ \ + -1, /* lbeg_regnum */ \ + -1, /* lend_regnum */ \ + -1, /* lcount_regnum */ \ + -1, /* sar_regnum */ \ + -1, /* litbase_regnum */ \ + -1, /* interrupt_regnum */ \ + -1, /* interrupt2_regnum */ \ + -1, /* cpenable_regnum */ \ + -1, /* debugcause_regnum */ \ + -1, /* exccause_regnum */ \ + -1, /* excvaddr_regnum */ \ + 0, /* max_register_raw_size */ \ + 0, /* max_register_virtual_size */ \ + 0, /* fp_layout */ \ + 0, /* fp_layout_bytes */ \ + 0, /* gregmap */ \ + } #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \ struct gdbarch_tdep xtensa_tdep = \ XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size); @@ -284,3 +293,4 @@ struct gdbarch_tdep data structure to their corresponding register in the AR register file (see xtensa-tdep.c). */ +#endif /* XTENSA_TDEP_H */