X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fxtensa-tdep.h;h=b99f8c9df2166876cebe5c4106ff22511db86544;hb=aa1f7fb133a5a4f95af8286f58b689d6ae131488;hp=49afff67bd9bb4cba82b7fd8f3eb01349ef03280;hpb=df4df182b49ab6808495f557d3727b8dfd4b98da;p=deliverable%2Fbinutils-gdb.git
diff --git a/gdb/xtensa-tdep.h b/gdb/xtensa-tdep.h
index 49afff67bd..b99f8c9df2 100644
--- a/gdb/xtensa-tdep.h
+++ b/gdb/xtensa-tdep.h
@@ -1,7 +1,6 @@
/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
- Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009
- Free Software Foundation, Inc.
+ Copyright (C) 2003-2020 Free Software Foundation, Inc.
This file is part of GDB.
@@ -18,6 +17,10 @@
You should have received a copy of the GNU General Public License
along with this program. If not, see . */
+#ifndef XTENSA_TDEP_H
+#define XTENSA_TDEP_H
+
+#include "arch/xtensa.h"
/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
whenever the "tdep" structure changes in an incompatible way. */
@@ -43,7 +46,7 @@ typedef enum
/* Xtensa register group. */
-#define XTENSA_MAX_COPROCESSOR 0x08 /* Number of Xtensa coprocessors. */
+#define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */
typedef enum
{
@@ -82,28 +85,6 @@ typedef enum
} xtensa_target_flags_t;
-/* Xtensa ELF core file register set representation ('.reg' section).
- Copied from target-side ELF header . */
-
-typedef unsigned long xtensa_elf_greg_t;
-
-typedef struct
-{
- xtensa_elf_greg_t pc;
- xtensa_elf_greg_t ps;
- xtensa_elf_greg_t lbeg;
- xtensa_elf_greg_t lend;
- xtensa_elf_greg_t lcount;
- xtensa_elf_greg_t sar;
- xtensa_elf_greg_t windowstart;
- xtensa_elf_greg_t windowbase;
- xtensa_elf_greg_t reserved[8+48];
- xtensa_elf_greg_t ar[64];
-} xtensa_elf_gregset_t;
-
-#define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
- / sizeof (xtensa_elf_greg_t))
-
/* Mask. */
typedef struct
@@ -124,7 +105,7 @@ typedef struct
typedef struct
{
- char* name; /* Register name. */
+ const char *name; /* Register name. */
int offset; /* Offset. */
xtensa_register_type_t type; /* Register type. */
xtensa_register_group_t group;/* Register group. */
@@ -145,9 +126,13 @@ typedef struct
/* For xtensa-config.c to expand to the structure above. */
#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
- {#name, ofs, ty, ((gr)|((xtRegisterGroupNCP>>2)<<(cp+2))), \
+ {#name, ofs, (xtensa_register_type_t) (ty), \
+ ((xtensa_register_group_t) \
+ ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2)))), \
ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
-#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
+#define XTREG_END \
+ {0, 0, (xtensa_register_type_t) 0, (xtensa_register_group_t) 0, \
+ 0, 0, 0, 0, (unsigned) -1, 0, 0, 0, 0, 0},
#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
@@ -163,6 +148,13 @@ typedef enum
} call_abi_t;
+struct ctype_cache
+{
+ struct ctype_cache *next;
+ int size;
+ struct type *virtual_type;
+};
+
/* Xtensa-specific target dependencies. */
struct gdbarch_tdep
@@ -214,6 +206,7 @@ struct gdbarch_tdep
int lcount_regnum;
int sar_regnum; /* Register number of SAR. */
int litbase_regnum; /* Register number of LITBASE. */
+ int threadptr_regnum; /* Register number of THREADPTR. */
int interrupt_regnum; /* Register number for interrupt. */
int interrupt2_regnum; /* Register number for interrupt2. */
@@ -229,63 +222,60 @@ struct gdbarch_tdep
unsigned long *gregmap;
/* Cached register types. */
- struct ctype_cache
- {
- struct ctype_cache *next;
- int size;
- struct type *virtual_type;
- } *type_entries;
+ struct ctype_cache *type_entries;
};
/* Macro to instantiate a gdbarch_tdep structure. */
-#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \
- { \
- .target_flags = 0, \
- .spill_location = -1, \
- .spill_size = (spillsz), \
- .unused = 0, \
- .call_abi = 0, \
- .debug_interrupt_level = XCHAL_DEBUGLEVEL, \
- .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \
- .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
- .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \
- .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \
- .isa_use_density_instructions = XCHAL_HAVE_DENSITY, \
- .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \
- .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \
- .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
- .debug_num_ibreaks = XCHAL_NUM_IBREAK, \
- .debug_num_dbreaks = XCHAL_NUM_DBREAK, \
- .regmap = rmap, \
- .num_regs = 0, \
- .num_nopriv_regs = 0, \
- .num_pseudo_regs = 0, \
- .num_aregs = XCHAL_NUM_AREGS, \
- .num_contexts = XCHAL_NUM_CONTEXTS, \
- .ar_base = -1, \
- .a0_base = -1, \
- .wb_regnum = -1, \
- .ws_regnum = -1, \
- .pc_regnum = -1, \
- .ps_regnum = -1, \
- .lbeg_regnum = -1, \
- .lend_regnum = -1, \
- .lcount_regnum = -1, \
- .sar_regnum = -1, \
- .litbase_regnum = -1, \
- .interrupt_regnum = -1, \
- .interrupt2_regnum = -1, \
- .cpenable_regnum = -1, \
- .debugcause_regnum = -1, \
- .exccause_regnum = -1, \
- .excvaddr_regnum = -1, \
- .max_register_raw_size = 0, \
- .max_register_virtual_size = 0, \
- .fp_layout = 0, \
- .fp_layout_bytes = 0, \
- .gregmap = 0, \
- }
+#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \
+ { \
+ 0, /* target_flags */ \
+ (unsigned) -1, /* spill_location */ \
+ (spillsz), /* spill_size */ \
+ 0, /* unused */ \
+ (XSHAL_ABI == XTHAL_ABI_CALL0 \
+ ? CallAbiCall0Only \
+ : CallAbiDefault), /* call_abi */ \
+ XCHAL_DEBUGLEVEL, /* debug_interrupt_level */ \
+ XCHAL_ICACHE_LINESIZE, /* icache_line_bytes */ \
+ XCHAL_DCACHE_LINESIZE, /* dcache_line_bytes */ \
+ XCHAL_DCACHE_IS_WRITEBACK, /* dcache_writeback */ \
+ (XSHAL_ABI != XTHAL_ABI_CALL0), /* isa_use_windowed_registers */ \
+ XCHAL_HAVE_DENSITY, /* isa_use_density_instructions */ \
+ XCHAL_HAVE_EXCEPTIONS, /* isa_use_exceptions */ \
+ XSHAL_USE_ABSOLUTE_LITERALS, /* isa_use_ext_l32r */ \
+ XCHAL_MAX_INSTRUCTION_SIZE, /* isa_max_insn_size */ \
+ XCHAL_NUM_IBREAK, /* debug_num_ibreaks */ \
+ XCHAL_NUM_DBREAK, /* debug_num_dbreaks */ \
+ rmap, /* regmap */ \
+ 0, /* num_regs */ \
+ 0, /* num_nopriv_regs */ \
+ 0, /* num_pseudo_regs */ \
+ XCHAL_NUM_AREGS, /* num_aregs */ \
+ XCHAL_NUM_CONTEXTS, /* num_contexts */ \
+ -1, /* ar_base */ \
+ -1, /* a0_base */ \
+ -1, /* wb_regnum */ \
+ -1, /* ws_regnum */ \
+ -1, /* pc_regnum */ \
+ -1, /* ps_regnum */ \
+ -1, /* lbeg_regnum */ \
+ -1, /* lend_regnum */ \
+ -1, /* lcount_regnum */ \
+ -1, /* sar_regnum */ \
+ -1, /* litbase_regnum */ \
+ -1, /* interrupt_regnum */ \
+ -1, /* interrupt2_regnum */ \
+ -1, /* cpenable_regnum */ \
+ -1, /* debugcause_regnum */ \
+ -1, /* exccause_regnum */ \
+ -1, /* excvaddr_regnum */ \
+ 0, /* max_register_raw_size */ \
+ 0, /* max_register_virtual_size */ \
+ 0, /* fp_layout */ \
+ 0, /* fp_layout_bytes */ \
+ 0, /* gregmap */ \
+ }
#define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \
struct gdbarch_tdep xtensa_tdep = \
XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
@@ -303,3 +293,4 @@ struct gdbarch_tdep
data structure to their corresponding register in the AR register
file (see xtensa-tdep.c). */
+#endif /* XTENSA_TDEP_H */