X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=36c5af2739975842d5527c1ddc2634e71d513f3e;hb=bde90be2cddc06371ee80a258bf6855d0f346324;hp=9f3253165c8c084d68eeef13f4078d862bc4b880;hpb=f24ff6e9b5adc7983c3ad7cf28375eb49921b3ed;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9f3253165c..36c5af2739 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,63 @@
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
+	* aarch64-dis.c (print_operands): Refactor to take notes.
+	(print_verifier_notes): New.
+	(print_aarch64_insn): Apply constraint verifier.
+	(print_insn_aarch64_word): Update call to print_aarch64_insn.
+	* aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* aarch64-opc.c (init_insn_block): New.
+	(verify_constraints, aarch64_is_destructive_by_operands): New.
+	* aarch64-opc.h (verify_constraints): New.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
+	* aarch64-opc.c (verify_ldpsw): Update arguments.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
+	(aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
+	* aarch64-dis.c (insn_sequence): New.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
+	_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
+	_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
+	V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
+	constraints.
+	(_SVE_INSNC): New.
+	(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
+	constraints.
+	(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
+	F_SCAN flags.
+	(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
+	sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
+	sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
+	sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
+	uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
+	uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
+	C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
+
+2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
+
+	* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
+
+2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
+	are used when extracting signed fields and converting them to
+	potentially 64-bit types.
+
 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 
 	* Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.