X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=7def411b049027dcda330f6415480a994d23b9ba;hb=d20dee9efad3c23c9098f03ac785037572258483;hp=da38824cf511101ea0e38cc1307d987b7aef9bc1;hpb=b8891f8d622a31306062065813fc278d8a94fe21;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index da38824cf5..7def411b04 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,363 @@ +2018-09-14 H.J. Lu + + PR binutils/23655 + * i386-dis-evex.h (evex_table): Replace Eq with Edqa for + vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. + * i386-dis.c (Edqa): New. + (dqa_mode): Likewise. + (intel_operand_size): Handle dqa_mode as m_mode. + (OP_E_register): Handle dqa_mode as dq_mode. + (OP_E_memory): Set shift for dqa_mode based on address_mode. + +2018-09-14 H.J. Lu + + * i386-dis.c (OP_E_memory): Reformat. + +2018-09-14 Jan Beulich + + * i386-opc.tbl (crc32): Fold byte and word forms. + * i386-tbl.h: Re-generate. + +2018-09-13 H.J. Lu + + * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd, + pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd. + Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and + vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq. + * i386-tbl.h: Regenerated. + +2018-09-13 Jan Beulich + + * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where + meaningless. + (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors, + xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq, + rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and + AVX512_4VNNIW insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SHA insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AVX insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from GNFI insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where + meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64. + (vpbroadcastw, rdpid): Drop NoRex64. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl (vmovsd, vmovss): Fold register form load and + store templates, adding D. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd, + movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps, + movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd, + vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32, + vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups): + Fold load and store templates where possible, adding D. Drop + IgnoreSize where it was pointlessly present. Drop redundant + *word. + * i386-tbl.h: Re-generate. + +2018-09-13 Jan Beulich + + * i386-dis.c (Mv_bnd, v_bndmk_mode): New. + (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk. + (intel_operand_size): Handle v_bndmk_mode. + (OP_E_memory): Likewise. Produce (bad) when also riprel. + +2018-09-08 John Darrington + + * disassemble.c (ARCH_s12z): Define if ARCH_all. + +2018-08-31 Kito Cheng + + * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for + compressed floating point instructions. + +2018-08-30 Kito Cheng + + * riscv-dis.c (riscv_disassemble_insn): Check XLEN by + riscv_opcode.xlen_requirement. + * riscv-opc.c (riscv_opcodes): Update for struct change. + +2018-08-29 Martin Aberg + + * sparc-opc.c (sparc_opcodes): Add Leon specific partial write + psr (PWRPSR) instruction. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add gs264e descriptors. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add gs464e descriptors. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep + loongson3a as an alias of gs464 for compatibility. + * mips-opc.c (mips_opcodes): Change Comments. + +2018-08-29 Chenghua Xu + + * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext + option. + (print_mips_disassembler_options): Document -M loongson-ext. + * mips-opc.c (LEXT2): New macro. + (mips_opcodes): Add cto, ctz, dcto, dctz instructions. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add EXT to loongson3a + descriptors. + (parse_mips_ase_option): Handle -M loongson-ext option. + (print_mips_disassembler_options): Document -M loongson-ext. + * mips-opc.c (IL3A): Delete. + * mips-opc.c (LEXT): New macro. + (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT + instructions. + +2018-08-29 Chenghua Xu + + * mips-dis.c (mips_arch_choices): Add CAM to loongson3a + descriptors. + (parse_mips_ase_option): Handle -M loongson-cam option. + (print_mips_disassembler_options): Document -M loongson-cam. + * mips-opc.c (LCAM): New macro. + (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM + instructions. + +2018-08-21 Alan Modra + + * ppc-dis.c (operand_value_powerpc): Init "invalid". + (skip_optional_operands): Count optional operands, and update + ppc_optional_operand_value call. + * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg. + (extract_vlensi): Likewise. + (extract_fxm): Return default value for missing optional operand. + (extract_ls, extract_raq, extract_tbr): Likewise. + (insert_sxl, extract_sxl): New functions. + (insert_esync, extract_esync): Remove Power9 handling and simplify. + (powerpc_operands ): Delete PPC_OPERAND_OPTIONAL_VALUE + flag and extra entry. + (powerpc_operands ): Likewise, and use insert_sxl and + extract_sxl. + +2018-08-20 Alan Modra + + * sh-opc.h (MASK): Simplify. + +2018-08-18 John Darrington + + * s12z-dis.c (bm_decode): Deal with cases where the mode is + BM_RESERVED0 or BM_RESERVED1 + (bm_rel_decode, bm_n_bytes): Ditto. + +2018-08-18 John Darrington + + * s12z.h: Delete. + +2018-08-14 H.J. Lu + + * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for + address with the addr32 prefix and without base nor index + registers. + +2018-08-11 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to + CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS, + CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS. + (cpu_flags): Add CpuCMOV and CpuFXSR. + * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64, + fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2018-08-06 Claudiu Zissulescu + + * arc-regs.h: Update auxiliary registers. + +2018-08-06 Jan Beulich + + * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines. + (RegIP, RegIZ): Define. + * i386-reg.tbl: Adjust comments. + (rip): Use Qword instead of BaseIndex. Use RegIP. + (eip): Use Dword instead of BaseIndex. Use RegIP. + (riz): Add Qword. Use RegIZ. + (eiz): Add Dword. Use RegIZ. + * i386-tbl.h: Re-generate. + +2018-08-03 Jan Beulich + + * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw, + pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw, + vpmovzxdq, vpmovzxwd): Remove NoRex64. + * i386-tbl.h: Re-generate. + +2018-08-03 Jan Beulich + + * i386-gen.c (operand_types): Remove Mem field. + * i386-opc.h (union i386_operand_type): Remove mem field. + * i386-init.h, i386-tbl.h: Re-generate. + +2018-08-01 Alan Modra + + * po/POTFILES.in: Regenerate. + +2018-07-31 Nick Clifton + + * po/sv.po: Updated Swedish translation. + +2018-07-31 Jan Beulich + + * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize. + * i386-init.h, i386-tbl.h: Re-generate. + +2018-07-31 Jan Beulich + + * i386-opc.h (ZEROING_MASKING) Rename to ... + (DYNAMIC_MASKING): ... this. Adjust comment. + * i386-opc.tbl (MaskingMorZ): Define. + (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4, + vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4, + vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps, + vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64, + vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd, + vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw, + vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb, + vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw, + vpmovuswb, vpmovwb): Fold AVX512 register and memory forms. + +2018-07-31 Jan Beulich + + * i386-opc.tbl: Use element rather than vector size for AVX512* + scatter/gather insns. + * i386-tbl.h: Re-generate. + +2018-07-31 Jan Beulich + + * i386-gen.c (cpu_flag_init): Drop CpuVREX uses. + (cpu_flags): Drop CpuVREX. + * i386-opc.h (CpuVREX): Delete. + (union i386_cpu_flags): Remove cpuvrex. + * i386-init.h, i386-tbl.h: Re-generate. + +2018-07-30 Jim Wilson + + * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size + fields. + * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns. + 2018-07-30 Andrew Jenner * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.