X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=809cad3117c51611ddee343ce2acc71411a614e5;hb=793a194839bc8add71fdc7429c58b10f0667a6f6;hp=b8c1586ae444d8efb522619b9aa9a0feb1d0ceeb;hpb=b55f3386e45d8ba4af1a70f0684bc0089060d600;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b8c1586ae4..809cad3117 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,315 @@ +2017-11-09 Tamar Christina + + * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers; + dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2, + cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2, + sder32_el2, vncr_el2. + (aarch64_sys_reg_supported_p): Likewise. + (aarch64_pstatefields): Add dit register. + (aarch64_pstatefield_supported_p): Likewise. + (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os, + vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os, + vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1, + rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os, + rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1, + ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os, + rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os. + +2017-11-09 Tamar Christina + + * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New. + (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New. + (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New. + (QL_STLW, QL_STLX): New. + +2017-11-09 Tamar Christina + + * aarch64-asm.h (ins_addr_offset): New. + * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3. + (aarch64_ins_addr_offset): New. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis.h (ext_addr_offset): New. + * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3. + (aarch64_ext_addr_offset): New. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2, + FLD_imm4_2 and FLD_SM3_imm2. + * aarch64-opc.c (fields): Add FLD_imm6_2, + FLD_imm4_2 and FLD_SM3_imm2. + (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET. + (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2, + AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET. + * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New. + * aarch64-tbl.h + (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2. + +2017-11-09 Tamar Christina + + * aarch64-tbl.h + (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New. + (aarch64_feature_sm4, aarch64_feature_sha3): New. + (aarch64_feature_fp_16_v8_2): New. + (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New. + (V8_4_INSN, CRYPTO_V8_2_INSN): New. + (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New. + +2017-11-08 Tamar Christina + + * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2. + (aarch64_feature_sha2, aarch64_feature_aes): New. + (SHA2, AES): New. + (AES_INSN, SHA2_INSN): New. + (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS. + (sha1h, sha1su1, sha256su0, sha1c, sha1p, + sha1m, sha1su0, sha256h, sha256h2, sha256su1): + Change to SHA2_INS. + +2017-11-08 Jiong Wang + Tamar Christina + + * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new + FP16 instructions, including vfmal.f16 and vfmsl.f16. + +2017-11-07 Andrew Burgess + + * arc-nps400-tbl.h: Change incorrect use of NONE to MISC. + +2017-11-07 Alan Modra + + * opintl.h: Formatting, comment fixes. + (gettext, ngettext): Redefine when ENABLE_NLS. + (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS. + (_): Define using gettext. + (textdomain, bindtextdomain): Use safer "do nothing". + +2017-11-03 Claudiu Zissulescu + + * arc-dis.c (print_hex): New variable. + (parse_option): Check for hex option. + (print_insn_arc): Use hexadecimal representation for short + immediate values when requested. + (print_arc_disassembler_options): Add hex option to the list. + +2017-11-03 Claudiu Zissulescu + + * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc) + (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr) + (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf) + (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm) + (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf) + (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl) + (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr) + (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf) + (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64) + (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath) + (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h) + (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h) + (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h) + (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf) + (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr) + (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h) + (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl) + (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b) + (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h): + Changed opcodes. + (prealloc, prefetch*): Place them before ld instruction. + * arc-opc.c (skip_this_opcode): Add ARITH class. + +2017-10-25 Alan Modra + + PR 22348 + * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static. + (cr16_words, cr16_allWords, processing_argument_number): Likewise. + (imm4flag, size_changed): Likewise. + * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise. + (words, allWords, processing_argument_number): Likewise. + (cst4flag, size_changed): Likewise. + * crx-opc.c (crx_cst4_map): Rename from cst4_map. + (crx_cst4_maps): Rename from cst4_maps. + (crx_no_op_insn): Rename from no_op_insn. + +2017-10-24 Andrew Waterman + + * riscv-opc.c (match_c_addi16sp) : New function. + (match_c_addi4spn): New function. + (match_c_lui): Don't allow 0-immediate encodings. + (riscv_opcodes) : Use the above functions. + : Likewise. + : Likewise. + : Likewise. + +2017-10-23 Igor Tsimbalist + + * i386-init.h: Regenerate + * i386-tbl.h: Likewise + +2017-10-23 Igor Tsimbalist + + * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. + (enum): Add EVEX_W_0F3854_P_2. + * i386-dis-evex.h (evex_table): Updated. + * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, + CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. + (cpu_flags): Add CpuAVX512_BITALG. + * i386-opc.h (enum): Add CpuAVX512_BITALG. + (i386_cpu_flags): Add cpuavx512_bitalg.. + * i386-opc.tbl: Add Intel AVX512_BITALG instructions. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2017-10-23 Igor Tsimbalist + + * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851. + * i386-dis-evex.h (evex_table): Updated. + * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI, + CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS. + (cpu_flags): Add CpuAVX512_VNNI. + * i386-opc.h (enum): Add CpuAVX512_VNNI. + (i386_cpu_flags): Add cpuavx512_vnni. + * i386-opc.tbl Add Intel AVX512_VNNI instructions. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2017-10-23 Igor Tsimbalist + + * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44. + (enum): Remove VEX_LEN_0F3A44_P_2. + (vex_len_table): Ditto. + (enum): Remove VEX_W_0F3A44_P_2. + (vew_w_table): Ditto. + (prefix_table): Adjust instructions (see prefixes above). + * i386-dis-evex.h (evex_table): + Add new instructions (see prefixes above). + * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ. + (bitfield_cpu_flags): Ditto. + * i386-opc.h (enum): Ditto. + (i386_cpu_flags): Ditto. + (CpuUnused): Comment out to avoid zero-width field problem. + * i386-opc.tbl (vpclmulqdq): New instruction. + * i386-init.h: Regenerate. + * i386-tbl.h: Ditto. + +2017-10-23 Igor Tsimbalist + + * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, + PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF. + (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2, + VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2. + (vex_len_table): Ditto. + (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2, + VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2. + (vew_w_table): Ditto. + (prefix_table): Adjust instructions (see prefixes above). + * i386-dis-evex.h (evex_table): + Add new instructions (see prefixes above). + * i386-gen.c (cpu_flag_init): Add VAES. + (bitfield_cpu_flags): Ditto. + * i386-opc.h (enum): Ditto. + (i386_cpu_flags): Ditto. + * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions. + * i386-init.h: Regenerate. + * i386-tbl.h: Ditto. + +2017-10-23 Igor Tsimbalist + + * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF, + PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, + PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF. + (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, + EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2. + (prefix_table): Updated (see prefixes above). + (three_byte_table): Likewise. + (vex_w_table): Likewise. + * i386-dis-evex.h: Likewise. + * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI. + (cpu_flags): Add CpuGFNI. + * i386-opc.h (enum): Add CpuGFNI. + (i386_cpu_flags): Add cpugfni. + * i386-opc.tbl: Add Intel GFNI instructions. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2017-10-23 Igor Tsimbalist + + * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode. + Define EXbScalar and EXwScalar for OP_EX. + (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, + PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, + PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71, + PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73. + (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, + EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2, + EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2, + EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2. + (intel_operand_size): Handle b_scalar_mode and w_scalar_mode. + (OP_E_memory): Likewise. + * i386-dis-evex.h: Updated. + * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2, + CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS. + (cpu_flags): Add CpuAVX512_VBMI2. + * i386-opc.h (enum): Add CpuAVX512_VBMI2. + (i386_cpu_flags): Add cpuavx512_vbmi2. + * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions. + * i386-init.h: Regenerate. + * i386-tbl.h: Likewise. + +2017-10-18 Eric Botcazou + + * visium-dis.c (disassem_class1) : Print the operands. + +2017-10-12 James Bowman + + * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15. + * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with + K15. Add jmpix pattern. + +2017-10-09 Andreas Krebbel + + * s390-opc.txt (prno, tpei, irbm): New instructions added. + +2017-10-09 Heiko Carstens + + * s390-opc.c (INSTR_SI_RD): New macro. + (INSTR_S_RD): Adjust example instruction. + * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to + SI_RD. + +2017-10-01 Alexander Fedotov + + * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw, + e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for + VLE multimple load/store instructions. Old e_ldm* variants are + kept as aliases. + Add missing e_lmvmcsrrw and e_stmvmcsrrw. + +2017-09-27 Nick Clifton + + PR 22179 + * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new + names for the fmv.x.s and fmv.s.x instructions respectively. + +2017-09-26 do + + PR 22123 + * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to + be used on CPUs that have emacs support. + +2017-09-21 Sergio Durigan Junior + + * aarch64-opc.c (expand_fp_imm): Initialize 'imm'. + +2017-09-09 Kamil Rytarowski + + * nds32-asm.c: Rename __BIT() to N32_BIT(). + * nds32-asm.h: Likewise. + * nds32-dis.c: Likewise. + +2017-09-09 H.J. Lu + + * i386-dis.c (last_active_prefix): Removed. + (ckprefix): Don't set last_active_prefix. + (NOTRACK_Fixup): Don't check last_active_prefix. + 2017-08-31 Nick Clifton * po/fr.po: Updated French translation.