X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=8676f5f3b525a2fde3d898a848628f8a77db224f;hb=2d5d5a8f0a8b5a03454bf168b7fa7024bb1ebbd8;hp=444ab05d1da67c629d0c67029ee55d64bc189b38;hpb=fd71a3756e2dd1eae116d77dc5ec58391c4840d8;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 444ab05d1d..8676f5f3b5 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,206 @@ +2018-12-18 Alan Modra + + * arm-dis.c: Include bfd.h. + * aarch64-opc.c: Include bfd_stdint.h rather than stdint.h. + * csky-dis.c: Likewise. + * nds32-asm.c: Likewise. + * riscv-dis.c: Likewise. + * s12z-dis.c: Likewise. + * wasm32-dis.c: Likewise. + +2018-12-07 Jim Wilson + + PR gas/23956 + * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg. + +2018-12-06 Andrew Burgess + + * configure.ac (enable-cgen-maint): Support passing path to cgen + source tree. + * configure: Regenerate. + +2018-12-06 Andrew Burgess + + * disassembler.c (disassemble_init_for_target): Add RISC-V + initialisation. + * riscv-dis.c (riscv_symbol_is_valid): New function. + +2018-12-03 Kito Cheng + + * riscv-opc.c: Change the type of xlen, because type of + xlen_requirement changed. + +2018-12-03 Egeyar Bagcioglu + + PR 23193 + PR 19721 + * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR + encoding as MOV if the shift operation is a left shift of zero. + +2018-11-29 Jim Wilson + + * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS. + (c.unimp): New. + +2018-11-27 Jim Wilson + + * riscv-opc.c (ciw): Fix whitespace to align columns. + (ca): New. + +2018-11-21 John Darrington + + * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case + if the postbyte matches the appropriate pattern. + +2018-11-13 Francois H. Theron + + * nfp-dis.c: Fix crc[] disassembly if operands are swapped. + +2018-11-12 Sudakshina Das + + * aarch64-opc.c (aarch64_sys_regs_dc): New entries for + IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA, + IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP, + CIGDVAC and GZVA. + (aarch64_sys_ins_reg_supported_p): New check for above. + +2018-11-12 Sudakshina Das + + * aarch64-opc.c (aarch64_sys_regs): New entries for TCO, + TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, + RGSR_EL1 and GCR_EL1. + (aarch64_sys_reg_supported_p): New check for above. + (aarch64_pstatefields): New entry for TCO. + (aarch64_pstatefield_supported_p): New check for above. + +2018-11-12 Sudakshina Das + + * aarch64-asm.c (aarch64_ins_addr_simple_2): New. + * aarch64-asm.h (ins_addr_simple_2): Declare the above. + * aarch64-dis.c (aarch64_ext_addr_simple_2): New. + * aarch64-dis.h (ext_addr_simple_2): Declare the above. + * aarch64-opc.c (operand_general_constraint_met_p): Add case for + AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed. + (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2. + * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv. + (AARCH64_OPERANDS): Define ADDR_SIMPLE_2. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2018-11-12 Sudakshina Das + + * aarch64-tbl.h (QL_LDG): New. + (aarch64_opcode_table): Add ldg. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2018-11-12 Sudakshina Das + + * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data + for AARCH64_OPND_QLF_imm_tag. + (operand_general_constraint_met_p): Add case for + AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13. + (aarch64_print_operand): Likewise. + * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New. + (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp + for both offset and pre/post indexed versions. + (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2018-11-12 Sudakshina Das + + * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2018-11-12 Sudakshina Das + + * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3. + (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New. + * aarch64-opc.c (fields): Add entry for imm4_3. + (operand_general_constraint_met_p): Add cases for + AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10. + (aarch64_print_operand): Likewise. + * aarch64-tbl.h (QL_ADDG): New. + (aarch64_opcode_table): Add addg, subg, irg and gmi. + (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10. + * aarch64-asm.c (aarch64_ins_imm): Add case for + operand_need_shift_by_four. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2018-11-12 Sudakshina Das + + * aarch64-tbl.h (aarch64_feature_memtag): New. + (MEMTAG, MEMTAG_INSN): New. + +2018-11-06 Sudakshina Das + + * arm-dis.c (select_arm_features): Update bfd_mach_arm_8 + with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML. + +2018-11-06 Alan Modra + + * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls), + (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0), + (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16), + (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd): + Don't return zero on error, insert mask bits instead. + (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete. + (insert_sh6, extract_sh6): Delete dead code. + (insert_sprbat, insert_sprg): Use unsigned comparisions. + (powerpc_operands ): Set shift count rather than using + PPC_OPSHIFT_INV. + : Likewise. Don't use insert/extract functions. + +2018-11-06 Jan Beulich + + * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for + vpbroadcast{d,q} with GPR operand. + +2018-11-06 Jan Beulich + + * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete. + * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand + cases up one level in the hierarchy. + +2018-11-06 Jan Beulich + + * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0, + MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0. + (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold + into MOD_VEX_0F93_P_3_LEN_0. + (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR + operand cases up one level in the hierarchy. + +2018-11-06 Jan Beulich + + * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2, + VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2, + EVEX_W_0F3A22_P_2): Delete. + (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w} + entries up one level in the hierarchy. + (OP_E_memory): Handle dq_mode when determining Disp8 shift + value. + * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q} + entries up one level in the hierarchy. + * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to + VexWIG for AVX flavors. + * i386-tbl.h: Re-generate. + +2018-11-06 Jan Beulich + + * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri, + vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd, + vcvtusi2ss, kmovd): Drop VexW=1. + * i386-tbl.h: Re-generate. + 2018-11-06 Jan Beulich * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,