X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=9d02fc45e7c505e955af3b9aeb9e1e1400af17b9;hb=ce504911e5c4068a3498eebde4064b24382c7598;hp=67332b06e8aa99a31d8999f49fae73846fecaeb2;hpb=4814632e69636177b71b8d091009a0ec614916ec;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 67332b06e8..9d02fc45e7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,271 @@ +2020-02-16 H.J. Lu + + * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from + CPU_ANY_SSE4A_FLAGS. + +2020-02-17 Alan Modra + + * i386-gen.c (cpu_flag_init): Correct last change. + +2020-02-16 H.J. Lu + + * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove + CPU_ANY_SSE4_FLAGS. + +2020-02-14 H.J. Lu + + * i386-opc.tbl (movsx): Remove Intel syntax comments. + (movzx): Likewise. + +2020-02-14 Jan Beulich + + PR gas/25438 + * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as + destination for Cpu64-only variant. + (movzx): Fold patterns. + * i386-tbl.h: Re-generate. + +2020-02-13 Jan Beulich + + * i386-gen.c (cpu_flag_init): Move CpuSSE4a from + CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add + CPU_ANY_SSE4_FLAGS entry. + * i386-init.h: Re-generate. + +2020-02-12 Jan Beulich + + * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form + with Unspecified, making the present one AT&T syntax only. + * i386-tbl.h: Re-generate. + +2020-02-12 Jan Beulich + + * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. + * i386-tbl.h: Re-generate. + +2020-02-12 Jan Beulich + + PR gas/24546 + * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. + * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into + Amd64 and Intel64 templates. + (call, jmp): Likewise for far indirect variants. Dro + Unspecified. + * i386-tbl.h: Re-generate. + +2020-02-11 Jan Beulich + + * i386-gen.c (opcode_modifiers): Remove ShortForm entry. + * i386-opc.h (ShortForm): Delete. + (struct i386_opcode_modifier): Remove shortform field. + * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, + fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, + fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, + ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): + Drop ShortForm. + * i386-tbl.h: Re-generate. + +2020-02-11 Jan Beulich + + * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, + fucompi): Drop ShortForm from operand-less templates. + * i386-tbl.h: Re-generate. + +2020-02-11 Alan Modra + + * cgen-ibld.in (extract_normal): Set *valuep on all return paths. + * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, + * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, + * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, + * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. + +2020-02-10 Matthew Malcomson + + * arm-dis.c (print_insn_cde): Define 'V' parse character. + (cde_opcodes): Add VCX* instructions. + +2020-02-10 Stam Markianos-Wright + Matthew Malcomson + + * arm-dis.c (struct cdeopcode32): New. + (CDE_OPCODE): New macro. + (cde_opcodes): New disassembly table. + (regnames): New option to table. + (cde_coprocs): New global variable. + (print_insn_cde): New + (print_insn_thumb32): Use print_insn_cde. + (parse_arm_disassembler_options): Parse coprocN args. + +2020-02-10 H.J. Lu + + PR gas/25516 + * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 + with ISA64. + * i386-opc.h (AMD64): Removed. + (Intel64): Likewose. + (AMD64): New. + (INTEL64): Likewise. + (INTEL64ONLY): Likewise. + (i386_opcode_modifier): Replace amd64 and intel64 with isa64. + * i386-opc.tbl (Amd64): New. + (Intel64): Likewise. + (Intel64Only): Likewise. + Replace AMD64 with Amd64. Update sysenter/sysenter with + Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. + * i386-tbl.h: Regenerated. + +2020-02-07 Sergey Belyashov + + PR 25469 + * z80-dis.c: Add support for GBZ80 opcodes. + +2020-02-04 Alan Modra + + * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned. + +2020-02-03 Alan Modra + + * m32c-ibld.c: Regenerate. + +2020-02-01 Alan Modra + + * frv-ibld.c: Regenerate. + +2020-01-31 Jan Beulich + + * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete. + (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label. + (OP_E_memory): Replace xmm_mdq_mode case label by + vex_scalar_w_dq_mode one. + * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar. + +2020-01-31 Jan Beulich + + * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete. + (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode, + vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments. + (intel_operand_size): Drop vex_w_dq_mode case label. + +2020-01-31 Richard Sandiford + + * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. + Remove C_SCAN_MOVPRFX for SVE bfcvtnt. + +2020-01-30 Alan Modra + + * m32c-ibld.c: Regenerate. + +2020-01-30 Jose E. Marchesi + + * bpf-opc.c: Regenerate. + +2020-01-30 Jan Beulich + + * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. + (dis386): Use them to replace C2/C3 table entries. + (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. + * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 + ones. Use Size64 instead of DefaultSize on Intel64 ones. + * i386-tbl.h: Re-generate. + +2020-01-30 Jan Beulich + + * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword + forms. + (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop + DefaultSize. + * i386-tbl.h: Re-generate. + +2020-01-30 Alan Modra + + * tic4x-dis.c (tic4x_dp): Make unsigned. + +2020-01-27 H.J. Lu + Jan Beulich + + PR binutils/25445 + * i386-dis.c (MOVSXD_Fixup): New function. + (movsxd_mode): New enum. + (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. + (intel_operand_size): Handle movsxd_mode. + (OP_E_register): Likewise. + (OP_G): Likewise. + * i386-opc.tbl: Remove Rex64 and allow 32-bit destination + register on movsxd. Add movsxd with 16-bit destination register + for AMD64 and Intel64 ISAs. + * i386-tbl.h: Regenerated. + +2020-01-27 Tamar Christina + + PR 25403 + * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. + * aarch64-asm-2.c: Regenerate + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + +2020-01-21 Jan Beulich + + * i386-opc.tbl (sysret): Drop DefaultSize. + * i386-tbl.h: Re-generate. + +2020-01-21 Jan Beulich + + * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and + Dword. + (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword. + * i386-tbl.h: Re-generate. + +2020-01-20 Nick Clifton + + * po/de.po: Updated German translation. + * po/pt_BR.po: Updated Brazilian Portuguese translation. + * po/uk.po: Updated Ukranian translation. + +2020-01-20 Alan Modra + + * hppa-dis.c (fput_const): Remove useless cast. + +2020-01-20 Alan Modra + + * arm-dis.c (print_insn_arm): Wrap 'T' value. + +2020-01-18 Nick Clifton + + * configure: Regenerate. + * po/opcodes.pot: Regenerate. + +2020-01-18 Nick Clifton + + Binutils 2.34 branch created. + +2020-01-17 Christian Biesinger + + * opintl.h: Fix spelling error (seperate). + +2020-01-17 H.J. Lu + + * i386-opc.tbl: Add {vex} pseudo prefix. + * i386-tbl.h: Regenerated. + +2020-01-16 Andre Vieira + + PR 25376 + * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. + (neon_opcodes): Likewise. + (select_arm_features): Make sure we enable MVE bits when selecting + armv8.1-m.main. Make sure we do not enable MVE bits when not selecting + any architecture. + +2020-01-16 Jan Beulich + + * i386-opc.tbl: Drop stale comment from XOP section. + +2020-01-16 Jan Beulich + + * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. + (extractps): Add VexWIG to SSE2AVX forms. + * i386-tbl.h: Re-generate. + 2020-01-16 Jan Beulich * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop