X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=cfdede862ba6ac1d9729d64401a0dce5be02953c;hb=af542c2e31e7ea8c5db851fe194841e39384a318;hp=5fd7db07162c97d81f0d4bca15d6c6834a0475a5;hpb=522fe56177eaa68d38d62ae56763544ab795c36b;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5fd7db0716..cfdede862b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,238 @@ +2009-08-22 Ralf Wildenhues + + * Makefile.am (install-pdf, install-html): Remove. + * Makefile.in: Regenerate. + + * Makefile.in: Regenerate. + * aclocal.m4: Likewise. + * config.in: Likewise. + * configure: Likewise. + +2009-08-06 Michael Eager + + * Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to + CFILES, microblaze-dis.lo to ALL_MACHINES, targets. + * Makefile.in: Regenerate. + * configure.in: Add bfd_microblaze_arch target. + * configure: Regenerate. + * disassemble.c: Define ARCH_microblaze, return + print_insn_microblaze(). + * microblaze-dis.c: New MicroBlaze disassembler. + * microblaze-opc.h: New MicroBlaze opcode definitions. + * microblaze-opcm.h: New MicroBlaze opcode types. + +2009-07-25 H.J. Lu + + * configure.in: Handle bfd_l1om_arch. + * disassemble.c (disassembler): Likewise. + + * configure: Regenerated. + + * i386-dis.c (print_insn): Handle bfd_mach_l1om and + bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM. + + * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM. + Add CPU_L1OM_FLAGS. + (cpu_flags): Add CpuL1OM. + (set_bitfield): Take an argument to set the value field. + (process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY). + (process_i386_opcode_modifier): Updated. + (process_i386_operand_type): Likewise. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + + * i386-opc.h (CpuL1OM): New. + (CpuXsave): Updated. + (i386_cpu_flags): Add cpul1om. + +2009-07-24 Jan Beulich + + * i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add + frstpm. + * i386-gen.c (cpu_flag_init): Add FP enabling flags where needed. + (cpu_flags): Add Cpu8087, Cpu287, Cpu387, Cpu687, and CpuFISTTP. + (set_bitfield): Expand CpuFP to Cpu8087|Cpu287|Cpu387. + * i386-opc.h (Cpu8087, Cpu287, Cpu387, Cpu687, CpuFISTTP): + Define. + (union i386_cpu_flags): Add cpu8087, cpu287, cpu387, cpu687, + and cpufisttp. + * i386-opc.tbl: Qualify floating point instructions by their + respective CpuXXX flag. Fix fucom{,p,pp}, fprem1, fsin, fcos, + and fsincos to be avilable only on 387. Fix fstsw ax to be + available only on 287+. Add f{,n}eni, f{,n}disi, f{,n}setpm, + and frstpm. + * i386-init.h, i386-tbl.h: Regenerate. + +2009-07-20 Nick Clifton + + PR 10288 + * arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register + offset or indexed based addressing mode 3. + +2009-07-14 Nick Clifton + + PR 10288 + * arm-dis.c (arm_opcodes): Catch illegal Addressing Mode 1 + patterns. + (arm_decode_shift): Catch illegal register based shifts. + (print_insn_arm): Properly handle negative register r0 + post-indexed addressing. + +2009-07-10 Doug Kwan + + * arm-disc.c (print_insn_coprocessor, print_insn_arm): Print only + lower 32 bits of long types to make hexadecimal output consistent + on both 32-bit and 64-bit hosts. + +2009-07-10 Alan Modra + + * fr30-desc.c, * fr30-desc.h, * fr30-opc.c, * fr30-opc.h, + * frv-desc.c, * frv-desc.h, * frv-opc.c, * frv-opc.h, + * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c, * ip2k-opc.h, + * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c, * iq2000-opc.h, + * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opc.h, + * lm32-opinst.c, * m32c-desc.c, * m32c-desc.h, * m32c-opc.c, + * m32c-opc.h, * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, + * m32r-opc.h, * m32r-opinst.c, * mt-desc.c, * mt-desc.h, + * mt-opc.c, * mt-opc.h, * openrisc-desc.c, * openrisc-desc.h, + * openrisc-opc.c, * openrisc-opc.h, * xc16x-desc.c, * xc16x-desc.h, + * xc16x-opc.c, * xc16x-opc.h, * xstormy16-desc.c, * xstormy16-desc.h, + * xstormy16-opc.c, * xstormy16-opc.h: Regenerate. + +2009-07-07 Chung-Lin Tang + + * arm-dis.c (coprocessor_opcodes): Fix mask for waddbhus. + +2009-07-07 Nick Clifton + + PR 10288 + * arm-dis.c (arm_opcodes): Be more strict about decoding scaled + addressing modes. + +2009-07-06 DJ Delorie + + * mep-desc.c: Regenerate. + * mep-desc.h: Regenerate. + * mep-opc.c: Regenerate. + * mep-opc.h: Regenerate. + +2009-07-06 Dwarakanath Rajagopal + + * i386-opc.h (CpuFMA4): Add CpuFMA4. + (i386_cpu_flags): New. + * i386-gen.c: Add CPU_FMA4_FLAGS. + * i386-opc.tbl: Add FMA4 instructions. + * i386-tbl.h: Regenerate. + * i386-init.h: Regenerate. + * i386-dis.c (OP_VEX_FMA): New. Handle FMA4. + (OP_XMM_VexW): Ditto. + (OP_EX_VexW): Ditto. + (VEXI4_Fixup): Ditto. + (VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros. + (PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New. + (PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New. + (PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New. + (PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New. + (PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New. + (PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New. + (PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New. + (VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New. + (VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New. + (VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New. + (get_vex_imm8): New. handle FMA4. + (OP_EX_VexReg): Ditto. + +2009-06-30 Nick Clifton + + PR 10288 + * arm-dis.c (coprocessor): Print the LDC and STC versions of the + LFM and SFM instructions as comments,. + Improve consistency of formatting for instructions displayed as + comments and decimal values displayed with their hexadecimal + equivalents. + Formatting tidy ups. + +2009-06-29 Nick Clifton + + PR 10288 + * arm-dis.c (enum opcode_sentinels): New: Used to mark the + boundary between variaant and generic coprocessor instuctions. + (coprocessor): Use it. + Fix architecture version of MCRR and MRRC instructions. + (arm_opcdes): Fix patterns for STRB and STRH instructions. + (print_insn_coprocessor): Check architecture and extension masks. + Print a hexadecimal version of any decimal constant that is + outside of the range of -16 to +32. + (print_arm_address): Add a return value of the offset used in the + adress, if it is worth printing a hexadecimal version of it. + (print_insn_neon): Print a hexadecimal version of any decimal + constant that is outside of the range of -16 to +32. + (print_insn_arm): Likewise. + (print_insn_thumb16): Likewise. + (print_insn_thumb32): Likewise. + + PR 10297 + * arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description + of an undefined instruction. + (arm_opcodes): Use it. + (thumb_opcod): Use it. + (thumb32_opc): Use it. + +2009-06-23 DJ Delorie + + * mep-desc.c: Regenerate. + * mep-desc.h: Regenerate. + * mep-dis.c: Regenerate. + * mep-ibld.c: Regenerate. + * mep-opc.c: Regenerate. + + * mep-asm.c: Regenerate. + * mep-opc.c: Regenerate. + * mep-opc.h: Regenerate. + +2009-06-22 Nick Clifton + + * po/fi.po: Updated Finish translation. + +2009-06-22 Alan Modra + + * m32c-asm.c: Regenerate. + +2009-06-22 Alan Modra + + * score-dis.c (print_insn_score48, print_insn_score32): Move default + case label to proper lexical block. + * score7-dis.c (print_insn_score32): Likewise. + +2009-06-19 Martin Schwidefsky + + * s390-opc.c (INSTR_RR_0R_OPT, INSTR_RX_0RRD_OPT, MASK_RR_0R_OPT, + MASK_RX_0RRD_OPT): New instruction formats with optional arguments. + * s390-opc.txt (nopr, nop): Use new instruction format. + +2009-06-18 Nick Clifton + + PR 10288 + * arm-dis.c (print_insn_coprocessor): Check that a user specified + ARM architecture supports the matched instruction. + (print_insn_arm): Likewise. + (select_arm_features): New function. Fills in the fields of an + arm_feature_set structure based on a given arm machine number. + (print_insn): Initialise an arm_feature_set structure. + +2009-06-16 Maciej W. Rozycki + + * vax-dis.c (is_function_entry): Return success for synthetic + symbols too. + (is_plt_tail): New function. + (print_insn_vax): Decode PLT entry offset longword. + 2009-06-15 Nick Clifton + PR 10186 + * arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W + instruction. + PR 10173 * cr16-dis.c (print_arg): Avoid printing the 0x prefix twice.