X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Farc-dis.c;h=a47e81f0a28be49522bb9e2e38bb43ec0b7c0b93;hb=a6e5765ff1c5fdebaf4953eed619a717178cc7e6;hp=7541b74d23034a10fa79bc00925a0d022d805323;hpb=fdddd2900f39584e7d6cee27127593fba2cb0cf2;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index 7541b74d23..a47e81f0a2 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -1,5 +1,5 @@ /* Instruction printing code for the ARC. - Copyright (C) 1994-2017 Free Software Foundation, Inc. + Copyright (C) 1994-2019 Free Software Foundation, Inc. Contributed by Claudiu Zissulescu (claziss@synopsys.com) @@ -137,8 +137,7 @@ static bfd_boolean print_hex = FALSE; (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \ : bfd_getb32 (buf)) -#define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \ - (s + (sizeof (word) * 8 - 1 - e))) +#define BITS(word,s,e) (((word) >> (s)) & ((1ull << ((e) - (s)) << 1) - 1)) #define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31)) /* Functions implementation. */ @@ -181,7 +180,9 @@ skip_this_opcode (const struct arc_opcode *opcode) /* Check opcode for major 0x06, return if it is not in. */ if (arc_opcode_len (opcode) == 4 - && OPCODE_32BIT_INSN (opcode->opcode) != 0x06) + && (OPCODE_32BIT_INSN (opcode->opcode) != 0x06 + /* Can be an APEX extensions. */ + && OPCODE_32BIT_INSN (opcode->opcode) != 0x07)) return FALSE; /* or not a known truble class. */ @@ -190,6 +191,7 @@ skip_this_opcode (const struct arc_opcode *opcode) case FLOAT: case DSP: case ARITH: + case MPY: break; default: return FALSE; @@ -292,7 +294,7 @@ find_format_from_table (struct disassemble_info *info, if (operand->extract) value = (*operand->extract) (insn, &invalid); else - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + value = (insn >> operand->shift) & ((1ull << operand->bits) - 1); /* Check for LIMM indicator. If it is there, then make sure we pick the right format. */ @@ -669,7 +671,7 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info) break; default: - abort (); + return 0; } } @@ -764,6 +766,23 @@ parse_option (const char *option) else if (disassembler_options_cmp (option, "fpuda") == 0) add_to_decodelist (FLOAT, DPA); + else if (disassembler_options_cmp (option, "nps400") == 0) + { + add_to_decodelist (ACL, NPS400); + add_to_decodelist (ARITH, NPS400); + add_to_decodelist (BITOP, NPS400); + add_to_decodelist (BMU, NPS400); + add_to_decodelist (CONTROL, NPS400); + add_to_decodelist (DMA, NPS400); + add_to_decodelist (DPI, NPS400); + add_to_decodelist (MEMORY, NPS400); + add_to_decodelist (MISC, NPS400); + add_to_decodelist (NET, NPS400); + add_to_decodelist (PMU, NPS400); + add_to_decodelist (PROTOCOL_DECODE, NPS400); + add_to_decodelist (ULTRAIP, NPS400); + } + else if (disassembler_options_cmp (option, "fpus") == 0) { add_to_decodelist (FLOAT, SP); @@ -778,7 +797,8 @@ parse_option (const char *option) else if (CONST_STRNEQ (option, "hex")) print_hex = TRUE; else - fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); + /* xgettext:c-format */ + opcodes_error_handler (_("unrecognised disassembler option: %s"), option); } #define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \ @@ -820,7 +840,8 @@ parse_cpu_option (const char *option) } } - fprintf (stderr, _("Unrecognised disassembler CPU option: %s\n"), option); + /* xgettext:c-format */ + opcodes_error_handler (_("unrecognised disassembler CPU option: %s"), option); return ARC_OPCODE_NONE; } @@ -923,9 +944,10 @@ print_insn_arc (bfd_vma memaddr, bfd_boolean open_braket; int size; const struct arc_operand *operand; - int value; + int value, vpcl; struct arc_operand_iterator iter; struct arc_disassemble_info *arc_infop; + bfd_boolean rpcl = FALSE, rset = FALSE; if (info->disassembler_options) { @@ -986,7 +1008,6 @@ print_insn_arc (bfd_vma memaddr, the number of bytes objdump should display on a single line. If the instruction decoder sets this, it should always set it to the same value in order to get reasonable looking output. */ - info->bytes_per_line = 8; /* In the next lines, we set two info variables control the way @@ -994,7 +1015,6 @@ print_insn_arc (bfd_vma memaddr, 8 and bytes_per_chunk is 4, the output will look like this: 00: 00000000 00000000 with the chunks displayed according to "display_endian". */ - if (info->section && !(info->section->flags & SEC_CODE)) { @@ -1022,6 +1042,7 @@ print_insn_arc (bfd_vma memaddr, /* Read the insn into a host word. */ status = (*info->read_memory_func) (memaddr, buffer, size, info); + if (status != 0) { (*info->memory_error_func) (status, memaddr, info); @@ -1048,13 +1069,16 @@ print_insn_arc (bfd_vma memaddr, (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data); break; default: - abort (); + return -1; } return size; } insn_len = arc_insn_length (buffer[highbyte], buffer[lowbyte], info); pr_debug ("instruction length = %d bytes\n", insn_len); + if (insn_len == 0) + return -1; + arc_infop = info->private_data; arc_infop->insn_len = insn_len; @@ -1107,7 +1131,7 @@ print_insn_arc (bfd_vma memaddr, default: /* There is no instruction whose length is not 2, 4, 6, or 8. */ - abort (); + return -1; } pr_debug ("instruction value = %llx\n", insn); @@ -1132,27 +1156,31 @@ print_insn_arc (bfd_vma memaddr, switch (insn_len) { case 2: - (*info->fprintf_func) (info->stream, ".long %#04llx", + (*info->fprintf_func) (info->stream, ".shor\t%#04llx", insn & 0xffff); break; + case 4: - (*info->fprintf_func) (info->stream, ".long %#08llx", + (*info->fprintf_func) (info->stream, ".word\t%#08llx", insn & 0xffffffff); break; + case 6: - (*info->fprintf_func) (info->stream, ".long %#08llx", + (*info->fprintf_func) (info->stream, ".long\t%#08llx", insn & 0xffffffff); - (*info->fprintf_func) (info->stream, ".long %#04llx", + (*info->fprintf_func) (info->stream, ".long\t%#04llx", (insn >> 32) & 0xffff); break; + case 8: - (*info->fprintf_func) (info->stream, ".long %#08llx", + (*info->fprintf_func) (info->stream, ".long\t%#08llx", insn & 0xffffffff); - (*info->fprintf_func) (info->stream, ".long %#08llx", + (*info->fprintf_func) (info->stream, ".long\t%#08llx", insn >> 32); break; + default: - abort (); + return -1; } info->insn_type = dis_noninsn; @@ -1178,6 +1206,7 @@ print_insn_arc (bfd_vma memaddr, /* Now extract and print the operands. */ operand = NULL; + vpcl = 0; while (operand_iterator_next (&iter, &operand, &value)) { if (open_braket && (operand->flags & ARC_OPERAND_BRAKET)) @@ -1215,6 +1244,20 @@ print_insn_arc (bfd_vma memaddr, need_comma = TRUE; + if (operand->flags & ARC_OPERAND_PCREL) + { + rpcl = TRUE; + vpcl = value; + rset = TRUE; + + info->target = (bfd_vma) (memaddr & ~3) + value; + } + else if (!(operand->flags & ARC_OPERAND_IR)) + { + vpcl = value; + rset = TRUE; + } + /* Print the operand as directed by the flags. */ if (operand->flags & ARC_OPERAND_IR) { @@ -1232,6 +1275,10 @@ print_insn_arc (bfd_vma memaddr, rname = regnames[value + 1]; (*info->fprintf_func) (info->stream, "%s", rname); } + if (value == 63) + rpcl = TRUE; + else + rpcl = FALSE; } else if (operand->flags & ARC_OPERAND_LIMM) { @@ -1247,15 +1294,6 @@ print_insn_arc (bfd_vma memaddr, info->target = (bfd_vma) value; } } - else if (operand->flags & ARC_OPERAND_PCREL) - { - /* PCL relative. */ - if (info->flags & INSN_HAS_RELOC) - memaddr = 0; - (*info->print_address_func) ((memaddr & ~3) + value, info); - - info->target = (bfd_vma) (memaddr & ~3) + value; - } else if (operand->flags & ARC_OPERAND_SIGNED) { const char *rname = get_auxreg (opcode, value, isa_mask); @@ -1283,6 +1321,7 @@ print_insn_arc (bfd_vma memaddr, && !(operand->flags & ARC_OPERAND_ALIGNED16) && value >= 0 && value <= 14) { + /* Leave/Enter mnemonics. */ switch (value) { case 0: @@ -1296,6 +1335,8 @@ print_insn_arc (bfd_vma memaddr, regnames[13 + value - 1]); break; } + rpcl = FALSE; + rset = FALSE; } else { @@ -1326,6 +1367,21 @@ print_insn_arc (bfd_vma memaddr, arc_infop->operands_count ++; } + /* Pretty print extra info for pc-relative operands. */ + if (rpcl && rset) + { + if (info->flags & INSN_HAS_RELOC) + /* If the instruction has a reloc associated with it, then the + offset field in the instruction will actually be the addend + for the reloc. (We are using REL type relocs). In such + cases, we can ignore the pc when computing addresses, since + the addend is not currently pc-relative. */ + memaddr = 0; + + (*info->fprintf_func) (info->stream, "\t;"); + (*info->print_address_func) ((memaddr & ~3) + vpcl, info); + } + return insn_len; } @@ -1379,6 +1435,8 @@ with -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _("\ fpud Recognize double precision FPU instructions.\n")); fprintf (stream, _("\ + nps400 Recognize NPS400 instructions.\n")); + fprintf (stream, _("\ hex Use only hexadecimal number to print immediates.\n")); }