X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Farc-opc.c;h=675738aa6befdf1bc016b3bc8ddff5ff36d3b557;hb=4c4addbe57711f1cdbb72305b8cbd03a68ae2e34;hp=7f934ce5b5d101595ab783d3a5ae543e2dabba23;hpb=684d5a10b1332e2a1b03a1d6e7a899ef87b3ea16;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index 7f934ce5b5..675738aa6b 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -1,5 +1,5 @@ /* Opcode table for the ARC. - Copyright (C) 1994-2017 Free Software Foundation, Inc. + Copyright (C) 1994-2020 Free Software Foundation, Inc. Contributed by Claudiu Zissulescu (claziss@synopsys.com) @@ -170,7 +170,9 @@ insert_rhv2 (unsigned long long insn, const char ** errmsg) { if (value == 0x1E) - *errmsg = _("Register R30 is a limm indicator"); + *errmsg = _("register R30 is a limm indicator"); + else if (value < 0 || value > 31) + *errmsg = _("register out of range"); return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); } @@ -189,7 +191,7 @@ insert_r0 (unsigned long long insn, const char ** errmsg) { if (value != 0) - *errmsg = _("Register must be R0"); + *errmsg = _("register must be R0"); return insn; } @@ -207,7 +209,7 @@ insert_r1 (unsigned long long insn, const char ** errmsg) { if (value != 1) - *errmsg = _("Register must be R1"); + *errmsg = _("register must be R1"); return insn; } @@ -224,7 +226,7 @@ insert_r2 (unsigned long long insn, const char ** errmsg) { if (value != 2) - *errmsg = _("Register must be R2"); + *errmsg = _("register must be R2"); return insn; } @@ -241,7 +243,7 @@ insert_r3 (unsigned long long insn, const char ** errmsg) { if (value != 3) - *errmsg = _("Register must be R3"); + *errmsg = _("register must be R3"); return insn; } @@ -258,7 +260,7 @@ insert_sp (unsigned long long insn, const char ** errmsg) { if (value != 28) - *errmsg = _("Register must be SP"); + *errmsg = _("register must be SP"); return insn; } @@ -275,7 +277,7 @@ insert_gp (unsigned long long insn, const char ** errmsg) { if (value != 26) - *errmsg = _("Register must be GP"); + *errmsg = _("register must be GP"); return insn; } @@ -292,7 +294,7 @@ insert_pcl (unsigned long long insn, const char ** errmsg) { if (value != 63) - *errmsg = _("Register must be PCL"); + *errmsg = _("register must be PCL"); return insn; } @@ -309,7 +311,7 @@ insert_blink (unsigned long long insn, const char ** errmsg) { if (value != 31) - *errmsg = _("Register must be BLINK"); + *errmsg = _("register must be BLINK"); return insn; } @@ -326,7 +328,7 @@ insert_ilink1 (unsigned long long insn, const char ** errmsg) { if (value != 29) - *errmsg = _("Register must be ILINK1"); + *errmsg = _("register must be ILINK1"); return insn; } @@ -343,7 +345,7 @@ insert_ilink2 (unsigned long long insn, const char ** errmsg) { if (value != 30) - *errmsg = _("Register must be ILINK2"); + *errmsg = _("register must be ILINK2"); return insn; } @@ -374,7 +376,7 @@ insert_ras (unsigned long long insn, insn |= (value - 8); break; default: - *errmsg = _("Register must be either r0-r3 or r12-r15"); + *errmsg = _("register must be either r0-r3 or r12-r15"); break; } return insn; @@ -412,7 +414,7 @@ insert_rbs (unsigned long long insn, insn |= ((value - 8)) << 8; break; default: - *errmsg = _("Register must be either r0-r3 or r12-r15"); + *errmsg = _("register must be either r0-r3 or r12-r15"); break; } return insn; @@ -450,7 +452,7 @@ insert_rcs (unsigned long long insn, insn |= ((value - 8)) << 5; break; default: - *errmsg = _("Register must be either r0-r3 or r12-r15"); + *errmsg = _("register must be either r0-r3 or r12-r15"); break; } return insn; @@ -501,7 +503,7 @@ insert_simm3s (unsigned long long insn, tmp = 0x06; break; default: - *errmsg = _("Accepted values are from -1 to 6"); + *errmsg = _("accepted values are from -1 to 6"); break; } @@ -530,9 +532,9 @@ insert_rrange (unsigned long long insn, int reg2 = value & 0xFFFF; if (reg1 != 13) - *errmsg = _("First register of the range should be r13"); + *errmsg = _("first register of the range should be r13"); else if (reg2 < 13 || reg2 > 26) - *errmsg = _("Last register of the range doesn't fit"); + *errmsg = _("last register of the range doesn't fit"); else insn |= ((reg2 - 12) & 0x0F) << 1; return insn; @@ -552,7 +554,7 @@ insert_r13el (unsigned long long insn, { if (value != 13) { - *errmsg = _("Invalid register number, should be fp"); + *errmsg = _("invalid register number, should be fp"); return insn; } @@ -567,7 +569,7 @@ insert_fpel (unsigned long long insn, { if (value != 27) { - *errmsg = _("Invalid register number, should be fp"); + *errmsg = _("invalid register number, should be fp"); return insn; } @@ -589,7 +591,7 @@ insert_blinkel (unsigned long long insn, { if (value != 31) { - *errmsg = _("Invalid register number, should be blink"); + *errmsg = _("invalid register number, should be blink"); return insn; } @@ -611,7 +613,7 @@ insert_pclel (unsigned long long insn, { if (value != 63) { - *errmsg = _("Invalid register number, should be pcl"); + *errmsg = _("invalid register number, should be pcl"); return insn; } @@ -649,10 +651,14 @@ static long long extract_w6 (unsigned long long insn, bfd_boolean * invalid ATTRIBUTE_UNUSED) { - unsigned value = 0; + int value = 0; value |= ((insn >> 6) & 0x003f) << 0; + /* Extend the sign. */ + int signbit = 1 << 5; + value = (value ^ signbit) - signbit; + return value; } @@ -715,7 +721,7 @@ insert_nps_3bit_reg_at_##OFFSET##_##NAME \ insn |= (value - 8) << (OFFSET); \ break; \ default: \ - *errmsg = _("Register must be either r0-r3 or r12-r15"); \ + *errmsg = _("register must be either r0-r3 or r12-r15"); \ break; \ } \ return insn; \ @@ -763,7 +769,7 @@ insert_nps_bitop_size_2b (unsigned long long insn, break; default: value = 0; - *errmsg = _("Invalid size, should be 1, 2, 4, or 8"); + *errmsg = _("invalid size, should be 1, 2, 4, or 8"); break; } @@ -874,7 +880,7 @@ insert_nps_imm_offset (unsigned long long insn, value = value >> 4; break; default: - *errmsg = _("Invalid position, should be 0, 16, 32, 48 or 64."); + *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64."); value = 0; } insn |= (value << 10); @@ -908,7 +914,7 @@ insert_nps_imm_entry (unsigned long long insn, value = 3; break; default: - *errmsg = _("Invalid position, should be 16, 32, 64 or 128."); + *errmsg = _("invalid position, should be 16, 32, 64 or 128."); value = 0; } insn |= (value << 2); @@ -930,7 +936,7 @@ insert_nps_size_16bit (unsigned long long insn, { if ((value < 1) || (value > 64)) { - *errmsg = _("Invalid size value must be on range 1-64."); + *errmsg = _("invalid size value must be on range 1-64."); value = 0; } value = value & 0x3f; @@ -961,7 +967,7 @@ insert_nps_##NAME##_pos (unsigned long long insn, \ value = value / 8; \ break; \ default: \ - *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \ + *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \ value = 0; \ } \ insn |= (value << SHIFT); \ @@ -986,7 +992,7 @@ insert_nps_##NAME (unsigned long long insn, \ { \ if (value < LOWER || value > UPPER) \ { \ - *errmsg = _("Invalid size, value must be " \ + *errmsg = _("invalid size, value must be " \ #LOWER " to " #UPPER "."); \ return insn; \ } \ @@ -1122,7 +1128,7 @@ insert_nps_bitop_ins_ext (unsigned long long insn, const char ** errmsg) { if (value < 0 || value > 28) - *errmsg = _("Value must be in the range 0 to 28"); + *errmsg = _("value must be in the range 0 to 28"); return insn | (value << 20); } @@ -1144,7 +1150,7 @@ insert_nps_##NAME (unsigned long long insn, \ const char ** errmsg) \ { \ if (value < 1 || value > UPPER) \ - *errmsg = _("Value must be in the range 1 to " #UPPER); \ + *errmsg = _("value must be in the range 1 to " #UPPER); \ if (value == UPPER) \ value = 0; \ return insn | (value << SHIFT); \ @@ -1174,9 +1180,9 @@ insert_nps_min_hofs (unsigned long long insn, const char ** errmsg) { if (value < 0 || value > 240) - *errmsg = _("Value must be in the range 0 to 240"); + *errmsg = _("value must be in the range 0 to 240"); if ((value % 16) != 0) - *errmsg = _("Value must be a multiple of 16"); + *errmsg = _("value must be a multiple of 16"); value = value / 16; return insn | (value << 6); } @@ -1196,7 +1202,7 @@ insert_nps_##NAME (unsigned long long insn, \ const char ** errmsg) \ { \ if (value != ARC_NPS400_ADDRTYPE_##VALUE) \ - *errmsg = _("Invalid address type for operand"); \ + *errmsg = _("invalid address type for operand"); \ return insn; \ } \ \ @@ -1230,7 +1236,7 @@ insert_nps_rbdouble_64 (unsigned long long insn, const char ** errmsg) { if (value < 0 || value > 31) - *errmsg = _("Value must be in the range 0 to 31"); + *errmsg = _("value must be in the range 0 to 31"); return insn | (value << 43) | (value << 48); } @@ -1255,7 +1261,7 @@ insert_nps_misc_imm_offset (unsigned long long insn, { if (value & 0x3) { - *errmsg = _("Invalid position, should be 0,4, 8,...124."); + *errmsg = _("invalid position, should be one of: 0,4,8,...124."); value = 0; } insn |= (value << 6); @@ -1269,6 +1275,18 @@ extract_nps_misc_imm_offset (unsigned long long insn, return ((insn >> 8) & 0x1f) * 4; } +static long long int +extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + value |= ((insn >> 0) & 0x003f) << 6; + + return value; +} + /* Include the generic extract/insert functions. Order is important as some of the functions present in the .h may be disabled via defines. */ @@ -1673,7 +1691,7 @@ const struct arc_flag_class arc_flag_classes[] = { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}}, #define C_NE (C_AS + 1) - { F_CLASS_OPTIONAL, { F_NE, F_NULL}}, + { F_CLASS_REQUIRED, { F_NE, F_NULL}}, /* ARC NPS400 Support: See comment near head of file. */ #define C_NPS_CL (C_NE + 1) @@ -1804,7 +1822,9 @@ const struct arc_operand arc_operands[] = #define RAD (RBdup + 1) { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, -#define RCD (RAD + 1) +#define RAD_CHK (RAD + 1) + { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, +#define RCD (RAD_CHK + 1) { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 }, /* The plain integer register fields. Used by short @@ -1934,8 +1954,12 @@ const struct arc_operand arc_operands[] = {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, insert_simm12_20, extract_simm12_20}, + /* UIMM12_20 mask = 00000000000000000000111111222222. */ +#define UIMM12_20 (SIMM12_20R + 1) + {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20}, + /* SIMM3_5_S mask = 0000011100000000. */ -#define SIMM3_5_S (SIMM12_20R + 1) +#define SIMM3_5_S (UIMM12_20 + 1) {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, insert_simm3s, extract_simm3s}, @@ -1990,7 +2014,7 @@ const struct arc_operand arc_operands[] = /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ #define SIMM21_A16_5 (UIMM6_8 + 1) {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED - | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, + | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a16_5, extract_simm21_a16_5}, /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */