X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Farm-dis.c;h=62a2a39ab62df8ef659ad71d8ffc58c31166eac9;hb=9255ee3150832d7e235fc0711f0efa70700559e7;hp=f131adafebfbb5f6f88d59e8472d13c4deeb9bad;hpb=a7f8487eecca8e23ac7be6b152e1a139e620c2ab;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index f131adafeb..62a2a39ab6 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1,19 +1,20 @@ /* Instruction printing code for the ARM - Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc. + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) Modification by James G. Smith (jsmith@cygnus.co.uk) -This file is part of libopcodes. +This file is part of libopcodes. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) -any later version. +any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. +more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software @@ -27,7 +28,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "libcoff.h" #include "opintl.h" -/* FIXME: This shouldn't be done here */ +/* FIXME: This shouldn't be done here. */ #include "elf-bfd.h" #include "elf/internal.h" #include "elf/arm.h" @@ -60,6 +61,8 @@ static arm_regname regnames[] = { { "raw" , "Select raw register names", { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, + { "gcc", "Select register names used by GCC", + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, { "std", "Select register names used in ARM's ISA documentation", { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, { "apcs", "Select register names used in the APCS", @@ -70,41 +73,47 @@ static arm_regname regnames[] = { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} }; -/* Default to standard register name set. */ +/* Default to GCC register name set. */ static unsigned int regname_selected = 1; #define NUM_ARM_REGNAMES NUM_ELEM (regnames) #define arm_regnames regnames[regname_selected].reg_names -static boolean force_thumb = false; +static bfd_boolean force_thumb = FALSE; static char * arm_fp_const[] = {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; -static char * arm_shift[] = +static char * arm_shift[] = {"lsl", "lsr", "asr", "ror"}; /* Forward declarations. */ -static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); -static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); -static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); -static void parse_disassembler_options PARAMS ((char *)); -static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); +static void arm_decode_shift + PARAMS ((long, fprintf_ftype, void *)); +static int print_insn_arm + PARAMS ((bfd_vma, struct disassemble_info *, long)); +static int print_insn_thumb + PARAMS ((bfd_vma, struct disassemble_info *, long)); +static void parse_disassembler_options + PARAMS ((char *)); +static int print_insn + PARAMS ((bfd_vma, struct disassemble_info *, bfd_boolean)); int get_arm_regname_num_options (void); int set_arm_regname_option (int option); int get_arm_regnames (int option, const char **setname, const char **setdescription, const char ***register_names); -/* Functions. */ +/* Functions. */ int -get_arm_regname_num_options (void) +get_arm_regname_num_options () { return NUM_ARM_REGNAMES; } int -set_arm_regname_option (int option) +set_arm_regname_option (option) + int option; { int old = regname_selected; regname_selected = option; @@ -112,9 +121,11 @@ set_arm_regname_option (int option) } int -get_arm_regnames (int option, const char **setname, - const char **setdescription, - const char ***register_names) +get_arm_regnames (option, setname, setdescription, register_names) + int option; + const char **setname; + const char **setdescription; + const char ***register_names; { *setname = regnames[option].name; *setdescription = regnames[option].description; @@ -129,14 +140,14 @@ arm_decode_shift (given, func, stream) void * stream; { func (stream, "%s", arm_regnames[given & 0xf]); - + if ((given & 0xff0) != 0) { if ((given & 0x10) == 0) { int amount = (given & 0xf80) >> 7; int shift = (given & 0x60) >> 5; - + if (amount == 0) { if (shift == 3) @@ -144,10 +155,10 @@ arm_decode_shift (given, func, stream) func (stream, ", rrx"); return; } - + amount = 32; } - + func (stream, ", %s #%d", arm_shift[shift], amount); } else @@ -158,22 +169,23 @@ arm_decode_shift (given, func, stream) /* Print one instruction from PC on INFO->STREAM. Return the size of the instruction (always 4 on ARM). */ + static int print_insn_arm (pc, info, given) - bfd_vma pc; - struct disassemble_info * info; - long given; + bfd_vma pc; + struct disassemble_info *info; + long given; { - struct arm_opcode * insn; - void * stream = info->stream; - fprintf_ftype func = info->fprintf_func; + const struct arm_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; for (insn = arm_opcodes; insn->assembler; insn++) { if ((given & insn->mask) == insn->value) { char * c; - + for (c = insn->assembler; *c; c++) { if (*c == '%') @@ -189,16 +201,16 @@ print_insn_arm (pc, info, given) && ((given & 0x02000000) == 0)) { int offset = given & 0xfff; - + func (stream, "[pc"); - + if (given & 0x01000000) { if ((given & 0x00800000) == 0) offset = - offset; - - /* pre-indexed */ - func (stream, ", #%x]", offset); + + /* Pre-indexed. */ + func (stream, ", #%d]", offset); offset += pc + 8; @@ -212,17 +224,18 @@ print_insn_arm (pc, info, given) else { /* Post indexed. */ - func (stream, "], #%x", offset); + func (stream, "], #%d", offset); - offset = pc + 8; /* ie ignore the offset. */ + /* ie ignore the offset. */ + offset = pc + 8; } - + func (stream, "\t; "); info->print_address_func (offset, info); } else { - func (stream, "[%s", + func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) { @@ -242,7 +255,7 @@ print_insn_arm (pc, info, given) arm_decode_shift (given, func, stream); } - func (stream, "]%s", + func (stream, "]%s", ((given & 0x00200000) != 0) ? "!" : ""); } else @@ -254,13 +267,13 @@ print_insn_arm (pc, info, given) func (stream, "], %s#%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); - else + else func (stream, "]"); } else { func (stream, "], %s", - (((given & 0x00800000) == 0) + (((given & 0x00800000) == 0) ? "-" : "")); arm_decode_shift (given, func, stream); } @@ -273,18 +286,18 @@ print_insn_arm (pc, info, given) { /* PC relative with immediate offset. */ int offset = ((given & 0xf00) >> 4) | (given & 0xf); - + if ((given & 0x00800000) == 0) offset = -offset; - - func (stream, "[pc, #%x]\t; ", offset); - + + func (stream, "[pc, #%d]\t; ", offset); + (*info->print_address_func) (offset + pc + 8, info); } else { - func (stream, "[%s", + func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) { @@ -307,7 +320,7 @@ print_insn_arm (pc, info, given) arm_regnames[given & 0xf]); } - func (stream, "]%s", + func (stream, "]%s", ((given & 0x00200000) != 0) ? "!" : ""); } else @@ -321,7 +334,7 @@ print_insn_arm (pc, info, given) func (stream, "], %s#%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); - else + else func (stream, "]"); } else @@ -335,7 +348,7 @@ print_insn_arm (pc, info, given) } } break; - + case 'b': (*info->print_address_func) (BDISP (given) * 4 + pc + 8, info); @@ -387,13 +400,6 @@ print_insn_arm (pc, info, given) func (stream, "t"); break; - case 'h': - if ((given & 0x00000020) == 0x00000020) - func (stream, "h"); - else - func (stream, "b"); - break; - case 'A': func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) @@ -419,22 +425,58 @@ print_insn_arm (pc, info, given) } break; + case 'B': + /* Print ARM V5 BLX(1) address: pc+25 bits. */ + { + bfd_vma address; + bfd_vma offset = 0; + + if (given & 0x00800000) + /* Is signed, hi bits should be ones. */ + offset = (-1) ^ 0x00ffffff; + + /* Offset is (SignExtend(offset field)<<2). */ + offset += given & 0x00ffffff; + offset <<= 2; + address = offset + pc + 8; + + if (given & 0x01000000) + /* H bit allows addressing to 2-byte boundaries. */ + address += 2; + + info->print_address_func (address, info); + } + break; + + case 'I': + /* Print a Cirrus/DSP shift immediate. */ + /* Immediates are 7bit signed ints with bits 0..3 in + bits 0..3 of opcode and bits 4..6 in bits 5..7 + of opcode. */ + { + int imm; + + imm = (given & 0xf) | ((given & 0xe0) >> 1); + + /* Is ``imm'' a negative number? */ + if (imm & 0x40) + imm |= (-1 << 7); + + func (stream, "%d", imm); + } + + break; + case 'C': - switch (given & 0x00090000) - { - default: - func (stream, "_???"); - break; - case 0x90000: - func (stream, "_all"); - break; - case 0x10000: - func (stream, "_ctl"); - break; - case 0x80000: - func (stream, "_flg"); - break; - } + func (stream, "_"); + if (given & 0x80000) + func (stream, "f"); + if (given & 0x40000) + func (stream, "s"); + if (given & 0x20000) + func (stream, "x"); + if (given & 0x10000) + func (stream, "c"); break; case 'F': @@ -453,7 +495,7 @@ print_insn_arm (pc, info, given) func (stream, "3"); } break; - + case 'P': switch (given & 0x00080080) { @@ -505,7 +547,7 @@ print_insn_arm (pc, info, given) } break; - case '0': case '1': case '2': case '3': case '4': + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int bitstart = *c++ - '0'; @@ -517,44 +559,44 @@ print_insn_arm (pc, info, given) { case '-': c++; - + while (*c >= '0' && *c <= '9') bitend = (bitend * 10) + *c++ - '0'; - + if (!bitend) abort (); - + switch (*c) { case 'r': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%s", arm_regnames[reg]); } break; case 'd': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%d", reg); } break; case 'x': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "0x%08x", reg); - + /* Some SWI instructions have special meanings. */ if ((given & 0x0fffffff) == 0x0FF00000) @@ -566,20 +608,20 @@ print_insn_arm (pc, info, given) case 'X': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%01x", reg & 0xf); } break; case 'f': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + if (reg > 7) func (stream, "#%s", arm_fp_const[reg & 7]); @@ -591,7 +633,85 @@ print_insn_arm (pc, info, given) abort (); } break; - + + case 'y': + case 'z': + { + int single = *c == 'y'; + int regno; + + switch (bitstart) + { + case 4: /* Sm pair */ + func (stream, "{"); + /* Fall through. */ + case 0: /* Sm, Dm */ + regno = given & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 5) & 1; + } + break; + + case 1: /* Sd, Dd */ + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + break; + + case 2: /* Sn, Dn */ + regno = (given >> 16) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 7) & 1; + } + break; + + case 3: /* List */ + func (stream, "{"); + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + break; + + + default: + abort (); + } + + func (stream, "%c%d", single ? 's' : 'd', regno); + + if (bitstart == 3) + { + int count = given & 0xff; + + if (single == 0) + count >>= 1; + + if (--count) + { + func (stream, "-%c%d", + single ? 's' : 'd', + regno + count); + } + + func (stream, "}"); + } + else if (bitstart == 4) + func (stream, ", %c%d}", single ? 's' : 'd', + regno + 1); + + break; + } + case '`': c++; if ((given & (1 << bitstart)) == 0) @@ -630,15 +750,16 @@ print_insn_arm (pc, info, given) /* Print one instruction from PC on INFO->STREAM. Return the size of the instruction. */ + static int print_insn_thumb (pc, info, given) - bfd_vma pc; - struct disassemble_info * info; - long given; + bfd_vma pc; + struct disassemble_info *info; + long given; { - struct thumb_opcode * insn; - void * stream = info->stream; - fprintf_ftype func = info->fprintf_func; + const struct thumb_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; for (insn = thumb_opcodes; insn->assembler; insn++) { @@ -649,28 +770,39 @@ print_insn_thumb (pc, info, given) /* Special processing for Thumb 2 instruction BL sequence: */ if (!*c) /* Check for empty (not NULL) assembler string. */ { + long offset; + info->bytes_per_chunk = 4; info->bytes_per_line = 4; - - func (stream, "bl\t"); - - info->print_address_func (BDISP23 (given) * 2 + pc + 4, info); + + offset = BDISP23 (given); + offset = offset * 2 + pc + 4; + + if ((given & 0x10000000) == 0) + { + func (stream, "blx\t"); + offset &= 0xfffffffc; + } + else + func (stream, "bl\t"); + + info->print_address_func (offset, info); return 4; } else { info->bytes_per_chunk = 2; info->bytes_per_line = 4; - + given &= 0xffff; - + for (; *c; c++) { if (*c == '%') { int domaskpc = 0; int domasklr = 0; - + switch (*++c) { case '%': @@ -680,11 +812,11 @@ print_insn_thumb (pc, info, given) case 'S': { long reg; - + reg = (given >> 3) & 0x7; if (given & (1 << 6)) reg += 8; - + func (stream, "%s", arm_regnames[reg]); } break; @@ -692,11 +824,11 @@ print_insn_thumb (pc, info, given) case 'D': { long reg; - + reg = given & 0x7; if (given & (1 << 7)) reg += 8; - + func (stream, "%s", arm_regnames[reg]); } break; @@ -718,9 +850,9 @@ print_insn_thumb (pc, info, given) { int started = 0; int reg; - + func (stream, "{"); - + /* It would be nice if we could spot ranges, and generate the rS-rE format: */ for (reg = 0; (reg < 8); reg++) @@ -752,12 +884,12 @@ print_insn_thumb (pc, info, given) break; - case '0': case '1': case '2': case '3': case '4': + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int bitstart = *c++ - '0'; int bitend = 0; - + while (*c >= '0' && *c <= '9') bitstart = (bitstart * 10) + *c++ - '0'; @@ -766,7 +898,7 @@ print_insn_thumb (pc, info, given) case '-': { long reg; - + c++; while (*c >= '0' && *c <= '9') bitend = (bitend * 10) + *c++ - '0'; @@ -858,17 +990,18 @@ print_insn_thumb (pc, info, given) } /* Parse an individual disassembler option. */ + void parse_arm_disassembler_option (option) char * option; { if (option == NULL) return; - + if (strneq (option, "reg-names-", 10)) { int i; - + option += 10; for (i = NUM_ARM_REGNAMES; i--;) @@ -877,7 +1010,7 @@ parse_arm_disassembler_option (option) regname_selected = i; break; } - + if (i < 0) fprintf (stderr, _("Unrecognised register name set: %s\n"), option); } @@ -887,17 +1020,18 @@ parse_arm_disassembler_option (option) force_thumb = 0; else fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); - + return; } /* Parse the string of disassembler options, spliting it at whitespaces. */ + static void parse_disassembler_options (options) char * options; { char * space; - + if (options == NULL) return; @@ -920,11 +1054,12 @@ parse_disassembler_options (options) /* NOTE: There are no checks in these routines that the relevant number of data bytes exist. */ + static int print_insn (pc, info, little) bfd_vma pc; struct disassemble_info * info; - boolean little; + bfd_boolean little; { unsigned char b[4]; long given; @@ -934,19 +1069,19 @@ print_insn (pc, info, little) if (info->disassembler_options) { parse_disassembler_options (info->disassembler_options); - + /* To avoid repeated parsing of these options, we remove them here. */ info->disassembler_options = NULL; } - + is_thumb = force_thumb; - + if (!is_thumb && info->symbols != NULL) { if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) { coff_symbol_type * cs; - + cs = coffsymbol (*info->symbols); is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT || cs->native->u.syment.n_sclass == C_THUMBSTAT @@ -958,14 +1093,14 @@ print_insn (pc, info, little) { elf_symbol_type * es; unsigned int type; - + es = *(elf_symbol_type **)(info->symbols); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); - + is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); } } - + info->bytes_per_chunk = 4; info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; @@ -975,17 +1110,17 @@ print_insn (pc, info, little) if (status != 0 && is_thumb) { info->bytes_per_chunk = 2; - + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); b[3] = b[2] = 0; } - + if (status != 0) { info->memory_error_func (status, pc, info); return -1; } - + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); } else @@ -997,13 +1132,13 @@ print_insn (pc, info, little) info->memory_error_func (status, pc, info); return -1; } - + if (is_thumb) { if (pc & 0x2) { given = (b[2] << 8) | b[3]; - + status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); if (status != 0) @@ -1011,7 +1146,7 @@ print_insn (pc, info, little) info->memory_error_func (status, pc + 4, info); return -1; } - + given |= (b[0] << 24) | (b[1] << 16); } else @@ -1020,7 +1155,15 @@ print_insn (pc, info, little) else given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); } - + + if (info->flags & INSN_HAS_RELOC) + /* If the instruction has a reloc associated with it, then + the offset field in the instruction will actually be the + addend for the reloc. (We are using REL type relocs). + In such cases, we can ignore the pc when computing + addresses, since the addend is not currently pc-relative. */ + pc = 0; + if (is_thumb) status = print_insn_thumb (pc, info, given); else @@ -1034,7 +1177,7 @@ print_insn_big_arm (pc, info) bfd_vma pc; struct disassemble_info * info; { - return print_insn (pc, info, false); + return print_insn (pc, info, FALSE); } int @@ -1042,7 +1185,7 @@ print_insn_little_arm (pc, info) bfd_vma pc; struct disassemble_info * info; { - return print_insn (pc, info, true); + return print_insn (pc, info, TRUE); } void @@ -1053,11 +1196,11 @@ print_arm_disassembler_options (FILE * stream) fprintf (stream, _("\n\ The following ARM specific disassembler options are supported for use with\n\ the -M switch:\n")); - + for (i = NUM_ARM_REGNAMES; i--;) fprintf (stream, " reg-names-%s %*c%s\n", regnames[i].name, - 14 - strlen (regnames[i].name), ' ', + (int)(14 - strlen (regnames[i].name)), ' ', regnames[i].description); fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");