X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Farm-dis.c;h=b926b65d6a23ab5a3a7b543e3b0afefd1b673808;hb=3cd7f3e3bdab2b9f5fa0005ce2b8333b46843c3e;hp=3763c1ee7c6fd62937c6e581c8625668ac3f50c1;hpb=9d82ec38013ba007963adfae2de0d1a88f965009;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 3763c1ee7c..b926b65d6a 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1,6 +1,5 @@ /* Instruction printing code for the ARM - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, - 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. + Copyright (C) 1994-2020 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) Modification by James G. Smith (jsmith@cygnus.co.uk) @@ -22,50 +21,382 @@ MA 02110-1301, USA. */ #include "sysdep.h" +#include -#include "dis-asm.h" +#include "disassemble.h" #include "opcode/arm.h" #include "opintl.h" #include "safe-ctype.h" +#include "libiberty.h" #include "floatformat.h" /* FIXME: This shouldn't be done here. */ #include "coff/internal.h" #include "libcoff.h" +#include "bfd.h" #include "elf-bfd.h" #include "elf/internal.h" #include "elf/arm.h" +#include "mach-o.h" /* FIXME: Belongs in global header. */ #ifndef strneq #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) #endif -#ifndef NUM_ELEM -#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) -#endif +/* Cached mapping symbol state. */ +enum map_type +{ + MAP_ARM, + MAP_THUMB, + MAP_DATA +}; struct arm_private_data { /* The features to use when disassembling optional instructions. */ arm_feature_set features; - /* Whether any mapping symbols are present in the provided symbol - table. -1 if we do not know yet, otherwise 0 or 1. */ - int has_mapping_symbols; + /* Track the last type (although this doesn't seem to be useful) */ + enum map_type last_type; + + /* Tracking symbol table information */ + int last_mapping_sym; + + /* The end range of the current range being disassembled. */ + bfd_vma last_stop_offset; + bfd_vma last_mapping_addr; +}; + +enum mve_instructions +{ + MVE_VPST, + MVE_VPT_FP_T1, + MVE_VPT_FP_T2, + MVE_VPT_VEC_T1, + MVE_VPT_VEC_T2, + MVE_VPT_VEC_T3, + MVE_VPT_VEC_T4, + MVE_VPT_VEC_T5, + MVE_VPT_VEC_T6, + MVE_VCMP_FP_T1, + MVE_VCMP_FP_T2, + MVE_VCMP_VEC_T1, + MVE_VCMP_VEC_T2, + MVE_VCMP_VEC_T3, + MVE_VCMP_VEC_T4, + MVE_VCMP_VEC_T5, + MVE_VCMP_VEC_T6, + MVE_VDUP, + MVE_VEOR, + MVE_VFMAS_FP_SCALAR, + MVE_VFMA_FP_SCALAR, + MVE_VFMA_FP, + MVE_VFMS_FP, + MVE_VHADD_T1, + MVE_VHADD_T2, + MVE_VHSUB_T1, + MVE_VHSUB_T2, + MVE_VRHADD, + MVE_VLD2, + MVE_VLD4, + MVE_VST2, + MVE_VST4, + MVE_VLDRB_T1, + MVE_VLDRH_T2, + MVE_VLDRB_T5, + MVE_VLDRH_T6, + MVE_VLDRW_T7, + MVE_VSTRB_T1, + MVE_VSTRH_T2, + MVE_VSTRB_T5, + MVE_VSTRH_T6, + MVE_VSTRW_T7, + MVE_VLDRB_GATHER_T1, + MVE_VLDRH_GATHER_T2, + MVE_VLDRW_GATHER_T3, + MVE_VLDRD_GATHER_T4, + MVE_VLDRW_GATHER_T5, + MVE_VLDRD_GATHER_T6, + MVE_VSTRB_SCATTER_T1, + MVE_VSTRH_SCATTER_T2, + MVE_VSTRW_SCATTER_T3, + MVE_VSTRD_SCATTER_T4, + MVE_VSTRW_SCATTER_T5, + MVE_VSTRD_SCATTER_T6, + MVE_VCVT_FP_FIX_VEC, + MVE_VCVT_BETWEEN_FP_INT, + MVE_VCVT_FP_HALF_FP, + MVE_VCVT_FROM_FP_TO_INT, + MVE_VRINT_FP, + MVE_VMOV_HFP_TO_GP, + MVE_VMOV_GP_TO_VEC_LANE, + MVE_VMOV_IMM_TO_VEC, + MVE_VMOV_VEC_TO_VEC, + MVE_VMOV2_VEC_LANE_TO_GP, + MVE_VMOV2_GP_TO_VEC_LANE, + MVE_VMOV_VEC_LANE_TO_GP, + MVE_VMVN_IMM, + MVE_VMVN_REG, + MVE_VORR_IMM, + MVE_VORR_REG, + MVE_VORN, + MVE_VBIC_IMM, + MVE_VBIC_REG, + MVE_VMOVX, + MVE_VMOVL, + MVE_VMOVN, + MVE_VMULL_INT, + MVE_VMULL_POLY, + MVE_VQDMULL_T1, + MVE_VQDMULL_T2, + MVE_VQMOVN, + MVE_VQMOVUN, + MVE_VADDV, + MVE_VMLADAV_T1, + MVE_VMLADAV_T2, + MVE_VMLALDAV, + MVE_VMLAS, + MVE_VADDLV, + MVE_VMLSDAV_T1, + MVE_VMLSDAV_T2, + MVE_VMLSLDAV, + MVE_VRMLALDAVH, + MVE_VRMLSLDAVH, + MVE_VQDMLADH, + MVE_VQRDMLADH, + MVE_VQDMLAH, + MVE_VQRDMLAH, + MVE_VQDMLASH, + MVE_VQRDMLASH, + MVE_VQDMLSDH, + MVE_VQRDMLSDH, + MVE_VQDMULH_T1, + MVE_VQRDMULH_T2, + MVE_VQDMULH_T3, + MVE_VQRDMULH_T4, + MVE_VDDUP, + MVE_VDWDUP, + MVE_VIWDUP, + MVE_VIDUP, + MVE_VCADD_FP, + MVE_VCADD_VEC, + MVE_VHCADD, + MVE_VCMLA_FP, + MVE_VCMUL_FP, + MVE_VQRSHL_T1, + MVE_VQRSHL_T2, + MVE_VQRSHRN, + MVE_VQRSHRUN, + MVE_VQSHL_T1, + MVE_VQSHL_T2, + MVE_VQSHLU_T3, + MVE_VQSHL_T4, + MVE_VQSHRN, + MVE_VQSHRUN, + MVE_VRSHL_T1, + MVE_VRSHL_T2, + MVE_VRSHR, + MVE_VRSHRN, + MVE_VSHL_T1, + MVE_VSHL_T2, + MVE_VSHL_T3, + MVE_VSHLC, + MVE_VSHLL_T1, + MVE_VSHLL_T2, + MVE_VSHR, + MVE_VSHRN, + MVE_VSLI, + MVE_VSRI, + MVE_VADC, + MVE_VABAV, + MVE_VABD_FP, + MVE_VABD_VEC, + MVE_VABS_FP, + MVE_VABS_VEC, + MVE_VADD_FP_T1, + MVE_VADD_FP_T2, + MVE_VADD_VEC_T1, + MVE_VADD_VEC_T2, + MVE_VSBC, + MVE_VSUB_FP_T1, + MVE_VSUB_FP_T2, + MVE_VSUB_VEC_T1, + MVE_VSUB_VEC_T2, + MVE_VAND, + MVE_VBRSR, + MVE_VCLS, + MVE_VCLZ, + MVE_VCTP, + MVE_VMAX, + MVE_VMAXA, + MVE_VMAXNM_FP, + MVE_VMAXNMA_FP, + MVE_VMAXNMV_FP, + MVE_VMAXNMAV_FP, + MVE_VMAXV, + MVE_VMAXAV, + MVE_VMIN, + MVE_VMINA, + MVE_VMINNM_FP, + MVE_VMINNMA_FP, + MVE_VMINNMV_FP, + MVE_VMINNMAV_FP, + MVE_VMINV, + MVE_VMINAV, + MVE_VMLA, + MVE_VMUL_FP_T1, + MVE_VMUL_FP_T2, + MVE_VMUL_VEC_T1, + MVE_VMUL_VEC_T2, + MVE_VMULH, + MVE_VRMULH, + MVE_VNEG_FP, + MVE_VNEG_VEC, + MVE_VPNOT, + MVE_VPSEL, + MVE_VQABS, + MVE_VQADD_T1, + MVE_VQADD_T2, + MVE_VQSUB_T1, + MVE_VQSUB_T2, + MVE_VQNEG, + MVE_VREV16, + MVE_VREV32, + MVE_VREV64, + MVE_LSLL, + MVE_LSLLI, + MVE_LSRL, + MVE_ASRL, + MVE_ASRLI, + MVE_SQRSHRL, + MVE_SQRSHR, + MVE_UQRSHL, + MVE_UQRSHLL, + MVE_UQSHL, + MVE_UQSHLL, + MVE_URSHRL, + MVE_URSHR, + MVE_SRSHRL, + MVE_SRSHR, + MVE_SQSHLL, + MVE_SQSHL, + MVE_CINC, + MVE_CINV, + MVE_CNEG, + MVE_CSINC, + MVE_CSINV, + MVE_CSET, + MVE_CSETM, + MVE_CSNEG, + MVE_CSEL, + MVE_NONE +}; + +enum mve_unpredictable +{ + UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block. + */ + UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and + fcB = 1 (vpt). */ + UNPRED_R13, /* Unpredictable because r13 (sp) or + r15 (sp) used. */ + UNPRED_R15, /* Unpredictable because r15 (pc) is used. */ + UNPRED_Q_GT_4, /* Unpredictable because + vec reg start > 4 (vld4/st4). */ + UNPRED_Q_GT_6, /* Unpredictable because + vec reg start > 6 (vld2/st2). */ + UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13 + and WB bit = 1. */ + UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are + equal. */ + UNPRED_OS, /* Unpredictable because offset scaled == 1. */ + UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the + same. */ + UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and + size = 1. */ + UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and + size = 2. */ + UNPRED_NONE /* No unpredictable behavior. */ +}; + +enum mve_undefined +{ + UNDEF_SIZE, /* undefined size. */ + UNDEF_SIZE_0, /* undefined because size == 0. */ + UNDEF_SIZE_2, /* undefined because size == 2. */ + UNDEF_SIZE_3, /* undefined because size == 3. */ + UNDEF_SIZE_LE_1, /* undefined because size <= 1. */ + UNDEF_SIZE_NOT_0, /* undefined because size != 0. */ + UNDEF_SIZE_NOT_2, /* undefined because size != 2. */ + UNDEF_SIZE_NOT_3, /* undefined because size != 3. */ + UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and + size == 0. */ + UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and + size == 1. */ + UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */ + UNDEF_VCVT_IMM6, /* imm6 < 32. */ + UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */ + UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and + op1 == (0 or 1). */ + UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and + op2 == 0 and op1 == (0 or 1). */ + UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode + in {0xx1, x0x1}. */ + UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */ + UNDEF_NONE /* no undefined behavior. */ }; struct opcode32 { - unsigned long arch; /* Architecture defining this insn. */ - unsigned long value; /* If arch == 0 then value is a sentinel. */ + arm_feature_set arch; /* Architecture defining this insn. */ + unsigned long value; /* If arch is 0 then value is a sentinel. */ + unsigned long mask; /* Recognise insn if (op & mask) == value. */ + const char * assembler; /* How to disassemble this insn. */ +}; + +struct cdeopcode32 +{ + arm_feature_set arch; /* Architecture defining this insn. */ + uint8_t coproc_shift; /* coproc is this far into op. */ + uint16_t coproc_mask; /* Length of coproc field in op. */ + unsigned long value; /* If arch is 0 then value is a sentinel. */ + unsigned long mask; /* Recognise insn if (op & mask) == value. */ + const char * assembler; /* How to disassemble this insn. */ +}; + +/* MVE opcodes. */ + +struct mopcode32 +{ + arm_feature_set arch; /* Architecture defining this insn. */ + enum mve_instructions mve_op; /* Specific mve instruction for faster + decoding. */ + unsigned long value; /* If arch is 0 then value is a sentinel. */ + unsigned long mask; /* Recognise insn if (op & mask) == value. */ + const char * assembler; /* How to disassemble this insn. */ +}; + +enum isa { + ANY, + T32, + ARM +}; + + +/* Shared (between Arm and Thumb mode) opcode. */ +struct sopcode32 +{ + enum isa isa; /* Execution mode instruction availability. */ + arm_feature_set arch; /* Architecture defining this insn. */ + unsigned long value; /* If arch is 0 then value is a sentinel. */ unsigned long mask; /* Recognise insn if (op & mask) == value. */ const char * assembler; /* How to disassemble this insn. */ }; struct opcode16 { - unsigned long arch; /* Architecture defining this insn. */ + arm_feature_set arch; /* Architecture defining this insn. */ unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ const char *assembler; /* How to disassemble this insn. */ }; @@ -75,16 +406,22 @@ struct opcode16 %% % %c print condition code (always bits 28-31 in ARM mode) + %b print condition code allowing cp_num == 9 %q print shifter argument - %u print condition code (unconditional in ARM mode) + %u print condition code (unconditional in ARM mode, + UNPREDICTABLE if not AL in Thumb) %A print address for ldc/stc/ldf/stf instruction %B print vstm/vldm register list + %C print vscclrm register list %I print cirrus signed shift immediate: bits 0..3|4..6 + %J print register for VLDR instruction + %K print address for VLDR instruction %F print the COUNT field of a LFM/SFM instruction. %P print floating point precision in arithmetic insn %Q print floating point precision in ldf/stf insn %R print floating point rounding mode + %c print as a condition code (for vsel) %r print as an ARM register %R as %<>r but r15 is UNPREDICTABLE %ru as %<>r but each u register must be unique. @@ -99,6 +436,8 @@ struct opcode16 %G print as an iWMMXt general purpose or control register %D print as a NEON D register %Q print as a NEON Q register + %V print as a NEON D or Q register + %E print a quarter-float immediate value %y print a single precision VFP reg. Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair @@ -108,7 +447,7 @@ struct opcode16 %'c print specified char iff bitfield is all ones %`c print specified char iff bitfield is all zeroes %?ab... select from array of values in big endian order - + %L print as an iWMMXt N/M width field. %Z print the Immediate of a WSHUFH instruction. %l like 'A' except use byte offsets for 'B' & 'H' @@ -125,372 +464,990 @@ enum opcode_sentinel_enum } opcode_sentinels; #define UNDEFINED_INSTRUCTION "\t\t; instruction: %0-31x" +#define UNKNOWN_INSTRUCTION_32BIT "\t\t; instruction: %08x" +#define UNKNOWN_INSTRUCTION_16BIT "\t\t; instruction: %04x" #define UNPREDICTABLE_INSTRUCTION "\t; " /* Common coprocessor opcodes shared between Arm and Thumb-2. */ -static const struct opcode32 coprocessor_opcodes[] = +/* print_insn_cde recognizes the following format control codes: + + %% % + + %a print 'a' iff bit 28 is 1 + %p print bits 8-10 as coprocessor + %d print as decimal + %r print as an ARM register + %n print as an ARM register but r15 is APSR_nzcv + %T print as an ARM register + 1 + %R as %r but r13 is UNPREDICTABLE + %S as %r but rX where X > 10 is UNPREDICTABLE + %j print immediate taken from bits (16..21,7,0..5) + %k print immediate taken from bits (20..21,7,0..5). + %l print immediate taken from bits (20..22,7,4..5). */ + +/* At the moment there is only one valid position for the coprocessor number, + and hence that's encoded in the macro below. */ +#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \ + { ARCH, 8, 7, VALUE, MASK, ASM } +static const struct cdeopcode32 cde_opcodes[] = +{ + /* Custom Datapath Extension instructions. */ + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xee000000, 0xefc00840, + "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"), + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xee000040, 0xefc00840, + "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"), + + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xee400000, 0xefc00840, + "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"), + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xee400040, 0xefc00840, + "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"), + + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xee800000, 0xef800840, + "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"), + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xee800040, 0xef800840, + "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"), + + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xec200000, 0xeeb00840, + "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"), + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xec200040, 0xeeb00840, + "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"), + + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xec300000, 0xeeb00840, + "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"), + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xec300040, 0xeeb00840, + "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"), + + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xec800000, 0xee800840, + "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"), + CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), + 0xec800040, 0xee800840, + "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"), + + CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0) + +}; + +static const struct sopcode32 coprocessor_opcodes[] = { /* XScale instructions. */ - {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, - {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200010, 0x0fff0ff0, + "mia%c\tacc0, %0-3r, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e280010, 0x0fff0ff0, + "miaph%c\tacc0, %0-3r, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, /* Intel Wireless MMX technology instructions. */ - { 0, SENTINEL_IWMMXT_START, 0, "" }, - {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, - {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, - {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, - {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, - {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, - {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, - {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, - {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, - {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, - {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, - {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, - {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, - {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, - {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, - {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, - {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, - {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, - {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, - {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, - {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, - {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, - {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, - {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, - {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, - {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, - {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, - {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, - { 0, SENTINEL_IWMMXT_END, 0, "" }, + {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), + 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e800120, 0x0f800ff0, + "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e8000a0, 0x0f800ff0, + "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), + 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, + {ANY, ARM_FEATURE_CORE_LOW (0), + SENTINEL_IWMMXT_END, 0, "" }, /* Floating point coprocessor (FPA) instructions. */ - {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, - {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, - {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, - {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, - {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, - {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, - {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, - {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, - {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, - {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, - {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), + 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), + 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, + {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), + 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + + /* Armv8.1-M Mainline instructions. */ + {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"}, + {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"}, + + /* ARMv8-M Mainline Security Extensions instructions. */ + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), + 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), + 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, /* Register load/store. */ - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, - {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, - {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, - {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, - {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, - {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, - {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, - {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, - {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, - {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, - - {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, - {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, - {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, - {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), + 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), + 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"}, + {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), + 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"}, + + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, /* Data transfer between ARM and NEON registers. */ - {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, - {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, - {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, - {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, - {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, - {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, - {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, - {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, /* Half-precision conversion instructions. */ - {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, - {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), + 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), + 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, /* Floating point coprocessor (VFP) instructions. */ - {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, - {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, - {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, - {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, - {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, - {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, - {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, - {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, - {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, - {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, - {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, "}, - {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, - {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, - {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, - {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, - {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, - {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, - {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, - {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, - {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, - {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, - {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, - {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, - {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"}, - {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"}, - {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, - {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, - {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, - {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, + {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), + 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, + {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), + 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ee00a10, 0x0ff00fff, "vmsr%c\t, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, "}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), + 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), + 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), + 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), + 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), + 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), + 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), + 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), + 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), + 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), + 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), + 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, /* Cirrus coprocessor instructions. */ - {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, - {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, - {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, - {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, - {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, - {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, - {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, - {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, - {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e000600, 0x0ff00f10, + "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e100600, 0x0ff00f10, + "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e200600, 0x0ff00f10, + "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), + 0x0e300600, 0x0ff00f10, + "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, /* VFP Fused multiply add instructions. */ - {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, - {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, - {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), + 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, + + /* FP v5. */ + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, + {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), + 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, + + {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, + /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, + + /* BFloat16 instructions. */ + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), + 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"}, + + /* Dot Product instructions in the space of coprocessor 13. */ + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), + 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, + {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), + 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, + + /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, + + /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. + cp_num: bit <11:8> == 0b1001. + cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, + + /* ARMv8.3 javascript conversion instruction. */ + {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), + 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, + + {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} +}; +/* Generic coprocessor instructions. These are only matched if a more specific + SIMD or co-processor instruction does not match first. */ + +static const struct sopcode32 generic_coprocessor_opcodes[] = +{ /* Generic coprocessor instructions. */ - { 0, SENTINEL_GENERIC_START, 0, "" }, - {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, - {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, - {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0x0c500000, 0x0ff00000, + "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0e000000, 0x0f000010, + "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0e10f010, 0x0f10f010, + "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0e100010, 0x0f100010, + "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0e000010, 0x0f100010, + "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, /* V6 coprocessor instructions. */ - {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, - {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xfc500000, 0xfff00000, + "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xfc400000, 0xfff00000, + "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, /* V5 coprocessor instructions. */ - {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, - {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, - {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, - - {0, 0, 0, 0} + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfe000000, 0xff000010, + "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfe000010, 0xff100010, + "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, + {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfe100010, 0xff100010, + "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + + {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} }; /* Neon opcode table: This does not encode the top byte -- that is @@ -502,6 +1459,8 @@ static const struct opcode32 coprocessor_opcodes[] = %% % %c print condition code + %u print condition code (unconditional in ARM mode, + UNPREDICTABLE if not AL in Thumb) %A print v{st,ld}[1234] operands %B print v{st,ld}[1234] any one operands %C print v{st,ld}[1234] single->all operands @@ -518,7 +1477,7 @@ static const struct opcode32 coprocessor_opcodes[] = %Sn print byte scaled width limited by n %Tn print short scaled width limited by n %Un print long scaled width limited by n - + %'c print specified char iff bitfield is all ones %`c print specified char iff bitfield is all zeroes %?ab... select from array of values in big endian order. */ @@ -526,256 +1485,2136 @@ static const struct opcode32 coprocessor_opcodes[] = static const struct opcode32 neon_opcodes[] = { /* Extract. */ - {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, - {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2b00840, 0xffb00850, + "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2b00000, 0xffb00810, + "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, + + /* Data transfer between ARM and NEON registers. */ + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, /* Move data element to all lanes. */ - {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, - {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, - {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, /* Table lookup. */ - {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, - + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, + /* Half-precision conversions. */ - {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, - {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), + 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), + 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, /* NEON fused multiply add instructions. */ - {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), + 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), + 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + + /* BFloat16 instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), + 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), + 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), + 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), + 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), + 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), + 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"}, + + /* Matrix Multiply instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), + 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), + 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), + 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), + 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), + 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), + 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"}, /* Two registers, miscellaneous. */ - {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, - {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, - {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), + 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), + 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20300, 0xffb30fd0, + "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3bb0600, 0xffbf0e10, + "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3b70600, 0xffbf0e10, + "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, /* Three registers of the same length. */ - {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, - {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, - {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, - {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, - {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, - {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), + 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), + 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000b00, 0xff800f10, + "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000b10, 0xff800f10, + "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3000b00, 0xff800f10, + "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000000, 0xfe800f10, + "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000010, 0xfe800f10, + "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000100, 0xfe800f10, + "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000200, 0xfe800f10, + "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000210, 0xfe800f10, + "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000300, 0xfe800f10, + "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000310, 0xfe800f10, + "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000400, 0xfe800f10, + "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000410, 0xfe800f10, + "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000500, 0xfe800f10, + "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000510, 0xfe800f10, + "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000600, 0xfe800f10, + "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000610, 0xfe800f10, + "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000700, 0xfe800f10, + "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000710, 0xfe800f10, + "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000910, 0xfe800f10, + "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000a00, 0xfe800f10, + "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2000a10, 0xfe800f10, + "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), + 0xf3000b10, 0xff800f10, + "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), + 0xf3000c10, 0xff800f10, + "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, /* One register and an immediate value. */ - {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, - {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, /* Two registers and a shift amount. */ - {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, - {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, - {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, - {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, - {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, - {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, - {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, - {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, - {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, - {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, - {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, - {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880950, 0xfeb80fd0, + "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900950, 0xfeb00fd0, + "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00950, 0xfea00fd0, + "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2a00e10, 0xfea00e90, + "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), + 0xf2a00c10, 0xfea00e90, + "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"}, /* Three registers of different lengths. */ - {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, - {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, - {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), + 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800400, 0xff800f50, + "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800600, 0xff800f50, + "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800900, 0xff800f50, + "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800b00, 0xff800f50, + "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800d00, 0xff800f50, + "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800400, 0xff800f50, + "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800600, 0xff800f50, + "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800000, 0xfe800f50, + "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800100, 0xfe800f50, + "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800200, 0xfe800f50, + "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800300, 0xfe800f50, + "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800500, 0xfe800f50, + "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800700, 0xfe800f50, + "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800800, 0xfe800f50, + "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800a00, 0xfe800f50, + "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800c00, 0xfe800f50, + "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, /* Two registers and a scalar. */ - {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, - {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, - {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), + 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), + 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), + 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), + 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), + 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), + 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800240, 0xfe800f50, + "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800640, 0xfe800f50, + "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf2800a40, 0xfe800f50, + "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), + 0xf2800e40, 0xff800f50, + "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), + 0xf2800f40, 0xff800f50, + "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), + 0xf3800e40, 0xff800f50, + "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), + 0xf3800f40, 0xff800f50, + "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" + }, /* Element and structure load/store. */ - {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, - {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, - {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, - {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, - {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, - {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, - {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, - {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, - {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, - {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, - {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, - - {0,0 ,0, 0} + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, + {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), + 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, + + {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} +}; + +/* mve opcode table. */ + +/* print_insn_mve recognizes the following format control codes: + + %% % + + %a print '+' or '-' or imm offset in vldr[bhwd] and + vstr[bhwd] + %c print condition code + %d print addr mode of MVE vldr[bhw] and vstr[bhw] + %u print 'U' (unsigned) or 'S' for various mve instructions + %i print MVE predicate(s) for vpt and vpst + %j print a 5-bit immediate from hw2[14:12,7:6] + %k print 48 if the 7th position bit is set else print 64. + %m print rounding mode for vcvt and vrint + %n print vector comparison code for predicated instruction + %s print size for various vcvt instructions + %v print vector predicate for instruction in predicated + block + %o print offset scaled for vldr[hwd] and vstr[hwd] + %w print writeback mode for MVE v{st,ld}[24] + %B print v{st,ld}[24] any one operands + %E print vmov, vmvn, vorr, vbic encoded constant + %N print generic index for vmov + %T print bottom ('b') or top ('t') of source register + %X print exchange field in vmla* instructions + + %r print as an ARM register + %d print the bitfield in decimal + %A print accumulate or not + %c print bitfield as a condition code + %C print bitfield as an inverted condition code + %Q print as a MVE Q register + %F print as a MVE S register + %Z as %<>r but r15 is ZR instead of PC and r13 is + UNPREDICTABLE + + %S as %<>r but r15 or r13 is UNPREDICTABLE + %s print size for vector predicate & non VMOV instructions + %I print carry flag or not + %i print immediate for vstr/vldr reg +/- imm + %h print high half of 64-bit destination reg + %k print immediate for vector conversion instruction + %l print low half of 64-bit destination reg + %o print rotate value for vcmul + %u print immediate value for vddup/vdwdup + %x print the bitfield in hex. + */ + +static const struct mopcode32 mve_opcodes[] = +{ + /* MVE. */ + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPST, + 0xfe310f4d, 0xffbf1fff, + "vpst%i" + }, + + /* Floating point VPT T1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VPT_FP_T1, + 0xee310f00, 0xefb10f50, + "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"}, + /* Floating point VPT T2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VPT_FP_T2, + 0xee310f40, 0xefb10f50, + "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"}, + + /* Vector VPT T1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPT_VEC_T1, + 0xfe010f00, 0xff811f51, + "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, + /* Vector VPT T2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPT_VEC_T2, + 0xfe010f01, 0xff811f51, + "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, + /* Vector VPT T3. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPT_VEC_T3, + 0xfe011f00, 0xff811f50, + "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, + /* Vector VPT T4. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPT_VEC_T4, + 0xfe010f40, 0xff811f70, + "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"}, + /* Vector VPT T5. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPT_VEC_T5, + 0xfe010f60, 0xff811f70, + "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"}, + /* Vector VPT T6. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPT_VEC_T6, + 0xfe011f40, 0xff811f50, + "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"}, + + /* Vector VBIC immediate. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VBIC_IMM, + 0xef800070, 0xefb81070, + "vbic%v.i%8-11s\t%13-15,22Q, %E"}, + + /* Vector VBIC register. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VBIC_REG, + 0xef100150, 0xffb11f51, + "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VABAV. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VABAV, + 0xee800f01, 0xefc10f51, + "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"}, + + /* Vector VABD floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VABD_FP, + 0xff200d40, 0xffa11f51, + "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VABD. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VABD_VEC, + 0xef000740, 0xef811f51, + "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VABS floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VABS_FP, + 0xFFB10740, 0xFFB31FD1, + "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, + /* Vector VABS. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VABS_VEC, + 0xffb10340, 0xffb31fd1, + "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VADD floating point T1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VADD_FP_T1, + 0xef000d40, 0xffa11f51, + "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + /* Vector VADD floating point T2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VADD_FP_T2, + 0xee300f40, 0xefb11f70, + "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + /* Vector VADD T1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VADD_VEC_T1, + 0xef000840, 0xff811f51, + "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + /* Vector VADD T2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VADD_VEC_T2, + 0xee010f40, 0xff811f70, + "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VADDLV. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VADDLV, + 0xee890f00, 0xef8f1fd1, + "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"}, + + /* Vector VADDV. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VADDV, + 0xeef10f00, 0xeff31fd1, + "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"}, + + /* Vector VADC. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VADC, + 0xee300f00, 0xffb10f51, + "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VAND. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VAND, + 0xef000150, 0xffb11f51, + "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VBRSR register. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VBRSR, + 0xfe011e60, 0xff811f70, + "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VCADD floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCADD_FP, + 0xfc800840, 0xfea11f51, + "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"}, + + /* Vector VCADD. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCADD_VEC, + 0xfe000f00, 0xff810f51, + "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"}, + + /* Vector VCLS. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCLS, + 0xffb00440, 0xffb31fd1, + "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VCLZ. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCLZ, + 0xffb004c0, 0xffb31fd1, + "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VCMLA. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCMLA_FP, + 0xfc200840, 0xfe211f51, + "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"}, + + /* Vector VCMP floating point T1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCMP_FP_T1, + 0xee310f00, 0xeff1ef50, + "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"}, + + /* Vector VCMP floating point T2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCMP_FP_T2, + 0xee310f40, 0xeff1ef50, + "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"}, + + /* Vector VCMP T1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCMP_VEC_T1, + 0xfe010f00, 0xffc1ff51, + "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, + /* Vector VCMP T2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCMP_VEC_T2, + 0xfe010f01, 0xffc1ff51, + "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, + /* Vector VCMP T3. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCMP_VEC_T3, + 0xfe011f00, 0xffc1ff50, + "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, + /* Vector VCMP T4. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCMP_VEC_T4, + 0xfe010f40, 0xffc1ff70, + "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"}, + /* Vector VCMP T5. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCMP_VEC_T5, + 0xfe010f60, 0xffc1ff70, + "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"}, + /* Vector VCMP T6. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCMP_VEC_T6, + 0xfe011f40, 0xffc1ff50, + "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"}, + + /* Vector VDUP. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VDUP, + 0xeea00b10, 0xffb10f5f, + "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, + + /* Vector VEOR. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VEOR, + 0xff000150, 0xffd11f51, + "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VFMA, vector * scalar. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VFMA_FP_SCALAR, + 0xee310e40, 0xefb11f70, + "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VFMA floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VFMA_FP, + 0xef000c50, 0xffa11f51, + "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VFMS floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VFMS_FP, + 0xef200c50, 0xffa11f51, + "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VFMAS, vector * scalar. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VFMAS_FP_SCALAR, + 0xee311e40, 0xefb11f70, + "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VHADD T1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VHADD_T1, + 0xef000040, 0xef811f51, + "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VHADD T2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VHADD_T2, + 0xee000f40, 0xef811f70, + "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VHSUB T1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VHSUB_T1, + 0xef000240, 0xef811f51, + "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VHSUB T2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VHSUB_T2, + 0xee001f40, 0xef811f70, + "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VCMUL. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCMUL_FP, + 0xee300e00, 0xefb10f50, + "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"}, + + /* Vector VCTP. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VCTP, + 0xf000e801, 0xffc0ffff, + "vctp%v.%20-21s\t%16-19r"}, + + /* Vector VDUP. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VDUP, + 0xeea00b10, 0xffb10f5f, + "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, + + /* Vector VRHADD. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRHADD, + 0xef000140, 0xef811f51, + "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VCVT. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCVT_FP_FIX_VEC, + 0xef800c50, 0xef801cd1, + "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"}, + + /* Vector VCVT. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCVT_BETWEEN_FP_INT, + 0xffb30640, 0xffb31e51, + "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VCVT between single and half-precision float, bottom half. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCVT_FP_HALF_FP, + 0xee3f0e01, 0xefbf1fd1, + "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VCVT between single and half-precision float, top half. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCVT_FP_HALF_FP, + 0xee3f1e01, 0xefbf1fd1, + "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VCVT. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VCVT_FROM_FP_TO_INT, + 0xffb30040, 0xffb31c51, + "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VDDUP. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VDDUP, + 0xee011f6e, 0xff811f7e, + "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"}, + + /* Vector VDWDUP. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VDWDUP, + 0xee011f60, 0xff811f70, + "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"}, + + /* Vector VHCADD. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VHCADD, + 0xee000f00, 0xff810f51, + "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"}, + + /* Vector VIWDUP. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VIWDUP, + 0xee010f60, 0xff811f70, + "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"}, + + /* Vector VIDUP. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VIDUP, + 0xee010f6e, 0xff811f7e, + "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"}, + + /* Vector VLD2. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLD2, + 0xfc901e00, 0xff901e5f, + "vld2%5d.%7-8s\t%B, [%16-19r]%w"}, + + /* Vector VLD4. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLD4, + 0xfc901e01, 0xff901e1f, + "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"}, + + /* Vector VLDRB gather load. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRB_GATHER_T1, + 0xec900e00, 0xefb01e50, + "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, + + /* Vector VLDRH gather load. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRH_GATHER_T2, + 0xec900e10, 0xefb01e50, + "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, + + /* Vector VLDRW gather load. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRW_GATHER_T3, + 0xfc900f40, 0xffb01fd0, + "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, + + /* Vector VLDRD gather load. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRD_GATHER_T4, + 0xec900fd0, 0xefb01fd0, + "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, + + /* Vector VLDRW gather load. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRW_GATHER_T5, + 0xfd101e00, 0xff111f00, + "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, + + /* Vector VLDRD gather load, variant T6. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRD_GATHER_T6, + 0xfd101f00, 0xff111f00, + "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, + + /* Vector VLDRB. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRB_T1, + 0xec100e00, 0xee581e00, + "vldrb%v.%u%7-8s\t%13-15Q, %d"}, + + /* Vector VLDRH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRH_T2, + 0xec180e00, 0xee581e00, + "vldrh%v.%u%7-8s\t%13-15Q, %d"}, + + /* Vector VLDRB unsigned, variant T5. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRB_T5, + 0xec101e00, 0xfe101f80, + "vldrb%v.u8\t%13-15,22Q, %d"}, + + /* Vector VLDRH unsigned, variant T6. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRH_T6, + 0xec101e80, 0xfe101f80, + "vldrh%v.u16\t%13-15,22Q, %d"}, + + /* Vector VLDRW unsigned, variant T7. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VLDRW_T7, + 0xec101f00, 0xfe101f80, + "vldrw%v.u32\t%13-15,22Q, %d"}, + + /* Vector VMAX. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMAX, + 0xef000640, 0xef811f51, + "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMAXA. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMAXA, + 0xee330e81, 0xffb31fd1, + "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VMAXNM floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMAXNM_FP, + 0xff000f50, 0xffa11f51, + "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMAXNMA floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMAXNMA_FP, + 0xee3f0e81, 0xefbf1fd1, + "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VMAXNMV floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMAXNMV_FP, + 0xeeee0f00, 0xefff0fd1, + "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"}, + + /* Vector VMAXNMAV floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMAXNMAV_FP, + 0xeeec0f00, 0xefff0fd1, + "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"}, + + /* Vector VMAXV. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMAXV, + 0xeee20f00, 0xeff30fd1, + "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, + + /* Vector VMAXAV. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMAXAV, + 0xeee00f00, 0xfff30fd1, + "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"}, + + /* Vector VMIN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMIN, + 0xef000650, 0xef811f51, + "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMINA. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMINA, + 0xee331e81, 0xffb31fd1, + "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VMINNM floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMINNM_FP, + 0xff200f50, 0xffa11f51, + "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMINNMA floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMINNMA_FP, + 0xee3f1e81, 0xefbf1fd1, + "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VMINNMV floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMINNMV_FP, + 0xeeee0f80, 0xefff0fd1, + "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"}, + + /* Vector VMINNMAV floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMINNMAV_FP, + 0xeeec0f80, 0xefff0fd1, + "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"}, + + /* Vector VMINV. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMINV, + 0xeee20f80, 0xeff30fd1, + "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, + + /* Vector VMINAV. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMINAV, + 0xeee00f80, 0xfff30fd1, + "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"}, + + /* Vector VMLA. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLA, + 0xee010e40, 0xef811f70, + "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction + opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLALDAV, + 0xee801e00, 0xef801f51, + "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLALDAV, + 0xee800e00, 0xef801f51, + "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, + + /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLADAV_T1, + 0xeef00e00, 0xeff01f51, + "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, + + /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLADAV_T2, + 0xeef00f00, 0xeff11f51, + "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, + + /* Vector VMLADAV T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLADAV_T1, + 0xeef01e00, 0xeff01f51, + "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, + + /* Vector VMLADAV T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLADAV_T2, + 0xeef01f00, 0xeff11f51, + "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, + + /* Vector VMLAS. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLAS, + 0xee011e40, 0xef811f70, + "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction + opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRMLSLDAVH, + 0xfe800e01, 0xff810f51, + "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, + + /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction + opcdoe aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLSLDAV, + 0xee800e01, 0xff800f51, + "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, + + /* Vector VMLSDAV T1 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLSDAV_T1, + 0xeef00e01, 0xfff00f51, + "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"}, + + /* Vector VMLSDAV T2 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMLSDAV_T2, + 0xfef00e01, 0xfff10f51, + "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"}, + + /* Vector VMOV between gpr and half precision register, op == 0. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMOV_HFP_TO_GP, + 0xee000910, 0xfff00f7f, + "vmov.f16\t%7,16-19F, %12-15r"}, + + /* Vector VMOV between gpr and half precision register, op == 1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMOV_HFP_TO_GP, + 0xee100910, 0xfff00f7f, + "vmov.f16\t%12-15r, %7,16-19F"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMOV_GP_TO_VEC_LANE, + 0xee000b10, 0xff900f1f, + "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"}, + + /* Vector VORR immediate to vector. + NOTE: MVE_VORR_IMM must appear in the table + before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VORR_IMM, + 0xef800050, 0xefb810f0, + "vorr%v.i%8-11s\t%13-15,22Q, %E"}, + + /* Vector VQSHL T2 Variant. + NOTE: MVE_VQSHL_T2 must appear in the table before + before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQSHL_T2, + 0xef800750, 0xef801fd1, + "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VQSHLU T3 Variant + NOTE: MVE_VQSHL_T2 must appear in the table before + before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQSHLU_T3, + 0xff800650, 0xff801fd1, + "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VRSHR + NOTE: MVE_VRSHR must appear in the table before + before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRSHR, + 0xef800250, 0xef801fd1, + "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VSHL. + NOTE: MVE_VSHL must appear in the table before + before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSHL_T1, + 0xef800550, 0xff801fd1, + "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VSHR + NOTE: MVE_VSHR must appear in the table before + before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSHR, + 0xef800050, 0xef801fd1, + "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VSLI + NOTE: MVE_VSLI must appear in the table before + before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSLI, + 0xff800550, 0xff801fd1, + "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VSRI + NOTE: MVE_VSRI must appear in the table before + before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSRI, + 0xff800450, 0xff801fd1, + "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VMOV immediate to vector, + undefinded for cmode == 1111 */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION}, + + /* Vector VMOV immediate to vector, + cmode == 1101 */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0, + "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, + + /* Vector VMOV immediate to vector. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOV_IMM_TO_VEC, + 0xef800050, 0xefb810d0, + "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, + + /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOV2_VEC_LANE_TO_GP, + 0xec000f00, 0xffb01ff0, + "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"}, + + /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOV2_VEC_LANE_TO_GP, + 0xec000f10, 0xffb01ff0, + "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"}, + + /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOV2_GP_TO_VEC_LANE, + 0xec100f00, 0xffb01ff0, + "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"}, + + /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOV2_GP_TO_VEC_LANE, + 0xec100f10, 0xffb01ff0, + "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"}, + + /* Vector VMOV Vector lane to gpr. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMOV_VEC_LANE_TO_GP, + 0xee100b10, 0xff100f1f, + "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"}, + + /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due + to instruction opcode aliasing. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSHLL_T1, + 0xeea00f40, 0xefa00fd1, + "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VMOVL long. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOVL, + 0xeea00f40, 0xefa70fd1, + "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VMOV and narrow. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOVN, + 0xfe310e81, 0xffb30fd1, + "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Floating point move extract. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMOVX, + 0xfeb00a40, 0xffbf0fd0, + "vmovx.f16\t%22,12-15F, %5,0-3F"}, + + /* Vector VMUL floating-point T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMUL_FP_T1, + 0xff000d50, 0xffa11f51, + "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMUL floating-point T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VMUL_FP_T2, + 0xee310e60, 0xefb11f70, + "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VMUL T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMUL_VEC_T1, + 0xef000950, 0xff811f51, + "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMUL T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMUL_VEC_T2, + 0xee011e60, 0xff811f70, + "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VMULH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMULH, + 0xee010e01, 0xef811f51, + "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VRMULH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRMULH, + 0xee011e01, 0xef811f51, + "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMULL integer. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMULL_INT, + 0xee010e00, 0xef810f51, + "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMULL polynomial. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMULL_POLY, + 0xee310e00, 0xefb10f51, + "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMVN immediate to vector. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMVN_IMM, + 0xef800070, 0xefb810f0, + "vmvn%v.i%8-11s\t%13-15,22Q, %E"}, + + /* Vector VMVN register. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMVN_REG, + 0xffb005c0, 0xffbf1fd1, + "vmvn%v\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VNEG floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VNEG_FP, + 0xffb107c0, 0xffb31fd1, + "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VNEG. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VNEG_VEC, + 0xffb103c0, 0xffb31fd1, + "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VORN, vector bitwise or not. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VORN, + 0xef300150, 0xffb11f51, + "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VORR register. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VORR_REG, + 0xef200150, 0xffb11f51, + "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if + "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen + MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes + array. */ + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VMOV_VEC_TO_VEC, + 0xef200150, 0xffb11f51, + "vmov%v\t%13-15,22Q, %17-19,7Q"}, + + /* Vector VQDMULL T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQDMULL_T1, + 0xee300f01, 0xefb10f51, + "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VPNOT. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPNOT, + 0xfe310f4d, 0xffffffff, + "vpnot%v"}, + + /* Vector VPSEL. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VPSEL, + 0xfe310f01, 0xffb11f51, + "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQABS. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQABS, + 0xffb00740, 0xffb31fd1, + "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQADD T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQADD_T1, + 0xef000050, 0xef811f51, + "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQADD T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQADD_T2, + 0xee000f60, 0xef811f70, + "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VQDMULL T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQDMULL_T2, + 0xee300f60, 0xefb10f70, + "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VQMOVN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQMOVN, + 0xee330e01, 0xefb30fd1, + "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VQMOVUN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQMOVUN, + 0xee310e81, 0xffb30fd1, + "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VQDMLADH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQDMLADH, + 0xee000e00, 0xff810f51, + "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQRDMLADH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRDMLADH, + 0xee000e01, 0xff810f51, + "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQDMLAH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQDMLAH, + 0xee000e60, 0xff811f70, + "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VQRDMLAH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRDMLAH, + 0xee000e40, 0xff811f70, + "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VQDMLASH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQDMLASH, + 0xee001e60, 0xff811f70, + "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VQRDMLASH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRDMLASH, + 0xee001e40, 0xff811f70, + "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VQDMLSDH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQDMLSDH, + 0xfe000e00, 0xff810f51, + "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQRDMLSDH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRDMLSDH, + 0xfe000e01, 0xff810f51, + "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQDMULH T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQDMULH_T1, + 0xef000b40, 0xff811f51, + "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQRDMULH T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRDMULH_T2, + 0xff000b40, 0xff811f51, + "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQDMULH T3 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQDMULH_T3, + 0xee010e60, 0xff811f70, + "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VQRDMULH T4 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRDMULH_T4, + 0xfe010e60, 0xff811f70, + "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VQNEG. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQNEG, + 0xffb007c0, 0xffb31fd1, + "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VQRSHL T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRSHL_T1, + 0xef000550, 0xef811f51, + "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, + + /* Vector VQRSHL T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRSHL_T2, + 0xee331ee0, 0xefb31ff0, + "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, + + /* Vector VQRSHRN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRSHRN, + 0xee800f41, 0xefa00fd1, + "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VQRSHRUN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQRSHRUN, + 0xfe800fc0, 0xffa00fd1, + "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VQSHL T1 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQSHL_T1, + 0xee311ee0, 0xefb31ff0, + "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, + + /* Vector VQSHL T4 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQSHL_T4, + 0xef000450, 0xef811f51, + "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, + + /* Vector VQSHRN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQSHRN, + 0xee800f40, 0xefa00fd1, + "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VQSHRUN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQSHRUN, + 0xee800fc0, 0xffa00fd1, + "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VQSUB T1 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQSUB_T1, + 0xef000250, 0xef811f51, + "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VQSUB T2 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VQSUB_T2, + 0xee001f60, 0xef811f70, + "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VREV16. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VREV16, + 0xffb00140, 0xffb31fd1, + "vrev16%v.8\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VREV32. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VREV32, + 0xffb000c0, 0xffb31fd1, + "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VREV64. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VREV64, + 0xffb00040, 0xffb31fd1, + "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VRINT floating point. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VRINT_FP, + 0xffb20440, 0xffb31c51, + "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, + + /* Vector VRMLALDAVH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRMLALDAVH, + 0xee800f00, 0xef811f51, + "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, + + /* Vector VRMLALDAVH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRMLALDAVH, + 0xee801f00, 0xef811f51, + "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, + + /* Vector VRSHL T1 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRSHL_T1, + 0xef000540, 0xef811f51, + "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, + + /* Vector VRSHL T2 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRSHL_T2, + 0xee331e60, 0xefb31ff0, + "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, + + /* Vector VRSHRN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VRSHRN, + 0xfe800fc1, 0xffa00fd1, + "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VSBC. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSBC, + 0xfe300f00, 0xffb10f51, + "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VSHL T2 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSHL_T2, + 0xee311e60, 0xefb31ff0, + "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, + + /* Vector VSHL T3 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSHL_T3, + 0xef000440, 0xef811f51, + "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, + + /* Vector VSHLC. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSHLC, + 0xeea00fc0, 0xffa01ff0, + "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"}, + + /* Vector VSHLL T2 Variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSHLL_T2, + 0xee310e01, 0xefb30fd1, + "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"}, + + /* Vector VSHRN. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSHRN, + 0xee800fc1, 0xffa00fd1, + "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"}, + + /* Vector VST2 no writeback. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VST2, + 0xfc801e00, 0xffb01e5f, + "vst2%5d.%7-8s\t%B, [%16-19r]"}, + + /* Vector VST2 writeback. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VST2, + 0xfca01e00, 0xffb01e5f, + "vst2%5d.%7-8s\t%B, [%16-19r]!"}, + + /* Vector VST4 no writeback. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VST4, + 0xfc801e01, 0xffb01e1f, + "vst4%5-6d.%7-8s\t%B, [%16-19r]"}, + + /* Vector VST4 writeback. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VST4, + 0xfca01e01, 0xffb01e1f, + "vst4%5-6d.%7-8s\t%B, [%16-19r]!"}, + + /* Vector VSTRB scatter store, T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRB_SCATTER_T1, + 0xec800e00, 0xffb01e50, + "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, + + /* Vector VSTRH scatter store, T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRH_SCATTER_T2, + 0xec800e10, 0xffb01e50, + "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, + + /* Vector VSTRW scatter store, T3 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRW_SCATTER_T3, + 0xec800e40, 0xffb01e50, + "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, + + /* Vector VSTRD scatter store, T4 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRD_SCATTER_T4, + 0xec800fd0, 0xffb01fd0, + "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, + + /* Vector VSTRW scatter store, T5 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRW_SCATTER_T5, + 0xfd001e00, 0xff111f00, + "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, + + /* Vector VSTRD scatter store, T6 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRD_SCATTER_T6, + 0xfd001f00, 0xff111f00, + "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"}, + + /* Vector VSTRB. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRB_T1, + 0xec000e00, 0xfe581e00, + "vstrb%v.%7-8s\t%13-15Q, %d"}, + + /* Vector VSTRH. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRH_T2, + 0xec080e00, 0xfe581e00, + "vstrh%v.%7-8s\t%13-15Q, %d"}, + + /* Vector VSTRB variant T5. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRB_T5, + 0xec001e00, 0xfe101f80, + "vstrb%v.8\t%13-15,22Q, %d"}, + + /* Vector VSTRH variant T6. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRH_T6, + 0xec001e80, 0xfe101f80, + "vstrh%v.16\t%13-15,22Q, %d"}, + + /* Vector VSTRW variant T7. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSTRW_T7, + 0xec001f00, 0xfe101f80, + "vstrw%v.32\t%13-15,22Q, %d"}, + + /* Vector VSUB floating point T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VSUB_FP_T1, + 0xef200d40, 0xffa11f51, + "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VSUB floating point T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), + MVE_VSUB_FP_T2, + 0xee301f40, 0xefb11f70, + "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + /* Vector VSUB T1 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSUB_VEC_T1, + 0xff000840, 0xff811f51, + "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, + + /* Vector VSUB T2 variant. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_VSUB_VEC_T2, + 0xee011f40, 0xff811f70, + "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_ASRLI, + 0xea50012f, 0xfff1813f, + "asrl%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_ASRL, + 0xea50012d, 0xfff101ff, + "asrl%c\t%17-19l, %9-11h, %12-15S"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_LSLLI, + 0xea50010f, 0xfff1813f, + "lsll%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_LSLL, + 0xea50010d, 0xfff101ff, + "lsll%c\t%17-19l, %9-11h, %12-15S"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_LSRL, + 0xea50011f, 0xfff1813f, + "lsrl%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_SQRSHRL, + 0xea51012d, 0xfff1017f, + "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_SQRSHR, + 0xea500f2d, 0xfff00fff, + "sqrshr%c\t%16-19S, %12-15S"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_SQSHLL, + 0xea51013f, 0xfff1813f, + "sqshll%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_SQSHL, + 0xea500f3f, 0xfff08f3f, + "sqshl%c\t%16-19S, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_SRSHRL, + 0xea51012f, 0xfff1813f, + "srshrl%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_SRSHR, + 0xea500f2f, 0xfff08f3f, + "srshr%c\t%16-19S, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_UQRSHLL, + 0xea51010d, 0xfff1017f, + "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_UQRSHL, + 0xea500f0d, 0xfff00fff, + "uqrshl%c\t%16-19S, %12-15S"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_UQSHLL, + 0xea51010f, 0xfff1813f, + "uqshll%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_UQSHL, + 0xea500f0f, 0xfff08f3f, + "uqshl%c\t%16-19S, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_URSHRL, + 0xea51011f, 0xfff1813f, + "urshrl%c\t%17-19l, %9-11h, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), + MVE_URSHR, + 0xea500f1f, 0xfff08f3f, + "urshr%c\t%16-19S, %j"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CSINC, + 0xea509000, 0xfff0f000, + "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CSINV, + 0xea50a000, 0xfff0f000, + "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CSET, + 0xea5f900f, 0xfffff00f, + "cset\t%8-11S, %4-7C"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CSETM, + 0xea5fa00f, 0xfffff00f, + "csetm\t%8-11S, %4-7C"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CSEL, + 0xea508000, 0xfff0f000, + "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CSNEG, + 0xea50b000, 0xfff0f000, + "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CINC, + 0xea509000, 0xfff0f000, + "cinc\t%8-11S, %16-19Z, %4-7C"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CINV, + 0xea50a000, 0xfff0f000, + "cinv\t%8-11S, %16-19Z, %4-7C"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + MVE_CNEG, + 0xea50b000, 0xfff0f000, + "cneg\t%8-11S, %16-19Z, %4-7C"}, + + {ARM_FEATURE_CORE_LOW (0), + MVE_NONE, + 0x00000000, 0x00000000, 0} }; /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially @@ -801,348 +3640,770 @@ static const struct opcode32 neon_opcodes[] = %P print address for pli instruction. %r print as an ARM register + %T print as an ARM register + 1 %R as %r but r15 is UNPREDICTABLE %{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE %{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE %d print the bitfield in decimal - %W print the bitfield plus one in decimal + %W print the bitfield plus one in decimal %x print the bitfield in hex %X print the bitfield as 1 hex digit without leading "0x" - + %'c print specified char iff bitfield is all ones %`c print specified char iff bitfield is all zeroes %?ab... select from array of values in big endian order %e print arm SMI operand (bits 0..7,8..19). %E print the LSB and WIDTH fields of a BFI or BFC instruction. - %V print the 16-bit immediate field of a MOVT or MOVW instruction. */ + %V print the 16-bit immediate field of a MOVT or MOVW instruction. + %R print the SPSR/CPSR or banked register of an MRS. */ static const struct opcode32 arm_opcodes[] = { /* ARM instructions. */ - {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, - {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, - {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), + 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), + 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), + 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), + 0x00800090, 0x0fa000f0, + "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), + 0x00a00090, 0x0fa000f0, + "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + + /* V8.2 RAS extension instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), + 0xe320f010, 0xffffffff, "esb"}, + + /* V8 instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x0320f005, 0x0fffffff, "sevl"}, + /* Defined in V8 but is in NOP space so available to all arch. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), + 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), + 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, + /* CRC32 instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, + + /* Privileged Access Never extension instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), + 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"}, + + /* Virtualization Extension instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, + + /* Integer Divide Extension instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), + 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), + 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, + + /* MP Extension instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, + + /* Speculation Barriers. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"}, /* V7 instructions. */ - {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, - {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, - {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"}, - {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"}, - {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), + 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, /* ARM V6T2 instructions. */ - {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, - {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, - {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"}, - - {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, - {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, - - {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, - {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, - {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, - - /* ARM V6Z instructions. */ - {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, + + /* ARM Security extension instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), + 0x01600070, 0x0ff000f0, "smc%c\t%e"}, /* ARM V6K instructions. */ - {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, - {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, - {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, - {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, - {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, - {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, - {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0xf57ff01f, 0xffffffff, "clrex"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, + + /* ARMv8.5-A instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"}, /* ARM V6K NOP hints. */ - {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, - {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"}, - {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"}, - {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, - {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f001, 0x0fffffff, "yield%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f002, 0x0fffffff, "wfe%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f003, 0x0fffffff, "wfi%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f004, 0x0fffffff, "sev%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), + 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, /* ARM V6 instructions. */ - {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, - {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, - {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, - {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, - {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, - {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, - {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, - {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, - {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, - {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, - {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, - {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, - {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, - {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, - {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, - {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, - {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, - {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, - {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, - {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, - {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, - {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, - {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, - {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), + 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, /* V5J instruction. */ - {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), + 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, /* V5 Instructions. */ - {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, - {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, - {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, - {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, - - /* V5E "El Segundo" Instructions. */ - {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, - {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, - {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, - {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, - - {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, - {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, - - {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, - - {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, - - {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, - {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, - - {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, - {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, - {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, - {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xe1200070, 0xfff000f0, + "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0xfa000000, 0xfe000000, "blx\t%B"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, + + /* V5E "El Segundo" Instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), + 0xf450f000, 0xfc70f000, "pld\t%a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), + 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, /* ARM Instructions. */ - {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, - - {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, - - {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, - {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, - - {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, - {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, - - {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, - {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15R, %22?SCPSR"}, - - {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, - - {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"}, - - {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, - {ARM_EXT_V3, 0x01400000, 0x0ff00010, "mrs%c\t%12-15R, %22?SCPSR"}, - {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, - - {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, - {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, - - {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, - {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, - {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, - {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, - {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, - {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, - {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, - - {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, - {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, - - {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, - {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, - {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, - - {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, - - {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, - - {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, - {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, - - {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, - {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, - {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, - {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), + 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), + 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), + 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x092d0000, 0x0fff0000, "push%c\t%m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, + + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, /* The rest. */ - {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, - {0, 0x00000000, 0x00000000, 0} + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), + 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (0), + 0x00000000, 0x00000000, 0} }; /* print_insn_thumb16 recognizes the following format control codes: @@ -1176,120 +4437,159 @@ static const struct opcode16 thumb_opcodes[] = { /* Thumb instructions. */ + /* ARMv8-M Security Extensions instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"}, + + /* ARM V8 instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"}, + /* ARM V6K no-argument instructions. */ - {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, - {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, - {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"}, - {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"}, - {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"}, - {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, /* ARM V6T2 instructions. */ - {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, - {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, - {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, /* ARM V6. */ - {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, - {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, - {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"}, - {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, - {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, /* ARM V5 ISA extends Thumb. */ - {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), + 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ /* This is BLX(2). BLX(1) is a 32-bit instruction. */ - {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), + 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ /* ARM V4T ISA (Thumb v1). */ - {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, /* Format 4. */ - {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, - {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, /* format 13 */ - {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, - {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, /* format 5 */ - {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"}, - {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"}, - {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"}, - {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, /* format 14 */ - {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"}, - {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, /* format 2 */ - {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, - {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, - {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, - {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, /* format 8 */ - {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, /* format 7 */ - {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, - {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, /* format 1 */ - {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, - {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, - {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, /* format 3 */ - {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, - {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, /* format 6 */ - {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=" */ + /* TODO: Disassemble PC relative "LDR rD,=" */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x4800, 0xF800, + "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* format 9 */ - {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, - {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, - {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, - {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, /* format 10 */ - {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, - {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, /* format 11 */ - {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, - {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, /* format 12 */ - {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, - {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, /* format 15 */ - {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, - {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, /* format 17 */ - {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, /* format 16 */ - {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, /* format 18 */ - {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, /* The E800 .. FFFF range is unconditionally redirected to the 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs are processed via that table. Thus, we can never encounter a bare "second half of BL/BLX(1)" instruction here. */ - {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, - {0, 0, 0, 0} + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} }; /* Thumb32 opcodes use the same table structure as the ARM opcodes. @@ -1304,14 +4604,23 @@ static const struct opcode16 thumb_opcodes[] = %M print a modified 12-bit immediate (same location) %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] + %H print a 16-bit immediate from hw2[3:0],hw1[11:0] %S print a possibly-shifted Rm + %L print address for a ldrd/strd instruction %a print the address of a plain load/store %w print the width and signedness of a core load/store %m print register mask for ldm/stm + %n print register mask for clrm %E print the lsb and width fields of a bfc/bfi instruction %F print the lsb and width fields of a sbfx/ubfx instruction + %G print a fallback offset for Branch Future instructions + %W print an offset for BF instruction + %Y print an offset for BFL instruction + %Z print an offset for BFCSEL instruction + %Q print an offset for Low Overhead Loop instructions + %P print an offset for Low Overhead Loop end instructions %b print a conditional branch offset %B print an unconditional branch offset %s print the shift field of an SSAT instruction @@ -1323,9 +4632,11 @@ static const struct opcode16 thumb_opcodes[] = %X print "\t; unpredictable " if conditional %d print bitfield in decimal + %D print bitfield plus one in decimal %W print bitfield*4 in decimal %r print bitfield as an ARM register - %R as %<>r bit r15 is UNPREDICTABLE + %R as %<>r but r15 is UNPREDICTABLE + %S as %<>r but r13 and r15 is UNPREDICTABLE %c print bitfield as a condition code %'c print specified char iff bitfield is all ones @@ -1342,209 +4653,512 @@ static const struct opcode16 thumb_opcodes[] = makes heavy use of special-case bit patterns. */ static const struct opcode32 thumb32_opcodes[] = { + /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions + instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf00fe001, 0xffffffff, "lctp%c"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf02fc001, 0xfffff001, "le\t%P"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf00fc001, 0xfffff001, "le\tlr, %P"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf01fc001, 0xfffff001, "letp\tlr, %P"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xe89f0000, 0xffff2000, "clrm%c\t%n"}, + + /* ARMv8-M and ARMv8-M Security Extensions instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), + 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), + 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), + 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), + 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, + + /* ARM V8.2 RAS extension instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), + 0xf3af8010, 0xffffffff, "esb"}, + + /* V8 instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xf3af8005, 0xffffffff, "sevl%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), + 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, + + /* CRC32 instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC), + 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, + + /* Speculation Barriers. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"}, + /* V7 instructions. */ - {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, - {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, - {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, - {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, - {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, - {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), + 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), + 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, + + /* Virtualization Extension instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, + /* We skip ERET as that is SUBS pc, lr, #0. */ + + /* MP Extension instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, + + /* Security extension instructions. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, + + /* ARMv8.5-A instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"}, /* Instructions defined in the basic V6T2 set. */ - {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, - {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, - {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"}, - {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, - {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"}, - {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, - - {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, - {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, - {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, - {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, - {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, - {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, - {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"}, - {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, - {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, - {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, - {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, - {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, - {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, - {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, - {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, - {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, - {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, - {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, - {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, - {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, - {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, - {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, - {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, - {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, - {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, - {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, - {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, - {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, - {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, - {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, - {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, - {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, - {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, - {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, - {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, - {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, - {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, - {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, - {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, - {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, - {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, - {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, - {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, - {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, - {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, - {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, - {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, - {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, - {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, - {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, - {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, - {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, + + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xf3bf8f2f, 0xffffffff, "clrex%c"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf810f000, 0xff70f000, "pld%c\t%a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfb100000, 0xfff000c0, + "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xfbc00080, 0xfff000c0, + "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9400000, 0xff500000, + "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe9500000, 0xff500000, + "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8600000, 0xff700000, + "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xe8700000, 0xff700000, + "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, /* Filter out Bcc with cond=E or F, which are used for other instructions. */ - {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, - {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, - {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, - {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, /* These have been 32-bit since the invention of Thumb. */ - {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"}, - {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), + 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, /* Fallback. */ - {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, - {0, 0, 0, 0} + {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), + 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, + {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} }; static const char *const arm_conditional[] = @@ -1567,18 +5181,21 @@ arm_regname; static const arm_regname regnames[] = { - { "raw" , "Select raw register names", + { "reg-names-raw", N_("Select raw register names"), { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, - { "gcc", "Select register names used by GCC", + { "reg-names-gcc", N_("Select register names used by GCC"), { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, - { "std", "Select register names used in ARM's ISA documentation", + { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, - { "apcs", "Select register names used in the APCS", + { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, + { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, + { "reg-names-apcs", N_("Select register names used in the APCS"), { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, - { "atpcs", "Select register names used in the ATPCS", + { "reg-names-atpcs", N_("Select register names used in the ATPCS"), { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, - { "special-atpcs", "Select special register names used in the ATPCS", + { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, + { "coproc=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL } } }; static const char *const iwmmxt_wwnames[] = @@ -1601,13 +5218,64 @@ static const char *const iwmmxt_cregnames[] = "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" }; +static const char *const vec_condnames[] = +{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le" +}; + +static const char *const mve_predicatenames[] = +{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "", + "eee", "ee", "eet", "e", "ett", "et", "ete" +}; + +/* Names for 2-bit size field for mve vector isntructions. */ +static const char *const mve_vec_sizename[] = + { "8", "16", "32", "64"}; + +/* Indicates whether we are processing a then predicate, + else predicate or none at all. */ +enum vpt_pred_state +{ + PRED_NONE, + PRED_THEN, + PRED_ELSE +}; + +/* Information used to process a vpt block and subsequent instructions. */ +struct vpt_block +{ + /* Are we in a vpt block. */ + bfd_boolean in_vpt_block; + + /* Next predicate state if in vpt block. */ + enum vpt_pred_state next_pred_state; + + /* Mask from vpt/vpst instruction. */ + long predicate_mask; + + /* Instruction number in vpt block. */ + long current_insn_num; + + /* Number of instructions in vpt block.. */ + long num_pred_insn; +}; + +static struct vpt_block vpt_block_state = +{ + FALSE, + PRED_NONE, + 0, + 0, + 0 +}; + /* Default to GCC register name set. */ static unsigned int regname_selected = 1; -#define NUM_ARM_REGNAMES NUM_ELEM (regnames) +#define NUM_ARM_OPTIONS ARRAY_SIZE (regnames) #define arm_regnames regnames[regname_selected].reg_names static bfd_boolean force_thumb = FALSE; +static uint16_t cde_coprocs = 0; /* Current IT instruction state. This contains the same state as the IT bits in the CPSR. */ @@ -1617,45 +5285,118 @@ static unsigned int ifthen_next_state; /* The address of the insn for which the IT state is valid. */ static bfd_vma ifthen_address; #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) +/* Indicates that the current Conditional state is unconditional or outside + an IT block. */ +#define COND_UNCOND 16 -/* Cached mapping symbol state. */ -enum map_type + +/* Functions. */ +/* Extract the predicate mask for a VPT or VPST instruction. + The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */ + +static long +mve_extract_pred_mask (long given) { - MAP_ARM, - MAP_THUMB, - MAP_DATA -}; + return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13); +} + +/* Return the number of instructions in a MVE predicate block. */ +static long +num_instructions_vpt_block (long given) +{ + long mask = mve_extract_pred_mask (given); + if (mask == 0) + return 0; -enum map_type last_type; -int last_mapping_sym = -1; -bfd_vma last_mapping_addr = 0; + if (mask == 8) + return 1; - -/* Functions. */ -int -get_arm_regname_num_options (void) + if ((mask & 7) == 4) + return 2; + + if ((mask & 3) == 2) + return 3; + + if ((mask & 1) == 1) + return 4; + + return 0; +} + +static void +mark_outside_vpt_block (void) { - return NUM_ARM_REGNAMES; + vpt_block_state.in_vpt_block = FALSE; + vpt_block_state.next_pred_state = PRED_NONE; + vpt_block_state.predicate_mask = 0; + vpt_block_state.current_insn_num = 0; + vpt_block_state.num_pred_insn = 0; } -int -set_arm_regname_option (int option) +static void +mark_inside_vpt_block (long given) { - int old = regname_selected; - regname_selected = option; - return old; + vpt_block_state.in_vpt_block = TRUE; + vpt_block_state.next_pred_state = PRED_THEN; + vpt_block_state.predicate_mask = mve_extract_pred_mask (given); + vpt_block_state.current_insn_num = 0; + vpt_block_state.num_pred_insn = num_instructions_vpt_block (given); + assert (vpt_block_state.num_pred_insn >= 1); } -int -get_arm_regnames (int option, - const char **setname, - const char **setdescription, - const char *const **register_names) +static enum vpt_pred_state +invert_next_predicate_state (enum vpt_pred_state astate) +{ + if (astate == PRED_THEN) + return PRED_ELSE; + else if (astate == PRED_ELSE) + return PRED_THEN; + else + return PRED_NONE; +} + +static enum vpt_pred_state +update_next_predicate_state (void) +{ + long pred_mask = vpt_block_state.predicate_mask; + long mask_for_insn = 0; + + switch (vpt_block_state.current_insn_num) + { + case 1: + mask_for_insn = 8; + break; + + case 2: + mask_for_insn = 4; + break; + + case 3: + mask_for_insn = 2; + break; + + case 4: + return PRED_NONE; + } + + if (pred_mask & mask_for_insn) + return invert_next_predicate_state (vpt_block_state.next_pred_state); + else + return vpt_block_state.next_pred_state; +} + +static void +update_vpt_block_state (void) { - *setname = regnames[option].name; - *setdescription = regnames[option].description; - *register_names = regnames[option].reg_names; - return 16; + vpt_block_state.current_insn_num++; + if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn) + { + /* No more instructions to process in vpt block. */ + mark_outside_vpt_block (); + return; + } + + vpt_block_state.next_pred_state = update_next_predicate_state (); } /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. @@ -1671,8 +5412,8 @@ arm_decode_bitfield (const char *ptr, { unsigned long value = 0; int width = 0; - - do + + do { int start, end; int bits; @@ -1736,123 +5477,2710 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream, } } -#define W_BIT 21 -#define I_BIT 22 -#define U_BIT 23 -#define P_BIT 24 +/* Return TRUE if the MATCHED_INSN can be inside an IT block. */ + +static bfd_boolean +is_mve_okay_in_it (enum mve_instructions matched_insn) +{ + switch (matched_insn) + { + case MVE_VMOV_GP_TO_VEC_LANE: + case MVE_VMOV2_VEC_LANE_TO_GP: + case MVE_VMOV2_GP_TO_VEC_LANE: + case MVE_VMOV_VEC_LANE_TO_GP: + case MVE_LSLL: + case MVE_LSLLI: + case MVE_LSRL: + case MVE_ASRL: + case MVE_ASRLI: + case MVE_SQRSHRL: + case MVE_SQRSHR: + case MVE_UQRSHL: + case MVE_UQRSHLL: + case MVE_UQSHL: + case MVE_UQSHLL: + case MVE_URSHRL: + case MVE_URSHR: + case MVE_SRSHRL: + case MVE_SRSHR: + case MVE_SQSHLL: + case MVE_SQSHL: + return TRUE; + default: + return FALSE; + } +} + +static bfd_boolean +is_mve_architecture (struct disassemble_info *info) +{ + struct arm_private_data *private_data = info->private_data; + arm_feature_set allowed_arches = private_data->features; -#define WRITEBACK_BIT_SET (given & (1 << W_BIT)) -#define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) -#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) -#define PRE_BIT_SET (given & (1 << P_BIT)) + arm_feature_set arm_ext_v8_1m_main + = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); -/* Print one coprocessor instruction on INFO->STREAM. - Return TRUE if the instuction matched, FALSE if this is not a - recognised coprocessor instruction. */ + if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) + && !ARM_CPU_IS_ANY (allowed_arches)) + return TRUE; + else + return FALSE; +} static bfd_boolean -print_insn_coprocessor (bfd_vma pc, - struct disassemble_info *info, - long given, - bfd_boolean thumb) +is_vpt_instruction (long given) { - const struct opcode32 *insn; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - unsigned long mask; + + /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */ + if ((given & 0x0040e000) == 0) + return FALSE; + + /* VPT floating point T1 variant. */ + if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1)) + /* VPT floating point T2 variant. */ + || ((given & 0xefb10f50) == 0xee310f40) + /* VPT vector T1 variant. */ + || ((given & 0xff811f51) == 0xfe010f00) + /* VPT vector T2 variant. */ + || ((given & 0xff811f51) == 0xfe010f01 + && ((given & 0x300000) != 0x300000)) + /* VPT vector T3 variant. */ + || ((given & 0xff811f50) == 0xfe011f00) + /* VPT vector T4 variant. */ + || ((given & 0xff811f70) == 0xfe010f40) + /* VPT vector T5 variant. */ + || ((given & 0xff811f70) == 0xfe010f60) + /* VPT vector T6 variant. */ + || ((given & 0xff811f50) == 0xfe011f40) + /* VPST vector T variant. */ + || ((given & 0xffbf1fff) == 0xfe310f4d)) + return TRUE; + else + return FALSE; +} + +/* Decode a bitfield from opcode GIVEN, with starting bitfield = START + and ending bitfield = END. END must be greater than START. */ + +static unsigned long +arm_decode_field (unsigned long given, unsigned int start, unsigned int end) +{ + int bits = end - start; + + if (bits < 0) + abort (); + + return ((given >> start) & ((2ul << bits) - 1)); +} + +/* Decode a bitfield from opcode GIVEN, with multiple bitfields: + START:END and START2:END2. END/END2 must be greater than + START/START2. */ + +static unsigned long +arm_decode_field_multiple (unsigned long given, unsigned int start, + unsigned int end, unsigned int start2, + unsigned int end2) +{ + int bits = end - start; + int bits2 = end2 - start2; unsigned long value = 0; - struct arm_private_data *private_data = info->private_data; - unsigned long allowed_arches = private_data->features.coproc; - int cond; + int width = 0; + + if (bits2 < 0) + abort (); + + value = arm_decode_field (given, start, end); + width += bits + 1; + + value |= ((given >> start2) & ((2ul << bits2) - 1)) << width; + return value; +} + +/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN. + This helps us decode instructions that change mnemonic depending on specific + operand values/encodings. */ - for (insn = coprocessor_opcodes; insn->assembler; insn++) +static bfd_boolean +is_mve_encoding_conflict (unsigned long given, + enum mve_instructions matched_insn) +{ + switch (matched_insn) { - unsigned long u_reg = 16; - bfd_boolean is_unpredictable = FALSE; - signed long value_in_comment = 0; - const char *c; + case MVE_VPST: + if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) + return TRUE; + else + return FALSE; - if (insn->arch == 0) - switch (insn->value) - { - case SENTINEL_IWMMXT_START: - if (info->mach != bfd_mach_arm_XScale - && info->mach != bfd_mach_arm_iWMMXt - && info->mach != bfd_mach_arm_iWMMXt2) - do - insn++; - while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END); - continue; + case MVE_VPT_FP_T1: + if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) + return TRUE; + if ((arm_decode_field (given, 12, 12) == 0) + && (arm_decode_field (given, 0, 0) == 1)) + return TRUE; + return FALSE; + + case MVE_VPT_FP_T2: + if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) + return TRUE; + if (arm_decode_field (given, 0, 3) == 0xd) + return TRUE; + return FALSE; + + case MVE_VPT_VEC_T1: + case MVE_VPT_VEC_T2: + case MVE_VPT_VEC_T3: + case MVE_VPT_VEC_T4: + case MVE_VPT_VEC_T5: + case MVE_VPT_VEC_T6: + if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0) + return TRUE; + if (arm_decode_field (given, 20, 21) == 3) + return TRUE; + return FALSE; + + case MVE_VCMP_FP_T1: + if ((arm_decode_field (given, 12, 12) == 0) + && (arm_decode_field (given, 0, 0) == 1)) + return TRUE; + else + return FALSE; - case SENTINEL_IWMMXT_END: - continue; + case MVE_VCMP_FP_T2: + if (arm_decode_field (given, 0, 3) == 0xd) + return TRUE; + else + return FALSE; - case SENTINEL_GENERIC_START: - allowed_arches = private_data->features.core; - continue; + case MVE_VQADD_T2: + case MVE_VQSUB_T2: + case MVE_VMUL_VEC_T2: + case MVE_VMULH: + case MVE_VRMULH: + case MVE_VMLA: + case MVE_VMAX: + case MVE_VMIN: + case MVE_VBRSR: + case MVE_VADD_VEC_T2: + case MVE_VSUB_VEC_T2: + case MVE_VABAV: + case MVE_VQRSHL_T1: + case MVE_VQSHL_T4: + case MVE_VRSHL_T1: + case MVE_VSHL_T3: + case MVE_VCADD_VEC: + case MVE_VHCADD: + case MVE_VDDUP: + case MVE_VIDUP: + case MVE_VQRDMLADH: + case MVE_VQDMLAH: + case MVE_VQRDMLAH: + case MVE_VQDMLASH: + case MVE_VQRDMLASH: + case MVE_VQDMLSDH: + case MVE_VQRDMLSDH: + case MVE_VQDMULH_T3: + case MVE_VQRDMULH_T4: + case MVE_VQDMLADH: + case MVE_VMLAS: + case MVE_VMULL_INT: + case MVE_VHADD_T2: + case MVE_VHSUB_T2: + case MVE_VCMP_VEC_T1: + case MVE_VCMP_VEC_T2: + case MVE_VCMP_VEC_T3: + case MVE_VCMP_VEC_T4: + case MVE_VCMP_VEC_T5: + case MVE_VCMP_VEC_T6: + if (arm_decode_field (given, 20, 21) == 3) + return TRUE; + else + return FALSE; - default: - abort (); - } + case MVE_VLD2: + case MVE_VLD4: + case MVE_VST2: + case MVE_VST4: + if (arm_decode_field (given, 7, 8) == 3) + return TRUE; + else + return FALSE; - mask = insn->mask; - value = insn->value; - if (thumb) + case MVE_VSTRB_T1: + case MVE_VSTRH_T2: + if ((arm_decode_field (given, 24, 24) == 0) + && (arm_decode_field (given, 21, 21) == 0)) { - /* The high 4 bits are 0xe for Arm conditional instructions, and - 0xe for arm unconditional instructions. The rest of the - encoding is the same. */ - mask |= 0xf0000000; - value |= 0xe0000000; - if (ifthen_state) - cond = IFTHEN_COND; - else - cond = 16; + return TRUE; } + else if ((arm_decode_field (given, 7, 8) == 3)) + return TRUE; else + return FALSE; + + case MVE_VSTRB_T5: + case MVE_VSTRH_T6: + case MVE_VSTRW_T7: + if ((arm_decode_field (given, 24, 24) == 0) + && (arm_decode_field (given, 21, 21) == 0)) { - /* Only match unconditional instuctions against unconditional - patterns. */ - if ((given & 0xf0000000) == 0xf0000000) - { - mask |= 0xf0000000; - cond = 16; - } - else - { - cond = (given >> 28) & 0xf; - if (cond == 0xe) - cond = 16; - } + return TRUE; } - - if ((given & mask) != value) - continue; + else + return FALSE; - if ((insn->arch & allowed_arches) == 0) - continue; + case MVE_VCVT_FP_FIX_VEC: + return (arm_decode_field (given, 16, 21) & 0x38) == 0; - for (c = insn->assembler; *c; c++) - { - if (*c == '%') + case MVE_VBIC_IMM: + case MVE_VORR_IMM: + { + unsigned long cmode = arm_decode_field (given, 8, 11); + + if ((cmode & 1) == 0) + return TRUE; + else if ((cmode & 0xc) == 0xc) + return TRUE; + else + return FALSE; + } + + case MVE_VMVN_IMM: + { + unsigned long cmode = arm_decode_field (given, 8, 11); + + if (cmode == 0xe) + return TRUE; + else if ((cmode & 0x9) == 1) + return TRUE; + else if ((cmode & 0xd) == 9) + return TRUE; + else + return FALSE; + } + + case MVE_VMOV_IMM_TO_VEC: + if ((arm_decode_field (given, 5, 5) == 1) + && (arm_decode_field (given, 8, 11) != 0xe)) + return TRUE; + else + return FALSE; + + case MVE_VMOVL: + { + unsigned long size = arm_decode_field (given, 19, 20); + if ((size == 0) || (size == 3)) + return TRUE; + else + return FALSE; + } + + case MVE_VMAXA: + case MVE_VMINA: + case MVE_VMAXV: + case MVE_VMAXAV: + case MVE_VMINV: + case MVE_VMINAV: + case MVE_VQRSHL_T2: + case MVE_VQSHL_T1: + case MVE_VRSHL_T2: + case MVE_VSHL_T2: + case MVE_VSHLL_T2: + case MVE_VADDV: + case MVE_VMOVN: + case MVE_VQMOVUN: + case MVE_VQMOVN: + if (arm_decode_field (given, 18, 19) == 3) + return TRUE; + else + return FALSE; + + case MVE_VMLSLDAV: + case MVE_VRMLSLDAVH: + case MVE_VMLALDAV: + case MVE_VADDLV: + if (arm_decode_field (given, 20, 22) == 7) + return TRUE; + else + return FALSE; + + case MVE_VRMLALDAVH: + if ((arm_decode_field (given, 20, 22) & 6) == 6) + return TRUE; + else + return FALSE; + + case MVE_VDWDUP: + case MVE_VIWDUP: + if ((arm_decode_field (given, 20, 21) == 3) + || (arm_decode_field (given, 1, 3) == 7)) + return TRUE; + else + return FALSE; + + + case MVE_VSHLL_T1: + if (arm_decode_field (given, 16, 18) == 0) + { + unsigned long sz = arm_decode_field (given, 19, 20); + + if ((sz == 1) || (sz == 2)) + return TRUE; + else + return FALSE; + } + else + return FALSE; + + case MVE_VQSHL_T2: + case MVE_VQSHLU_T3: + case MVE_VRSHR: + case MVE_VSHL_T1: + case MVE_VSHR: + case MVE_VSLI: + case MVE_VSRI: + if (arm_decode_field (given, 19, 21) == 0) + return TRUE; + else + return FALSE; + + case MVE_VCTP: + if (arm_decode_field (given, 16, 19) == 0xf) + return TRUE; + else + return FALSE; + + case MVE_ASRLI: + case MVE_ASRL: + case MVE_LSLLI: + case MVE_LSLL: + case MVE_LSRL: + case MVE_SQRSHRL: + case MVE_SQSHLL: + case MVE_SRSHRL: + case MVE_UQRSHLL: + case MVE_UQSHLL: + case MVE_URSHRL: + if (arm_decode_field (given, 9, 11) == 0x7) + return TRUE; + else + return FALSE; + + case MVE_CSINC: + case MVE_CSINV: + { + unsigned long rm, rn; + rm = arm_decode_field (given, 0, 3); + rn = arm_decode_field (given, 16, 19); + /* CSET/CSETM. */ + if (rm == 0xf && rn == 0xf) + return TRUE; + /* CINC/CINV. */ + else if (rn == rm && rn != 0xf) + return TRUE; + } + /* Fall through. */ + case MVE_CSEL: + case MVE_CSNEG: + if (arm_decode_field (given, 0, 3) == 0xd) + return TRUE; + /* CNEG. */ + else if (matched_insn == MVE_CSNEG) + if (arm_decode_field (given, 0, 3) == arm_decode_field (given, 16, 19)) + return TRUE; + return FALSE; + + default: + case MVE_VADD_FP_T1: + case MVE_VADD_FP_T2: + case MVE_VADD_VEC_T1: + return FALSE; + + } +} + +static void +print_mve_vld_str_addr (struct disassemble_info *info, + unsigned long given, + enum mve_instructions matched_insn) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + unsigned long p, w, gpr, imm, add, mod_imm; + + imm = arm_decode_field (given, 0, 6); + mod_imm = imm; + + switch (matched_insn) + { + case MVE_VLDRB_T1: + case MVE_VSTRB_T1: + gpr = arm_decode_field (given, 16, 18); + break; + + case MVE_VLDRH_T2: + case MVE_VSTRH_T2: + gpr = arm_decode_field (given, 16, 18); + mod_imm = imm << 1; + break; + + case MVE_VLDRH_T6: + case MVE_VSTRH_T6: + gpr = arm_decode_field (given, 16, 19); + mod_imm = imm << 1; + break; + + case MVE_VLDRW_T7: + case MVE_VSTRW_T7: + gpr = arm_decode_field (given, 16, 19); + mod_imm = imm << 2; + break; + + case MVE_VLDRB_T5: + case MVE_VSTRB_T5: + gpr = arm_decode_field (given, 16, 19); + break; + + default: + return; + } + + p = arm_decode_field (given, 24, 24); + w = arm_decode_field (given, 21, 21); + + add = arm_decode_field (given, 23, 23); + + char * add_sub; + + /* Don't print anything for '+' as it is implied. */ + if (add == 1) + add_sub = ""; + else + add_sub = "-"; + + if (p == 1) + { + /* Offset mode. */ + if (w == 0) + func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm); + /* Pre-indexed mode. */ + else + func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm); + } + else if ((p == 0) && (w == 1)) + /* Post-index mode. */ + func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm); +} + +/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN. + Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why + this encoding is undefined. */ + +static bfd_boolean +is_mve_undefined (unsigned long given, enum mve_instructions matched_insn, + enum mve_undefined *undefined_code) +{ + *undefined_code = UNDEF_NONE; + + switch (matched_insn) + { + case MVE_VDUP: + if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else + return FALSE; + + case MVE_VQADD_T1: + case MVE_VQSUB_T1: + case MVE_VMUL_VEC_T1: + case MVE_VABD_VEC: + case MVE_VADD_VEC_T1: + case MVE_VSUB_VEC_T1: + case MVE_VQDMULH_T1: + case MVE_VQRDMULH_T2: + case MVE_VRHADD: + case MVE_VHADD_T1: + case MVE_VHSUB_T1: + if (arm_decode_field (given, 20, 21) == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else + return FALSE; + + case MVE_VLDRB_T1: + if (arm_decode_field (given, 7, 8) == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else + return FALSE; + + case MVE_VLDRH_T2: + if (arm_decode_field (given, 7, 8) <= 1) + { + *undefined_code = UNDEF_SIZE_LE_1; + return TRUE; + } + else + return FALSE; + + case MVE_VSTRB_T1: + if ((arm_decode_field (given, 7, 8) == 0)) + { + *undefined_code = UNDEF_SIZE_0; + return TRUE; + } + else + return FALSE; + + case MVE_VSTRH_T2: + if ((arm_decode_field (given, 7, 8) <= 1)) + { + *undefined_code = UNDEF_SIZE_LE_1; + return TRUE; + } + else + return FALSE; + + case MVE_VLDRB_GATHER_T1: + if (arm_decode_field (given, 7, 8) == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else if ((arm_decode_field (given, 28, 28) == 0) + && (arm_decode_field (given, 7, 8) == 0)) + { + *undefined_code = UNDEF_NOT_UNS_SIZE_0; + return TRUE; + } + else + return FALSE; + + case MVE_VLDRH_GATHER_T2: + if (arm_decode_field (given, 7, 8) == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else if ((arm_decode_field (given, 28, 28) == 0) + && (arm_decode_field (given, 7, 8) == 1)) + { + *undefined_code = UNDEF_NOT_UNS_SIZE_1; + return TRUE; + } + else if (arm_decode_field (given, 7, 8) == 0) + { + *undefined_code = UNDEF_SIZE_0; + return TRUE; + } + else + return FALSE; + + case MVE_VLDRW_GATHER_T3: + if (arm_decode_field (given, 7, 8) != 2) + { + *undefined_code = UNDEF_SIZE_NOT_2; + return TRUE; + } + else if (arm_decode_field (given, 28, 28) == 0) + { + *undefined_code = UNDEF_NOT_UNSIGNED; + return TRUE; + } + else + return FALSE; + + case MVE_VLDRD_GATHER_T4: + if (arm_decode_field (given, 7, 8) != 3) + { + *undefined_code = UNDEF_SIZE_NOT_3; + return TRUE; + } + else if (arm_decode_field (given, 28, 28) == 0) + { + *undefined_code = UNDEF_NOT_UNSIGNED; + return TRUE; + } + else + return FALSE; + + case MVE_VSTRB_SCATTER_T1: + if (arm_decode_field (given, 7, 8) == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else + return FALSE; + + case MVE_VSTRH_SCATTER_T2: + { + unsigned long size = arm_decode_field (given, 7, 8); + if (size == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else if (size == 0) + { + *undefined_code = UNDEF_SIZE_0; + return TRUE; + } + else + return FALSE; + } + + case MVE_VSTRW_SCATTER_T3: + if (arm_decode_field (given, 7, 8) != 2) + { + *undefined_code = UNDEF_SIZE_NOT_2; + return TRUE; + } + else + return FALSE; + + case MVE_VSTRD_SCATTER_T4: + if (arm_decode_field (given, 7, 8) != 3) + { + *undefined_code = UNDEF_SIZE_NOT_3; + return TRUE; + } + else + return FALSE; + + case MVE_VCVT_FP_FIX_VEC: + { + unsigned long imm6 = arm_decode_field (given, 16, 21); + if ((imm6 & 0x20) == 0) + { + *undefined_code = UNDEF_VCVT_IMM6; + return TRUE; + } + + if ((arm_decode_field (given, 9, 9) == 0) + && ((imm6 & 0x30) == 0x20)) + { + *undefined_code = UNDEF_VCVT_FSI_IMM6; + return TRUE; + } + + return FALSE; + } + + case MVE_VNEG_FP: + case MVE_VABS_FP: + case MVE_VCVT_BETWEEN_FP_INT: + case MVE_VCVT_FROM_FP_TO_INT: + { + unsigned long size = arm_decode_field (given, 18, 19); + if (size == 0) + { + *undefined_code = UNDEF_SIZE_0; + return TRUE; + } + else if (size == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else + return FALSE; + } + + case MVE_VMOV_VEC_LANE_TO_GP: + { + unsigned long op1 = arm_decode_field (given, 21, 22); + unsigned long op2 = arm_decode_field (given, 5, 6); + unsigned long u = arm_decode_field (given, 23, 23); + + if ((op2 == 0) && (u == 1)) + { + if ((op1 == 0) || (op1 == 1)) + { + *undefined_code = UNDEF_BAD_U_OP1_OP2; + return TRUE; + } + else + return FALSE; + } + else if (op2 == 2) + { + if ((op1 == 0) || (op1 == 1)) + { + *undefined_code = UNDEF_BAD_OP1_OP2; + return TRUE; + } + else + return FALSE; + } + + return FALSE; + } + + case MVE_VMOV_GP_TO_VEC_LANE: + if (arm_decode_field (given, 5, 6) == 2) + { + unsigned long op1 = arm_decode_field (given, 21, 22); + if ((op1 == 0) || (op1 == 1)) + { + *undefined_code = UNDEF_BAD_OP1_OP2; + return TRUE; + } + else + return FALSE; + } + else + return FALSE; + + case MVE_VMOV_VEC_TO_VEC: + if ((arm_decode_field (given, 5, 5) == 1) + || (arm_decode_field (given, 22, 22) == 1)) + return TRUE; + return FALSE; + + case MVE_VMOV_IMM_TO_VEC: + if (arm_decode_field (given, 5, 5) == 0) + { + unsigned long cmode = arm_decode_field (given, 8, 11); + + if (((cmode & 9) == 1) || ((cmode & 5) == 1)) + { + *undefined_code = UNDEF_OP_0_BAD_CMODE; + return TRUE; + } + else + return FALSE; + } + else + return FALSE; + + case MVE_VSHLL_T2: + case MVE_VMOVN: + if (arm_decode_field (given, 18, 19) == 2) + { + *undefined_code = UNDEF_SIZE_2; + return TRUE; + } + else + return FALSE; + + case MVE_VRMLALDAVH: + case MVE_VMLADAV_T1: + case MVE_VMLADAV_T2: + case MVE_VMLALDAV: + if ((arm_decode_field (given, 28, 28) == 1) + && (arm_decode_field (given, 12, 12) == 1)) + { + *undefined_code = UNDEF_XCHG_UNS; + return TRUE; + } + else + return FALSE; + + case MVE_VQSHRN: + case MVE_VQSHRUN: + case MVE_VSHLL_T1: + case MVE_VSHRN: + { + unsigned long sz = arm_decode_field (given, 19, 20); + if (sz == 1) + return FALSE; + else if ((sz & 2) == 2) + return FALSE; + else + { + *undefined_code = UNDEF_SIZE; + return TRUE; + } + } + break; + + case MVE_VQSHL_T2: + case MVE_VQSHLU_T3: + case MVE_VRSHR: + case MVE_VSHL_T1: + case MVE_VSHR: + case MVE_VSLI: + case MVE_VSRI: + { + unsigned long sz = arm_decode_field (given, 19, 21); + if ((sz & 7) == 1) + return FALSE; + else if ((sz & 6) == 2) + return FALSE; + else if ((sz & 4) == 4) + return FALSE; + else + { + *undefined_code = UNDEF_SIZE; + return TRUE; + } + } + + case MVE_VQRSHRN: + case MVE_VQRSHRUN: + if (arm_decode_field (given, 19, 20) == 0) + { + *undefined_code = UNDEF_SIZE_0; + return TRUE; + } + else + return FALSE; + + case MVE_VABS_VEC: + if (arm_decode_field (given, 18, 19) == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else + return FALSE; + + case MVE_VQNEG: + case MVE_VQABS: + case MVE_VNEG_VEC: + case MVE_VCLS: + case MVE_VCLZ: + if (arm_decode_field (given, 18, 19) == 3) + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + else + return FALSE; + + case MVE_VREV16: + if (arm_decode_field (given, 18, 19) == 0) + return FALSE; + else + { + *undefined_code = UNDEF_SIZE_NOT_0; + return TRUE; + } + + case MVE_VREV32: + { + unsigned long size = arm_decode_field (given, 18, 19); + if ((size & 2) == 2) + { + *undefined_code = UNDEF_SIZE_2; + return TRUE; + } + else + return FALSE; + } + + case MVE_VREV64: + if (arm_decode_field (given, 18, 19) != 3) + return FALSE; + else + { + *undefined_code = UNDEF_SIZE_3; + return TRUE; + } + + default: + return FALSE; + } +} + +/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN. + Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to + why this encoding is unpredictable. */ + +static bfd_boolean +is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn, + enum mve_unpredictable *unpredictable_code) +{ + *unpredictable_code = UNPRED_NONE; + + switch (matched_insn) + { + case MVE_VCMP_FP_T2: + case MVE_VPT_FP_T2: + if ((arm_decode_field (given, 12, 12) == 0) + && (arm_decode_field (given, 5, 5) == 1)) + { + *unpredictable_code = UNPRED_FCA_0_FCB_1; + return TRUE; + } + else + return FALSE; + + case MVE_VPT_VEC_T4: + case MVE_VPT_VEC_T5: + case MVE_VPT_VEC_T6: + case MVE_VCMP_VEC_T4: + case MVE_VCMP_VEC_T5: + case MVE_VCMP_VEC_T6: + if (arm_decode_field (given, 0, 3) == 0xd) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else + return FALSE; + + case MVE_VDUP: + { + unsigned long gpr = arm_decode_field (given, 12, 15); + if (gpr == 0xd) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else if (gpr == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + return FALSE; + } + + case MVE_VQADD_T2: + case MVE_VQSUB_T2: + case MVE_VMUL_FP_T2: + case MVE_VMUL_VEC_T2: + case MVE_VMLA: + case MVE_VBRSR: + case MVE_VADD_FP_T2: + case MVE_VSUB_FP_T2: + case MVE_VADD_VEC_T2: + case MVE_VSUB_VEC_T2: + case MVE_VQRSHL_T2: + case MVE_VQSHL_T1: + case MVE_VRSHL_T2: + case MVE_VSHL_T2: + case MVE_VSHLC: + case MVE_VQDMLAH: + case MVE_VQRDMLAH: + case MVE_VQDMLASH: + case MVE_VQRDMLASH: + case MVE_VQDMULH_T3: + case MVE_VQRDMULH_T4: + case MVE_VMLAS: + case MVE_VFMA_FP_SCALAR: + case MVE_VFMAS_FP_SCALAR: + case MVE_VHADD_T2: + case MVE_VHSUB_T2: + { + unsigned long gpr = arm_decode_field (given, 0, 3); + if (gpr == 0xd) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else if (gpr == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + return FALSE; + } + + case MVE_VLD2: + case MVE_VST2: + { + unsigned long rn = arm_decode_field (given, 16, 19); + + if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) + { + *unpredictable_code = UNPRED_R13_AND_WB; + return TRUE; + } + + if (rn == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6) + { + *unpredictable_code = UNPRED_Q_GT_6; + return TRUE; + } + else + return FALSE; + } + + case MVE_VLD4: + case MVE_VST4: + { + unsigned long rn = arm_decode_field (given, 16, 19); + + if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) + { + *unpredictable_code = UNPRED_R13_AND_WB; + return TRUE; + } + + if (rn == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4) + { + *unpredictable_code = UNPRED_Q_GT_4; + return TRUE; + } + else + return FALSE; + } + + case MVE_VLDRB_T5: + case MVE_VLDRH_T6: + case MVE_VLDRW_T7: + case MVE_VSTRB_T5: + case MVE_VSTRH_T6: + case MVE_VSTRW_T7: + { + unsigned long rn = arm_decode_field (given, 16, 19); + + if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)) + { + *unpredictable_code = UNPRED_R13_AND_WB; + return TRUE; + } + else if (rn == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + else + return FALSE; + } + + case MVE_VLDRB_GATHER_T1: + if (arm_decode_field (given, 0, 0) == 1) + { + *unpredictable_code = UNPRED_OS; + return TRUE; + } + + /* fall through. */ + /* To handle common code with T2-T4 variants. */ + case MVE_VLDRH_GATHER_T2: + case MVE_VLDRW_GATHER_T3: + case MVE_VLDRD_GATHER_T4: + { + unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); + unsigned long qm = arm_decode_field_multiple (given, 1, 3, 5, 5); + + if (qd == qm) + { + *unpredictable_code = UNPRED_Q_REGS_EQUAL; + return TRUE; + } + + if (arm_decode_field (given, 16, 19) == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + return FALSE; + } + + case MVE_VLDRW_GATHER_T5: + case MVE_VLDRD_GATHER_T6: + { + unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); + unsigned long qm = arm_decode_field_multiple (given, 17, 19, 7, 7); + + if (qd == qm) + { + *unpredictable_code = UNPRED_Q_REGS_EQUAL; + return TRUE; + } + else + return FALSE; + } + + case MVE_VSTRB_SCATTER_T1: + if (arm_decode_field (given, 16, 19) == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + else if (arm_decode_field (given, 0, 0) == 1) + { + *unpredictable_code = UNPRED_OS; + return TRUE; + } + else + return FALSE; + + case MVE_VSTRH_SCATTER_T2: + case MVE_VSTRW_SCATTER_T3: + case MVE_VSTRD_SCATTER_T4: + if (arm_decode_field (given, 16, 19) == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + else + return FALSE; + + case MVE_VMOV2_VEC_LANE_TO_GP: + case MVE_VMOV2_GP_TO_VEC_LANE: + case MVE_VCVT_BETWEEN_FP_INT: + case MVE_VCVT_FROM_FP_TO_INT: + { + unsigned long rt = arm_decode_field (given, 0, 3); + unsigned long rt2 = arm_decode_field (given, 16, 19); + + if ((rt == 0xd) || (rt2 == 0xd)) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else if ((rt == 0xf) || (rt2 == 0xf)) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + else if (rt == rt2) + { + *unpredictable_code = UNPRED_GP_REGS_EQUAL; + return TRUE; + } + + return FALSE; + } + + case MVE_VMAXV: + case MVE_VMAXAV: + case MVE_VMAXNMV_FP: + case MVE_VMAXNMAV_FP: + case MVE_VMINNMV_FP: + case MVE_VMINNMAV_FP: + case MVE_VMINV: + case MVE_VMINAV: + case MVE_VABAV: + case MVE_VMOV_HFP_TO_GP: + case MVE_VMOV_GP_TO_VEC_LANE: + case MVE_VMOV_VEC_LANE_TO_GP: + { + unsigned long rda = arm_decode_field (given, 12, 15); + if (rda == 0xd) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else if (rda == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + return FALSE; + } + + case MVE_VMULL_INT: + { + unsigned long Qd; + unsigned long Qm; + unsigned long Qn; + + if (arm_decode_field (given, 20, 21) == 2) + { + Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); + Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); + Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); + + if ((Qd == Qn) || (Qd == Qm)) + { + *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; + return TRUE; + } + else + return FALSE; + } + else + return FALSE; + } + + case MVE_VCMUL_FP: + case MVE_VQDMULL_T1: + { + unsigned long Qd; + unsigned long Qm; + unsigned long Qn; + + if (arm_decode_field (given, 28, 28) == 1) + { + Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); + Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); + Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); + + if ((Qd == Qn) || (Qd == Qm)) + { + *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; + return TRUE; + } + else + return FALSE; + } + else + return FALSE; + } + + case MVE_VQDMULL_T2: + { + unsigned long gpr = arm_decode_field (given, 0, 3); + if (gpr == 0xd) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else if (gpr == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + if (arm_decode_field (given, 28, 28) == 1) + { + unsigned long Qd + = arm_decode_field_multiple (given, 13, 15, 22, 22); + unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); + + if (Qd == Qn) + { + *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; + return TRUE; + } + else + return FALSE; + } + + return FALSE; + } + + case MVE_VMLSLDAV: + case MVE_VRMLSLDAVH: + case MVE_VMLALDAV: + case MVE_VADDLV: + if (arm_decode_field (given, 20, 22) == 6) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else + return FALSE; + + case MVE_VDWDUP: + case MVE_VIWDUP: + if (arm_decode_field (given, 1, 3) == 6) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else + return FALSE; + + case MVE_VCADD_VEC: + case MVE_VHCADD: + { + unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); + unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); + if ((Qd == Qm) && arm_decode_field (given, 20, 21) == 2) + { + *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_2; + return TRUE; + } + else + return FALSE; + } + + case MVE_VCADD_FP: + { + unsigned long Qd = arm_decode_field_multiple (given, 13, 15, 22, 22); + unsigned long Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); + if ((Qd == Qm) && arm_decode_field (given, 20, 20) == 1) + { + *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; + return TRUE; + } + else + return FALSE; + } + + case MVE_VCMLA_FP: + { + unsigned long Qda; + unsigned long Qm; + unsigned long Qn; + + if (arm_decode_field (given, 20, 20) == 1) + { + Qda = arm_decode_field_multiple (given, 13, 15, 22, 22); + Qm = arm_decode_field_multiple (given, 1, 3, 5, 5); + Qn = arm_decode_field_multiple (given, 17, 19, 7, 7); + + if ((Qda == Qn) || (Qda == Qm)) + { + *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1; + return TRUE; + } + else + return FALSE; + } + else + return FALSE; + + } + + case MVE_VCTP: + if (arm_decode_field (given, 16, 19) == 0xd) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else + return FALSE; + + case MVE_VREV64: + { + unsigned long qd = arm_decode_field_multiple (given, 13, 15, 22, 22); + unsigned long qm = arm_decode_field_multiple (given, 1, 3, 6, 6); + + if (qd == qm) + { + *unpredictable_code = UNPRED_Q_REGS_EQUAL; + return TRUE; + } + else + return FALSE; + } + + case MVE_LSLL: + case MVE_LSLLI: + case MVE_LSRL: + case MVE_ASRL: + case MVE_ASRLI: + case MVE_UQSHLL: + case MVE_UQRSHLL: + case MVE_URSHRL: + case MVE_SRSHRL: + case MVE_SQSHLL: + case MVE_SQRSHRL: + { + unsigned long gpr = arm_decode_field (given, 9, 11); + gpr = ((gpr << 1) | 1); + if (gpr == 0xd) + { + *unpredictable_code = UNPRED_R13; + return TRUE; + } + else if (gpr == 0xf) + { + *unpredictable_code = UNPRED_R15; + return TRUE; + } + + return FALSE; + } + + default: + return FALSE; + } +} + +static void +print_mve_vmov_index (struct disassemble_info *info, unsigned long given) +{ + unsigned long op1 = arm_decode_field (given, 21, 22); + unsigned long op2 = arm_decode_field (given, 5, 6); + unsigned long h = arm_decode_field (given, 16, 16); + unsigned long index_operand, esize, targetBeat, idx; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + if ((op1 & 0x2) == 0x2) + { + index_operand = op2; + esize = 8; + } + else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1)) + { + index_operand = op2 >> 1; + esize = 16; + } + else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0)) + { + index_operand = 0; + esize = 32; + } + else + { + func (stream, ""); + return; + } + + targetBeat = (op1 & 0x1) | (h << 1); + idx = index_operand + targetBeat * (32/esize); + + func (stream, "%lu", idx); +} + +/* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits + in length and integer of floating-point type. */ +static void +print_simd_imm8 (struct disassemble_info *info, unsigned long given, + unsigned int ibit_loc, const struct mopcode32 *insn) +{ + int bits = 0; + int cmode = (given >> 8) & 0xf; + int op = (given >> 5) & 0x1; + unsigned long value = 0, hival = 0; + unsigned shift; + int size = 0; + int isfloat = 0; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + /* On Neon the 'i' bit is at bit 24, on mve it is + at bit 28. */ + bits |= ((given >> ibit_loc) & 1) << 7; + bits |= ((given >> 16) & 7) << 4; + bits |= ((given >> 0) & 15) << 0; + + if (cmode < 8) + { + shift = (cmode >> 1) & 3; + value = (unsigned long) bits << (8 * shift); + size = 32; + } + else if (cmode < 12) + { + shift = (cmode >> 1) & 1; + value = (unsigned long) bits << (8 * shift); + size = 16; + } + else if (cmode < 14) + { + shift = (cmode & 1) + 1; + value = (unsigned long) bits << (8 * shift); + value |= (1ul << (8 * shift)) - 1; + size = 32; + } + else if (cmode == 14) + { + if (op) + { + /* Bit replication into bytes. */ + int ix; + unsigned long mask; + + value = 0; + hival = 0; + for (ix = 7; ix >= 0; ix--) + { + mask = ((bits >> ix) & 1) ? 0xff : 0; + if (ix <= 3) + value = (value << 8) | mask; + else + hival = (hival << 8) | mask; + } + size = 64; + } + else + { + /* Byte replication. */ + value = (unsigned long) bits; + size = 8; + } + } + else if (!op) + { + /* Floating point encoding. */ + int tmp; + + value = (unsigned long) (bits & 0x7f) << 19; + value |= (unsigned long) (bits & 0x80) << 24; + tmp = bits & 0x40 ? 0x3c : 0x40; + value |= (unsigned long) tmp << 24; + size = 32; + isfloat = 1; + } + else + { + func (stream, "", + bits, cmode, op); + size = 32; + return; + } + + // printU determines whether the immediate value should be printed as + // unsigned. + unsigned printU = 0; + switch (insn->mve_op) + { + default: + break; + // We want this for instructions that don't have a 'signed' type + case MVE_VBIC_IMM: + case MVE_VORR_IMM: + case MVE_VMVN_IMM: + case MVE_VMOV_IMM_TO_VEC: + printU = 1; + break; + } + switch (size) + { + case 8: + func (stream, "#%ld\t; 0x%.2lx", value, value); + break; + + case 16: + func (stream, + printU + ? "#%lu\t; 0x%.4lx" + : "#%ld\t; 0x%.4lx", value, value); + break; + + case 32: + if (isfloat) + { + unsigned char valbytes[4]; + double fvalue; + + /* Do this a byte at a time so we don't have to + worry about the host's endianness. */ + valbytes[0] = value & 0xff; + valbytes[1] = (value >> 8) & 0xff; + valbytes[2] = (value >> 16) & 0xff; + valbytes[3] = (value >> 24) & 0xff; + + floatformat_to_double + (& floatformat_ieee_single_little, valbytes, + & fvalue); + + func (stream, "#%.7g\t; 0x%.8lx", fvalue, + value); + } + else + func (stream, + printU + ? "#%lu\t; 0x%.8lx" + : "#%ld\t; 0x%.8lx", + (long) (((value & 0x80000000L) != 0) + && !printU + ? value | ~0xffffffffL : value), + value); + break; + + case 64: + func (stream, "#0x%.8lx%.8lx", hival, value); + break; + + default: + abort (); + } + +} + +static void +print_mve_undefined (struct disassemble_info *info, + enum mve_undefined undefined_code) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + func (stream, "\t\tundefined instruction: "); + + switch (undefined_code) + { + case UNDEF_SIZE: + func (stream, "illegal size"); + break; + + case UNDEF_SIZE_0: + func (stream, "size equals zero"); + break; + + case UNDEF_SIZE_2: + func (stream, "size equals two"); + break; + + case UNDEF_SIZE_3: + func (stream, "size equals three"); + break; + + case UNDEF_SIZE_LE_1: + func (stream, "size <= 1"); + break; + + case UNDEF_SIZE_NOT_0: + func (stream, "size not equal to 0"); + break; + + case UNDEF_SIZE_NOT_2: + func (stream, "size not equal to 2"); + break; + + case UNDEF_SIZE_NOT_3: + func (stream, "size not equal to 3"); + break; + + case UNDEF_NOT_UNS_SIZE_0: + func (stream, "not unsigned and size = zero"); + break; + + case UNDEF_NOT_UNS_SIZE_1: + func (stream, "not unsigned and size = one"); + break; + + case UNDEF_NOT_UNSIGNED: + func (stream, "not unsigned"); + break; + + case UNDEF_VCVT_IMM6: + func (stream, "invalid imm6"); + break; + + case UNDEF_VCVT_FSI_IMM6: + func (stream, "fsi = 0 and invalid imm6"); + break; + + case UNDEF_BAD_OP1_OP2: + func (stream, "bad size with op2 = 2 and op1 = 0 or 1"); + break; + + case UNDEF_BAD_U_OP1_OP2: + func (stream, "unsigned with op2 = 0 and op1 = 0 or 1"); + break; + + case UNDEF_OP_0_BAD_CMODE: + func (stream, "op field equal 0 and bad cmode"); + break; + + case UNDEF_XCHG_UNS: + func (stream, "exchange and unsigned together"); + break; + + case UNDEF_NONE: + break; + } + +} + +static void +print_mve_unpredictable (struct disassemble_info *info, + enum mve_unpredictable unpredict_code) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION); + + switch (unpredict_code) + { + case UNPRED_IT_BLOCK: + func (stream, "mve instruction in it block"); + break; + + case UNPRED_FCA_0_FCB_1: + func (stream, "condition bits, fca = 0 and fcb = 1"); + break; + + case UNPRED_R13: + func (stream, "use of r13 (sp)"); + break; + + case UNPRED_R15: + func (stream, "use of r15 (pc)"); + break; + + case UNPRED_Q_GT_4: + func (stream, "start register block > r4"); + break; + + case UNPRED_Q_GT_6: + func (stream, "start register block > r6"); + break; + + case UNPRED_R13_AND_WB: + func (stream, "use of r13 and write back"); + break; + + case UNPRED_Q_REGS_EQUAL: + func (stream, + "same vector register used for destination and other operand"); + break; + + case UNPRED_OS: + func (stream, "use of offset scaled"); + break; + + case UNPRED_GP_REGS_EQUAL: + func (stream, "same general-purpose register used for both operands"); + break; + + case UNPRED_Q_REGS_EQ_AND_SIZE_1: + func (stream, "use of identical q registers and size = 1"); + break; + + case UNPRED_Q_REGS_EQ_AND_SIZE_2: + func (stream, "use of identical q registers and size = 1"); + break; + + case UNPRED_NONE: + break; + } +} + +/* Print register block operand for mve vld2/vld4/vst2/vld4. */ + +static void +print_mve_register_blocks (struct disassemble_info *info, + unsigned long given, + enum mve_instructions matched_insn) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + unsigned long q_reg_start = arm_decode_field_multiple (given, + 13, 15, + 22, 22); + switch (matched_insn) + { + case MVE_VLD2: + case MVE_VST2: + if (q_reg_start <= 6) + func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1); + else + func (stream, "", q_reg_start); + break; + + case MVE_VLD4: + case MVE_VST4: + if (q_reg_start <= 4) + func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start, + q_reg_start + 1, q_reg_start + 2, + q_reg_start + 3); + else + func (stream, "", q_reg_start); + break; + + default: + break; + } +} + +static void +print_mve_rounding_mode (struct disassemble_info *info, + unsigned long given, + enum mve_instructions matched_insn) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + switch (matched_insn) + { + case MVE_VCVT_FROM_FP_TO_INT: + { + switch (arm_decode_field (given, 8, 9)) + { + case 0: + func (stream, "a"); + break; + + case 1: + func (stream, "n"); + break; + + case 2: + func (stream, "p"); + break; + + case 3: + func (stream, "m"); + break; + + default: + break; + } + } + break; + + case MVE_VRINT_FP: + { + switch (arm_decode_field (given, 7, 9)) + { + case 0: + func (stream, "n"); + break; + + case 1: + func (stream, "x"); + break; + + case 2: + func (stream, "a"); + break; + + case 3: + func (stream, "z"); + break; + + case 5: + func (stream, "m"); + break; + + case 7: + func (stream, "p"); + + case 4: + case 6: + default: + break; + } + } + break; + + default: + break; + } +} + +static void +print_mve_vcvt_size (struct disassemble_info *info, + unsigned long given, + enum mve_instructions matched_insn) +{ + unsigned long mode = 0; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + switch (matched_insn) + { + case MVE_VCVT_FP_FIX_VEC: + { + mode = (((given & 0x200) >> 7) + | ((given & 0x10000000) >> 27) + | ((given & 0x100) >> 8)); + + switch (mode) + { + case 0: + func (stream, "f16.s16"); + break; + + case 1: + func (stream, "s16.f16"); + break; + + case 2: + func (stream, "f16.u16"); + break; + + case 3: + func (stream, "u16.f16"); + break; + + case 4: + func (stream, "f32.s32"); + break; + + case 5: + func (stream, "s32.f32"); + break; + + case 6: + func (stream, "f32.u32"); + break; + + case 7: + func (stream, "u32.f32"); + break; + + default: + break; + } + break; + } + case MVE_VCVT_BETWEEN_FP_INT: + { + unsigned long size = arm_decode_field (given, 18, 19); + unsigned long op = arm_decode_field (given, 7, 8); + + if (size == 1) + { + switch (op) + { + case 0: + func (stream, "f16.s16"); + break; + + case 1: + func (stream, "f16.u16"); + break; + + case 2: + func (stream, "s16.f16"); + break; + + case 3: + func (stream, "u16.f16"); + break; + + default: + break; + } + } + else if (size == 2) + { + switch (op) + { + case 0: + func (stream, "f32.s32"); + break; + + case 1: + func (stream, "f32.u32"); + break; + + case 2: + func (stream, "s32.f32"); + break; + + case 3: + func (stream, "u32.f32"); + break; + } + } + } + break; + + case MVE_VCVT_FP_HALF_FP: + { + unsigned long op = arm_decode_field (given, 28, 28); + if (op == 0) + func (stream, "f16.f32"); + else if (op == 1) + func (stream, "f32.f16"); + } + break; + + case MVE_VCVT_FROM_FP_TO_INT: + { + unsigned long size = arm_decode_field_multiple (given, 7, 7, 18, 19); + + switch (size) + { + case 2: + func (stream, "s16.f16"); + break; + + case 3: + func (stream, "u16.f16"); + break; + + case 4: + func (stream, "s32.f32"); + break; + + case 5: + func (stream, "u32.f32"); + break; + + default: + break; + } + } + break; + + default: + break; + } +} + +static void +print_mve_rotate (struct disassemble_info *info, unsigned long rot, + unsigned long rot_width) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + if (rot_width == 1) + { + switch (rot) + { + case 0: + func (stream, "90"); + break; + case 1: + func (stream, "270"); + break; + default: + break; + } + } + else if (rot_width == 2) + { + switch (rot) + { + case 0: + func (stream, "0"); + break; + case 1: + func (stream, "90"); + break; + case 2: + func (stream, "180"); + break; + case 3: + func (stream, "270"); + break; + default: + break; + } + } +} + +static void +print_instruction_predicate (struct disassemble_info *info) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + if (vpt_block_state.next_pred_state == PRED_THEN) + func (stream, "t"); + else if (vpt_block_state.next_pred_state == PRED_ELSE) + func (stream, "e"); +} + +static void +print_mve_size (struct disassemble_info *info, + unsigned long size, + enum mve_instructions matched_insn) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + switch (matched_insn) + { + case MVE_VABAV: + case MVE_VABD_VEC: + case MVE_VABS_FP: + case MVE_VABS_VEC: + case MVE_VADD_VEC_T1: + case MVE_VADD_VEC_T2: + case MVE_VADDV: + case MVE_VBRSR: + case MVE_VCADD_VEC: + case MVE_VCLS: + case MVE_VCLZ: + case MVE_VCMP_VEC_T1: + case MVE_VCMP_VEC_T2: + case MVE_VCMP_VEC_T3: + case MVE_VCMP_VEC_T4: + case MVE_VCMP_VEC_T5: + case MVE_VCMP_VEC_T6: + case MVE_VCTP: + case MVE_VDDUP: + case MVE_VDWDUP: + case MVE_VHADD_T1: + case MVE_VHADD_T2: + case MVE_VHCADD: + case MVE_VHSUB_T1: + case MVE_VHSUB_T2: + case MVE_VIDUP: + case MVE_VIWDUP: + case MVE_VLD2: + case MVE_VLD4: + case MVE_VLDRB_GATHER_T1: + case MVE_VLDRH_GATHER_T2: + case MVE_VLDRW_GATHER_T3: + case MVE_VLDRD_GATHER_T4: + case MVE_VLDRB_T1: + case MVE_VLDRH_T2: + case MVE_VMAX: + case MVE_VMAXA: + case MVE_VMAXV: + case MVE_VMAXAV: + case MVE_VMIN: + case MVE_VMINA: + case MVE_VMINV: + case MVE_VMINAV: + case MVE_VMLA: + case MVE_VMLAS: + case MVE_VMUL_VEC_T1: + case MVE_VMUL_VEC_T2: + case MVE_VMULH: + case MVE_VRMULH: + case MVE_VMULL_INT: + case MVE_VNEG_FP: + case MVE_VNEG_VEC: + case MVE_VPT_VEC_T1: + case MVE_VPT_VEC_T2: + case MVE_VPT_VEC_T3: + case MVE_VPT_VEC_T4: + case MVE_VPT_VEC_T5: + case MVE_VPT_VEC_T6: + case MVE_VQABS: + case MVE_VQADD_T1: + case MVE_VQADD_T2: + case MVE_VQDMLADH: + case MVE_VQRDMLADH: + case MVE_VQDMLAH: + case MVE_VQRDMLAH: + case MVE_VQDMLASH: + case MVE_VQRDMLASH: + case MVE_VQDMLSDH: + case MVE_VQRDMLSDH: + case MVE_VQDMULH_T1: + case MVE_VQRDMULH_T2: + case MVE_VQDMULH_T3: + case MVE_VQRDMULH_T4: + case MVE_VQNEG: + case MVE_VQRSHL_T1: + case MVE_VQRSHL_T2: + case MVE_VQSHL_T1: + case MVE_VQSHL_T4: + case MVE_VQSUB_T1: + case MVE_VQSUB_T2: + case MVE_VREV32: + case MVE_VREV64: + case MVE_VRHADD: + case MVE_VRINT_FP: + case MVE_VRSHL_T1: + case MVE_VRSHL_T2: + case MVE_VSHL_T2: + case MVE_VSHL_T3: + case MVE_VSHLL_T2: + case MVE_VST2: + case MVE_VST4: + case MVE_VSTRB_SCATTER_T1: + case MVE_VSTRH_SCATTER_T2: + case MVE_VSTRW_SCATTER_T3: + case MVE_VSTRB_T1: + case MVE_VSTRH_T2: + case MVE_VSUB_VEC_T1: + case MVE_VSUB_VEC_T2: + if (size <= 3) + func (stream, "%s", mve_vec_sizename[size]); + else + func (stream, ""); + break; + + case MVE_VABD_FP: + case MVE_VADD_FP_T1: + case MVE_VADD_FP_T2: + case MVE_VSUB_FP_T1: + case MVE_VSUB_FP_T2: + case MVE_VCMP_FP_T1: + case MVE_VCMP_FP_T2: + case MVE_VFMA_FP_SCALAR: + case MVE_VFMA_FP: + case MVE_VFMS_FP: + case MVE_VFMAS_FP_SCALAR: + case MVE_VMAXNM_FP: + case MVE_VMAXNMA_FP: + case MVE_VMAXNMV_FP: + case MVE_VMAXNMAV_FP: + case MVE_VMINNM_FP: + case MVE_VMINNMA_FP: + case MVE_VMINNMV_FP: + case MVE_VMINNMAV_FP: + case MVE_VMUL_FP_T1: + case MVE_VMUL_FP_T2: + case MVE_VPT_FP_T1: + case MVE_VPT_FP_T2: + if (size == 0) + func (stream, "32"); + else if (size == 1) + func (stream, "16"); + break; + + case MVE_VCADD_FP: + case MVE_VCMLA_FP: + case MVE_VCMUL_FP: + case MVE_VMLADAV_T1: + case MVE_VMLALDAV: + case MVE_VMLSDAV_T1: + case MVE_VMLSLDAV: + case MVE_VMOVN: + case MVE_VQDMULL_T1: + case MVE_VQDMULL_T2: + case MVE_VQMOVN: + case MVE_VQMOVUN: + if (size == 0) + func (stream, "16"); + else if (size == 1) + func (stream, "32"); + break; + + case MVE_VMOVL: + if (size == 1) + func (stream, "8"); + else if (size == 2) + func (stream, "16"); + break; + + case MVE_VDUP: + switch (size) + { + case 0: + func (stream, "32"); + break; + case 1: + func (stream, "16"); + break; + case 2: + func (stream, "8"); + break; + default: + break; + } + break; + + case MVE_VMOV_GP_TO_VEC_LANE: + case MVE_VMOV_VEC_LANE_TO_GP: + switch (size) + { + case 0: case 4: + func (stream, "32"); + break; + + case 1: case 3: + case 5: case 7: + func (stream, "16"); + break; + + case 8: case 9: case 10: case 11: + case 12: case 13: case 14: case 15: + func (stream, "8"); + break; + + default: + break; + } + break; + + case MVE_VMOV_IMM_TO_VEC: + switch (size) + { + case 0: case 4: case 8: + case 12: case 24: case 26: + func (stream, "i32"); + break; + case 16: case 20: + func (stream, "i16"); + break; + case 28: + func (stream, "i8"); + break; + case 29: + func (stream, "i64"); + break; + case 30: + func (stream, "f32"); + break; + default: + break; + } + break; + + case MVE_VMULL_POLY: + if (size == 0) + func (stream, "p8"); + else if (size == 1) + func (stream, "p16"); + break; + + case MVE_VMVN_IMM: + switch (size) + { + case 0: case 2: case 4: + case 6: case 12: case 13: + func (stream, "32"); + break; + + case 8: case 10: + func (stream, "16"); + break; + + default: + break; + } + break; + + case MVE_VBIC_IMM: + case MVE_VORR_IMM: + switch (size) + { + case 1: case 3: + case 5: case 7: + func (stream, "32"); + break; + + case 9: case 11: + func (stream, "16"); + break; + + default: + break; + } + break; + + case MVE_VQSHRN: + case MVE_VQSHRUN: + case MVE_VQRSHRN: + case MVE_VQRSHRUN: + case MVE_VRSHRN: + case MVE_VSHRN: + { + switch (size) + { + case 1: + func (stream, "16"); + break; + + case 2: case 3: + func (stream, "32"); + break; + + default: + break; + } + } + break; + + case MVE_VQSHL_T2: + case MVE_VQSHLU_T3: + case MVE_VRSHR: + case MVE_VSHL_T1: + case MVE_VSHLL_T1: + case MVE_VSHR: + case MVE_VSLI: + case MVE_VSRI: + { + switch (size) + { + case 1: + func (stream, "8"); + break; + + case 2: case 3: + func (stream, "16"); + break; + + case 4: case 5: case 6: case 7: + func (stream, "32"); + break; + + default: + break; + } + } + break; + + default: + break; + } +} + +static void +print_mve_shift_n (struct disassemble_info *info, long given, + enum mve_instructions matched_insn) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + int startAt0 + = matched_insn == MVE_VQSHL_T2 + || matched_insn == MVE_VQSHLU_T3 + || matched_insn == MVE_VSHL_T1 + || matched_insn == MVE_VSHLL_T1 + || matched_insn == MVE_VSLI; + + unsigned imm6 = (given & 0x3f0000) >> 16; + + if (matched_insn == MVE_VSHLL_T1) + imm6 &= 0x1f; + + unsigned shiftAmount = 0; + if ((imm6 & 0x20) != 0) + shiftAmount = startAt0 ? imm6 - 32 : 64 - imm6; + else if ((imm6 & 0x10) != 0) + shiftAmount = startAt0 ? imm6 - 16 : 32 - imm6; + else if ((imm6 & 0x08) != 0) + shiftAmount = startAt0 ? imm6 - 8 : 16 - imm6; + else + print_mve_undefined (info, UNDEF_SIZE_0); + + func (stream, "%u", shiftAmount); +} + +static void +print_vec_condition (struct disassemble_info *info, long given, + enum mve_instructions matched_insn) +{ + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + long vec_cond = 0; + + switch (matched_insn) + { + case MVE_VPT_FP_T1: + case MVE_VCMP_FP_T1: + vec_cond = (((given & 0x1000) >> 10) + | ((given & 1) << 1) + | ((given & 0x0080) >> 7)); + func (stream, "%s",vec_condnames[vec_cond]); + break; + + case MVE_VPT_FP_T2: + case MVE_VCMP_FP_T2: + vec_cond = (((given & 0x1000) >> 10) + | ((given & 0x0020) >> 4) + | ((given & 0x0080) >> 7)); + func (stream, "%s",vec_condnames[vec_cond]); + break; + + case MVE_VPT_VEC_T1: + case MVE_VCMP_VEC_T1: + vec_cond = (given & 0x0080) >> 7; + func (stream, "%s",vec_condnames[vec_cond]); + break; + + case MVE_VPT_VEC_T2: + case MVE_VCMP_VEC_T2: + vec_cond = 2 | ((given & 0x0080) >> 7); + func (stream, "%s",vec_condnames[vec_cond]); + break; + + case MVE_VPT_VEC_T3: + case MVE_VCMP_VEC_T3: + vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7); + func (stream, "%s",vec_condnames[vec_cond]); + break; + + case MVE_VPT_VEC_T4: + case MVE_VCMP_VEC_T4: + vec_cond = (given & 0x0080) >> 7; + func (stream, "%s",vec_condnames[vec_cond]); + break; + + case MVE_VPT_VEC_T5: + case MVE_VCMP_VEC_T5: + vec_cond = 2 | ((given & 0x0080) >> 7); + func (stream, "%s",vec_condnames[vec_cond]); + break; + + case MVE_VPT_VEC_T6: + case MVE_VCMP_VEC_T6: + vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7); + func (stream, "%s",vec_condnames[vec_cond]); + break; + + case MVE_NONE: + case MVE_VPST: + default: + break; + } +} + +#define W_BIT 21 +#define I_BIT 22 +#define U_BIT 23 +#define P_BIT 24 + +#define WRITEBACK_BIT_SET (given & (1 << W_BIT)) +#define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) +#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) +#define PRE_BIT_SET (given & (1 << P_BIT)) + + +/* Print one coprocessor instruction on INFO->STREAM. + Return TRUE if the instuction matched, FALSE if this is not a + recognised coprocessor instruction. */ + +static bfd_boolean +print_insn_coprocessor_1 (const struct sopcode32 *opcodes, + bfd_vma pc, + struct disassemble_info *info, + long given, + bfd_boolean thumb) +{ + const struct sopcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + unsigned long mask; + unsigned long value = 0; + int cond; + int cp_num; + struct arm_private_data *private_data = info->private_data; + arm_feature_set allowed_arches = ARM_ARCH_NONE; + arm_feature_set arm_ext_v8_1m_main = + ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN); + + allowed_arches = private_data->features; + + for (insn = opcodes; insn->assembler; insn++) + { + unsigned long u_reg = 16; + bfd_boolean is_unpredictable = FALSE; + signed long value_in_comment = 0; + const char *c; + + if (ARM_FEATURE_ZERO (insn->arch)) + switch (insn->value) + { + case SENTINEL_IWMMXT_START: + if (info->mach != bfd_mach_arm_XScale + && info->mach != bfd_mach_arm_iWMMXt + && info->mach != bfd_mach_arm_iWMMXt2) + do + insn++; + while ((! ARM_FEATURE_ZERO (insn->arch)) + && insn->value != SENTINEL_IWMMXT_END); + continue; + + case SENTINEL_IWMMXT_END: + continue; + + case SENTINEL_GENERIC_START: + allowed_arches = private_data->features; + continue; + + default: + abort (); + } + + mask = insn->mask; + value = insn->value; + cp_num = (given >> 8) & 0xf; + + if (thumb) + { + /* The high 4 bits are 0xe for Arm conditional instructions, and + 0xe for arm unconditional instructions. The rest of the + encoding is the same. */ + mask |= 0xf0000000; + value |= 0xe0000000; + if (ifthen_state) + cond = IFTHEN_COND; + else + cond = COND_UNCOND; + } + else + { + /* Only match unconditional instuctions against unconditional + patterns. */ + if ((given & 0xf0000000) == 0xf0000000) + { + mask |= 0xf0000000; + cond = COND_UNCOND; + } + else + { + cond = (given >> 28) & 0xf; + if (cond == 0xe) + cond = COND_UNCOND; + } + } + + if ((insn->isa == T32 && !thumb) + || (insn->isa == ARM && thumb)) + continue; + + if ((given & mask) != value) + continue; + + if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) + continue; + + if (insn->value == 0xfe000010 /* mcr2 */ + || insn->value == 0xfe100010 /* mrc2 */ + || insn->value == 0xfc100000 /* ldc2 */ + || insn->value == 0xfc000000) /* stc2 */ + { + if (cp_num == 9 || cp_num == 10 || cp_num == 11) + is_unpredictable = TRUE; + + /* Armv8.1-M Mainline FP & MVE instructions. */ + if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) + && !ARM_CPU_IS_ANY (allowed_arches) + && (cp_num == 8 || cp_num == 14 || cp_num == 15)) + continue; + + } + else if (insn->value == 0x0e000000 /* cdp */ + || insn->value == 0xfe000000 /* cdp2 */ + || insn->value == 0x0e000010 /* mcr */ + || insn->value == 0x0e100010 /* mrc */ + || insn->value == 0x0c100000 /* ldc */ + || insn->value == 0x0c000000) /* stc */ + { + /* Floating-point instructions. */ + if (cp_num == 9 || cp_num == 10 || cp_num == 11) + continue; + + /* Armv8.1-M Mainline FP & MVE instructions. */ + if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches) + && !ARM_CPU_IS_ANY (allowed_arches) + && (cp_num == 8 || cp_num == 14 || cp_num == 15)) + continue; + } + else if ((insn->value == 0xec100f80 /* vldr (system register) */ + || insn->value == 0xec000f80) /* vstr (system register) */ + && arm_decode_field (given, 24, 24) == 0 + && arm_decode_field (given, 21, 21) == 0) + /* If the P and W bits are both 0 then these encodings match the MVE + VLDR and VSTR instructions, these are in a different table, so we + don't let it match here. */ + continue; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') { - switch (*++c) + const char mod = *++c; + switch (mod) { case '%': func (stream, "%%"); break; case 'A': + case 'K': { int rn = (given >> 16) & 0xf; - int offset = given & 0xff; + bfd_vma offset = given & 0xff; + + if (mod == 'K') + offset = given & 0x7f; func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); if (PRE_BIT_SET || WRITEBACK_BIT_SET) { /* Not unindexed. The offset is scaled. */ - offset = offset * 4; + if (cp_num == 9) + /* vldr.16/vstr.16 will shift the address + left by 1 bit only. */ + offset = offset * 2; + else + offset = offset * 4; + if (NEGATIVE_BIT_SET) offset = - offset; if (rn != 15) @@ -1863,8 +8191,10 @@ print_insn_coprocessor (bfd_vma pc, { if (offset) func (stream, ", #%d]%s", - offset, + (int) offset, WRITEBACK_BIT_SET ? "!" : ""); + else if (NEGATIVE_BIT_SET) + func (stream, ", #-0]"); else func (stream, "]"); } @@ -1875,19 +8205,27 @@ print_insn_coprocessor (bfd_vma pc, if (WRITEBACK_BIT_SET) { if (offset) - func (stream, ", #%d", offset); + func (stream, ", #%d", (int) offset); + else if (NEGATIVE_BIT_SET) + func (stream, ", #-0"); } else { - func (stream, ", {%d}", offset); + func (stream, ", {%s%d}", + (NEGATIVE_BIT_SET && !offset) ? "-" : "", + (int) offset); value_in_comment = offset; } } if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) { func (stream, "\t; "); + /* For unaligned PCs, apply off-by-alignment + correction. */ info->print_address_func (offset + pc - + info->bytes_per_chunk * 2, info); + + info->bytes_per_chunk * 2 + - (pc & 3), + info); } } break; @@ -1902,11 +8240,46 @@ print_insn_coprocessor (bfd_vma pc, else if (regno + offset > 32) func (stream, "{d%d-}", regno, regno + offset - 1); else - func (stream, "{d%d-d%d}", regno, regno + offset - 1); + func (stream, "{d%d-d%d}", regno, regno + offset - 1); + } + break; + + case 'C': + { + bfd_boolean single = ((given >> 8) & 1) == 0; + char reg_prefix = single ? 's' : 'd'; + int Dreg = (given >> 22) & 0x1; + int Vdreg = (given >> 12) & 0xf; + int reg = single ? ((Vdreg << 1) | Dreg) + : ((Dreg << 4) | Vdreg); + int num = (given >> (single ? 0 : 1)) & 0x7f; + int maxreg = single ? 31 : 15; + int topreg = reg + num - 1; + + if (!num) + func (stream, "{VPR}"); + else if (num == 1) + func (stream, "{%c%d, VPR}", reg_prefix, reg); + else if (topreg > maxreg) + func (stream, "{%c%d-> 1 : topreg); + else + func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg, + reg_prefix, topreg); } break; + case 'u': + if (cond != COND_UNCOND) + is_unpredictable = TRUE; + + /* Fall through. */ case 'c': + if (cond != COND_UNCOND && cp_num == 9) + is_unpredictable = TRUE; + + /* Fall through. */ + case 'b': func (stream, "%s", arm_conditional[cond]); break; @@ -1922,13 +8295,45 @@ print_insn_coprocessor (bfd_vma pc, /* Is ``imm'' a negative number? */ if (imm & 0x40) - imm |= (-1 << 7); + imm -= 0x80; func (stream, "%d", imm); } break; + case 'J': + { + unsigned long regno + = arm_decode_field_multiple (given, 13, 15, 22, 22); + + switch (regno) + { + case 0x1: + func (stream, "FPSCR"); + break; + case 0x2: + func (stream, "FPSCR_nzcvqc"); + break; + case 0xc: + func (stream, "VPR"); + break; + case 0xd: + func (stream, "P0"); + break; + case 0xe: + func (stream, "FPCXTNS"); + break; + case 0xf: + func (stream, "FPCXTS"); + break; + default: + func (stream, "", regno); + break; + } + } + break; + case 'F': switch (given & 0x00408000) { @@ -2024,10 +8429,15 @@ print_insn_coprocessor (bfd_vma pc, } func (stream, "%s", arm_regnames[value]); break; + case 'V': + if (given & (1 << 6)) + goto Q; + /* FALLTHROUGH */ case 'D': func (stream, "d%ld", value); break; case 'Q': + Q: if (value & 1) func (stream, "", value >> 1); else @@ -2037,6 +8447,36 @@ print_insn_coprocessor (bfd_vma pc, func (stream, "%ld", value); value_in_comment = value; break; + case 'E': + { + /* Converts immediate 8 bit back to float value. */ + unsigned floatVal = (value & 0x80) << 24 + | (value & 0x3F) << 19 + | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); + + /* Quarter float have a maximum value of 31.0. + Get floating point value multiplied by 1e7. + The maximum value stays in limit of a 32-bit int. */ + unsigned decVal = + (78125 << (((floatVal >> 23) & 0xFF) - 124)) * + (16 + (value & 0xF)); + + if (!(decVal % 1000000)) + func (stream, "%ld\t; 0x%08x %c%u.%01u", value, + floatVal, value & 0x80 ? '-' : ' ', + decVal / 10000000, + decVal % 10000000 / 1000000); + else if (!(decVal % 10000)) + func (stream, "%ld\t; 0x%08x %c%u.%03u", value, + floatVal, value & 0x80 ? '-' : ' ', + decVal / 10000000, + decVal % 10000000 / 10000); + else + func (stream, "%ld\t; 0x%08x %c%u.%07u", value, + floatVal, value & 0x80 ? '-' : ' ', + decVal / 10000000, decVal % 10000000); + break; + } case 'k': { int from = (given & (1 << 7)) ? 32 : 16; @@ -2069,6 +8509,31 @@ print_insn_coprocessor (bfd_vma pc, func (stream, "0x%lx", (value & 0xffffffffUL)); break; + case 'c': + switch (value) + { + case 0: + func (stream, "eq"); + break; + + case 1: + func (stream, "vs"); + break; + + case 2: + func (stream, "ge"); + break; + + case 3: + func (stream, "gt"); + break; + + default: + func (stream, "??"); + break; + } + break; + case '`': c++; if (value == 0) @@ -2086,190 +8551,190 @@ print_insn_coprocessor (bfd_vma pc, default: abort (); } - break; - - case 'y': - case 'z': - { - int single = *c++ == 'y'; - int regno; + } + break; - switch (*c) - { - case '4': /* Sm pair */ - case '0': /* Sm, Dm */ - regno = given & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 5) & 1; - } - else - regno += ((given >> 5) & 1) << 4; - break; + case 'y': + case 'z': + { + int single = *c++ == 'y'; + int regno; - case '1': /* Sd, Dd */ - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - else - regno += ((given >> 22) & 1) << 4; - break; + switch (*c) + { + case '4': /* Sm pair */ + case '0': /* Sm, Dm */ + regno = given & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 5) & 1; + } + else + regno += ((given >> 5) & 1) << 4; + break; - case '2': /* Sn, Dn */ - regno = (given >> 16) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 7) & 1; - } - else - regno += ((given >> 7) & 1) << 4; - break; + case '1': /* Sd, Dd */ + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + else + regno += ((given >> 22) & 1) << 4; + break; - case '3': /* List */ - func (stream, "{"); - regno = (given >> 12) & 0x0000000f; - if (single) - { - regno <<= 1; - regno += (given >> 22) & 1; - } - else - regno += ((given >> 22) & 1) << 4; - break; + case '2': /* Sn, Dn */ + regno = (given >> 16) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 7) & 1; + } + else + regno += ((given >> 7) & 1) << 4; + break; - default: - abort (); - } + case '3': /* List */ + func (stream, "{"); + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + else + regno += ((given >> 22) & 1) << 4; + break; - func (stream, "%c%d", single ? 's' : 'd', regno); + default: + abort (); + } - if (*c == '3') - { - int count = given & 0xff; + func (stream, "%c%d", single ? 's' : 'd', regno); - if (single == 0) - count >>= 1; + if (*c == '3') + { + int count = given & 0xff; - if (--count) - { - func (stream, "-%c%d", - single ? 's' : 'd', - regno + count); - } + if (single == 0) + count >>= 1; - func (stream, "}"); - } - else if (*c == '4') - func (stream, ", %c%d", single ? 's' : 'd', - regno + 1); - } - break; + if (--count) + { + func (stream, "-%c%d", + single ? 's' : 'd', + regno + count); + } - case 'L': - switch (given & 0x00400100) - { - case 0x00000000: func (stream, "b"); break; - case 0x00400000: func (stream, "h"); break; - case 0x00000100: func (stream, "w"); break; - case 0x00400100: func (stream, "d"); break; - default: - break; + func (stream, "}"); } - break; + else if (*c == '4') + func (stream, ", %c%d", single ? 's' : 'd', + regno + 1); + } + break; - case 'Z': + case 'L': + switch (given & 0x00400100) { - /* given (20, 23) | given (0, 3) */ - value = ((given >> 16) & 0xf0) | (given & 0xf); - func (stream, "%d", value); + case 0x00000000: func (stream, "b"); break; + case 0x00400000: func (stream, "h"); break; + case 0x00000100: func (stream, "w"); break; + case 0x00400100: func (stream, "d"); break; + default: + break; } - break; + break; - case 'l': - /* This is like the 'A' operator, except that if - the width field "M" is zero, then the offset is - *not* multiplied by four. */ - { - int offset = given & 0xff; - int multiplier = (given & 0x00000100) ? 4 : 1; + case 'Z': + { + /* given (20, 23) | given (0, 3) */ + value = ((given >> 16) & 0xf0) | (given & 0xf); + func (stream, "%d", (int) value); + } + break; - func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + case 'l': + /* This is like the 'A' operator, except that if + the width field "M" is zero, then the offset is + *not* multiplied by four. */ + { + int offset = given & 0xff; + int multiplier = (given & 0x00000100) ? 4 : 1; - if (multiplier > 1) - { - value_in_comment = offset * multiplier; - if (NEGATIVE_BIT_SET) - value_in_comment = - value_in_comment; - } + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - if (offset) - { - if (PRE_BIT_SET) - func (stream, ", #%s%d]%s", - NEGATIVE_BIT_SET ? "-" : "", - offset * multiplier, - WRITEBACK_BIT_SET ? "!" : ""); - else - func (stream, "], #%s%d", - NEGATIVE_BIT_SET ? "-" : "", - offset * multiplier); - } - else - func (stream, "]"); - } - break; + if (multiplier > 1) + { + value_in_comment = offset * multiplier; + if (NEGATIVE_BIT_SET) + value_in_comment = - value_in_comment; + } - case 'r': - { - int imm4 = (given >> 4) & 0xf; - int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); - int ubit = ! NEGATIVE_BIT_SET; - const char *rm = arm_regnames [given & 0xf]; - const char *rn = arm_regnames [(given >> 16) & 0xf]; + if (offset) + { + if (PRE_BIT_SET) + func (stream, ", #%s%d]%s", + NEGATIVE_BIT_SET ? "-" : "", + offset * multiplier, + WRITEBACK_BIT_SET ? "!" : ""); + else + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", + offset * multiplier); + } + else + func (stream, "]"); + } + break; - switch (puw_bits) - { - case 1: - case 3: - func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); - if (imm4) - func (stream, ", lsl #%d", imm4); - break; + case 'r': + { + int imm4 = (given >> 4) & 0xf; + int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); + int ubit = ! NEGATIVE_BIT_SET; + const char *rm = arm_regnames [given & 0xf]; + const char *rn = arm_regnames [(given >> 16) & 0xf]; - case 4: - case 5: - case 6: - case 7: - func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); - if (imm4 > 0) - func (stream, ", lsl #%d", imm4); - func (stream, "]"); - if (puw_bits == 5 || puw_bits == 7) - func (stream, "!"); - break; + switch (puw_bits) + { + case 1: + case 3: + func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); + if (imm4) + func (stream, ", lsl #%d", imm4); + break; - default: - func (stream, "INVALID"); - } - } - break; + case 4: + case 5: + case 6: + case 7: + func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); + if (imm4 > 0) + func (stream, ", lsl #%d", imm4); + func (stream, "]"); + if (puw_bits == 5 || puw_bits == 7) + func (stream, "!"); + break; - case 'i': - { - long imm5; - imm5 = ((given & 0x100) >> 4) | (given & 0xf); - func (stream, "%ld", (imm5 == 0) ? 32 : imm5); - } - break; + default: + func (stream, "INVALID"); + } + } + break; - default: - abort (); + case 'i': + { + long imm5; + imm5 = ((given & 0x100) >> 4) | (given & 0xf); + func (stream, "%ld", (imm5 == 0) ? 32 : imm5); } + break; + + default: + abort (); } } else @@ -2287,6 +8752,26 @@ print_insn_coprocessor (bfd_vma pc, return FALSE; } +static bfd_boolean +print_insn_coprocessor (bfd_vma pc, + struct disassemble_info *info, + long given, + bfd_boolean thumb) +{ + return print_insn_coprocessor_1 (coprocessor_opcodes, + pc, info, given, thumb); +} + +static bfd_boolean +print_insn_generic_coprocessor (bfd_vma pc, + struct disassemble_info *info, + long given, + bfd_boolean thumb) +{ + return print_insn_coprocessor_1 (generic_coprocessor_opcodes, + pc, info, given, thumb); +} + /* Decodes and prints ARM addressing modes. Returns the offset used in the address, if any, if it is worthwhile printing the offset as a hexadecimal value in a comment at the end of the @@ -2297,7 +8782,7 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) { void *stream = info->stream; fprintf_ftype func = info->fprintf_func; - int offset = 0; + bfd_vma offset = 0; if (((given & 0x000f0000) == 0x000f0000) && ((given & 0x02000000) == 0)) @@ -2306,13 +8791,15 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "[pc"); - if (NEGATIVE_BIT_SET) - offset = - offset; - if (PRE_BIT_SET) { - /* Pre-indexed. */ - func (stream, ", #%d]", offset); + /* Pre-indexed. Elide offset of positive zero when + non-writeback. */ + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); + + if (NEGATIVE_BIT_SET) + offset = -offset; offset += pc + 8; @@ -2320,12 +8807,11 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) being used. Probably a very dangerous thing for the programmer to do, but who are we to argue ? */ - if (WRITEBACK_BIT_SET) - func (stream, "!"); + func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); } else /* Post indexed. */ { - func (stream, "], #%d", offset); + func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); /* Ie ignore the offset. */ offset = pc + 8; @@ -2344,15 +8830,14 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) { if ((given & 0x02000000) == 0) { + /* Elide offset of positive zero when non-writeback. */ offset = given & 0xfff; - if (offset) - func (stream, ", #%s%d", - NEGATIVE_BIT_SET ? "-" : "", offset); + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); } else { - func (stream, ", %s", - NEGATIVE_BIT_SET ? "-" : ""); + func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); arm_decode_shift (given, func, stream, TRUE); } @@ -2363,12 +8848,10 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) { if ((given & 0x02000000) == 0) { + /* Always show offset. */ offset = given & 0xfff; - if (offset) - func (stream, "], #%s%d", - NEGATIVE_BIT_SET ? "-" : "", offset); - else - func (stream, "]"); + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); } else { @@ -2377,11 +8860,147 @@ print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) arm_decode_shift (given, func, stream, TRUE); } } + if (NEGATIVE_BIT_SET) + offset = -offset; } return (signed long) offset; } + +/* Print one cde instruction on INFO->STREAM. + Return TRUE if the instuction matched, FALSE if this is not a + recognised cde instruction. */ +static bfd_boolean +print_insn_cde (struct disassemble_info *info, long given, bfd_boolean thumb) +{ + const struct cdeopcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + if (thumb) + { + /* Manually extract the coprocessor code from a known point. + This position is the same across all CDE instructions. */ + for (insn = cde_opcodes; insn->assembler; insn++) + { + uint16_t coproc = (given >> insn->coproc_shift) & insn->coproc_mask; + uint16_t coproc_mask = 1 << coproc; + if (! (coproc_mask & cde_coprocs)) + continue; + + if ((given & insn->mask) == insn->value) + { + bfd_boolean is_unpredictable = FALSE; + const char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + { + int width; + unsigned long value; + + c = arm_decode_bitfield (c, given, &value, &width); + + switch (*c) + { + case 'S': + if (value > 10) + is_unpredictable = TRUE; + /* Fall through. */ + case 'R': + if (value == 13) + is_unpredictable = TRUE; + /* Fall through. */ + case 'r': + func (stream, "%s", arm_regnames[value]); + break; + + case 'n': + if (value == 15) + func (stream, "%s", "APSR_nzcv"); + else + func (stream, "%s", arm_regnames[value]); + break; + + case 'T': + func (stream, "%s", arm_regnames[value + 1]); + break; + + case 'd': + func (stream, "%ld", value); + break; + + case 'V': + if (given & (1 << 6)) + func (stream, "q%ld", value >> 1); + else if (given & (1 << 24)) + func (stream, "d%ld", value); + else + { + /* Encoding for S register is different than for D and + Q registers. S registers are encoded using the top + single bit in position 22 as the lowest bit of the + register number, while for Q and D it represents the + highest bit of the register number. */ + uint8_t top_bit = (value >> 4) & 1; + uint8_t tmp = (value << 1) & 0x1e; + uint8_t res = tmp | top_bit; + func (stream, "s%u", res); + } + break; + + default: + abort (); + } + } + break; + + case 'p': + { + uint8_t proc_number = (given >> 8) & 0x7; + func (stream, "p%u", proc_number); + break; + } + + case 'a': + { + uint8_t a_offset = 28; + if (given & (1 << a_offset)) + func (stream, "a"); + break; + } + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + + return TRUE; + } + } + return FALSE; + } + else + return FALSE; +} + + /* Print one neon instruction on INFO->STREAM. Return TRUE if the instuction matched, FALSE if this is not a recognised neon instruction. */ @@ -2408,15 +9027,21 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) } else if ((given & 0xff000000) == 0xf9000000) given ^= 0xf9000000 ^ 0xf4000000; - else + /* BFloat16 neon instructions without special top byte handling. */ + else if ((given & 0xff000000) == 0xfe000000 + || (given & 0xff000000) == 0xfc000000) + ; + /* vdup is also a valid neon instruction. */ + else if ((given & 0xff910f5f) != 0xee800b10) return FALSE; } - + for (insn = neon_opcodes; insn->assembler; insn++) { if ((given & insn->mask) == insn->value) { signed long value_in_comment = 0; + bfd_boolean is_unpredictable = FALSE; const char *c; for (c = insn->assembler; *c; c++) @@ -2429,6 +9054,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "%%"); break; + case 'u': + if (thumb && ifthen_state) + is_unpredictable = TRUE; + + /* Fall through. */ case 'c': if (thumb && ifthen_state) func (stream, "%s", arm_conditional[IFTHEN_COND]); @@ -2436,7 +9066,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) case 'A': { - static const unsigned char enc[16] = + static const unsigned char enc[16] = { 0x4, 0x14, /* st4 0,1 */ 0x4, /* st1 2 */ @@ -2458,7 +9088,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) int n = enc[type] & 0xf; int stride = (enc[type] >> 4) + 1; int ix; - + func (stream, "{"); if (stride > 1) for (ix = 0; ix != n; ix++) @@ -2469,7 +9099,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, "d%d-d%d", rd, rd + n - 1); func (stream, "}, [%s", arm_regnames[rn]); if (align) - func (stream, ", :%d", 32 << align); + func (stream, " :%d", 32 << align); func (stream, "]"); if (rm == 0xd) func (stream, "!"); @@ -2477,7 +9107,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, ", %s", arm_regnames[rm]); } break; - + case 'B': { int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); @@ -2493,7 +9123,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) if (length > 1 && size > 0) stride = (idx_align & (1 << size)) ? 2 : 1; - + switch (length) { case 1: @@ -2510,19 +9140,19 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) } } break; - + case 2: if (size == 2 && (idx_align & 2) != 0) return FALSE; align = (idx_align & 1) ? 16 << size : 0; break; - + case 3: if ((size == 2 && (idx_align & 3) != 0) || (idx_align & 1) != 0) return FALSE; break; - + case 4: if (size == 2) { @@ -2533,18 +9163,18 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) else align = (idx_align & 1) ? 32 << size : 0; break; - + default: abort (); } - + func (stream, "{"); for (i = 0; i < length; i++) func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", rd + i * stride, idx); func (stream, "}, [%s", arm_regnames[rn]); if (align) - func (stream, ", :%d", align); + func (stream, " :%d", align); func (stream, "]"); if (rm == 0xd) func (stream, "!"); @@ -2552,7 +9182,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, ", %s", arm_regnames[rm]); } break; - + case 'C': { int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); @@ -2564,12 +9194,12 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) int n = type + 1; int stride = ((given >> 5) & 0x1); int ix; - + if (stride && (n == 1)) n++; else stride++; - + func (stream, "{"); if (stride > 1) for (ix = 0; ix != n; ix++) @@ -2585,9 +9215,9 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) if (type == 3) align = (size > 1) ? align >> 1 : align; if (type == 2 || (type == 0 && !size)) - func (stream, ", :", align); + func (stream, " :", align); else - func (stream, ", :%d", align); + func (stream, " :%d", align); } func (stream, "]"); if (rm == 0xd) @@ -2596,18 +9226,18 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) func (stream, ", %s", arm_regnames[rm]); } break; - + case 'D': { int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); int size = (given >> 20) & 3; int reg = raw_reg & ((4 << size) - 1); int ix = raw_reg >> size >> 2; - + func (stream, "d%d[%d]", reg, ix); } break; - + case 'E': /* Neon encoded constant for mov, mvn, vorr, vbic. */ { @@ -2618,11 +9248,11 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) unsigned shift; int size = 0; int isfloat = 0; - + bits |= ((given >> 24) & 1) << 7; bits |= ((given >> 16) & 7) << 4; bits |= ((given >> 0) & 15) << 0; - + if (cmode < 8) { shift = (cmode >> 1) & 3; @@ -2649,7 +9279,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) /* Bit replication into bytes. */ int ix; unsigned long mask; - + value = 0; hival = 0; for (ix = 7; ix >= 0; ix--) @@ -2673,7 +9303,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) { /* Floating point encoding. */ int tmp; - + value = (unsigned long) (bits & 0x7f) << 19; value |= (unsigned long) (bits & 0x80) << 24; tmp = bits & 0x40 ? 0x3c : 0x40; @@ -2683,72 +9313,350 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) } else { - func (stream, "", - bits, cmode, op); - size = 32; - break; + func (stream, "", + bits, cmode, op); + size = 32; + break; + } + switch (size) + { + case 8: + func (stream, "#%ld\t; 0x%.2lx", value, value); + break; + + case 16: + func (stream, "#%ld\t; 0x%.4lx", value, value); + break; + + case 32: + if (isfloat) + { + unsigned char valbytes[4]; + double fvalue; + + /* Do this a byte at a time so we don't have to + worry about the host's endianness. */ + valbytes[0] = value & 0xff; + valbytes[1] = (value >> 8) & 0xff; + valbytes[2] = (value >> 16) & 0xff; + valbytes[3] = (value >> 24) & 0xff; + + floatformat_to_double + (& floatformat_ieee_single_little, valbytes, + & fvalue); + + func (stream, "#%.7g\t; 0x%.8lx", fvalue, + value); + } + else + func (stream, "#%ld\t; 0x%.8lx", + (long) (((value & 0x80000000L) != 0) + ? value | ~0xffffffffL : value), + value); + break; + + case 64: + func (stream, "#0x%.8lx%.8lx", hival, value); + break; + + default: + abort (); + } + } + break; + + case 'F': + { + int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); + int num = (given >> 8) & 0x3; + + if (!num) + func (stream, "{d%d}", regno); + else if (num + regno >= 32) + func (stream, "{d%d-= '0' && *c <= '9') + limit = *c - '0'; + else if (*c >= 'a' && *c <= 'f') + limit = *c - 'a' + 10; + else + abort (); + low = limit >> 2; + high = limit & 3; + + if (value < low || value > high) + func (stream, "", base << value); + else + func (stream, "%d", base << value); + } + break; + case 'R': + if (given & (1 << 6)) + goto Q; + /* FALLTHROUGH */ + case 'D': + func (stream, "d%ld", value); + break; + case 'Q': + Q: + if (value & 1) + func (stream, "", value >> 1); + else + func (stream, "q%ld", value >> 1); + break; + + case '`': + c++; + if (value == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if (value == ((1ul << width) - 1)) + func (stream, "%c", *c); + break; + case '?': + func (stream, "%c", c[(1 << width) - (int) value]); + c += 1 << width; + break; + default: + abort (); + } + } + break; + + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + + if (value_in_comment > 32 || value_in_comment < -16) + func (stream, "\t; 0x%lx", value_in_comment); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); + + return TRUE; + } + } + return FALSE; +} + +/* Print one mve instruction on INFO->STREAM. + Return TRUE if the instuction matched, FALSE if this is not a + recognised mve instruction. */ + +static bfd_boolean +print_insn_mve (struct disassemble_info *info, long given) +{ + const struct mopcode32 *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + + for (insn = mve_opcodes; insn->assembler; insn++) + { + if (((given & insn->mask) == insn->value) + && !is_mve_encoding_conflict (given, insn->mve_op)) + { + signed long value_in_comment = 0; + bfd_boolean is_unpredictable = FALSE; + bfd_boolean is_undefined = FALSE; + const char *c; + enum mve_unpredictable unpredictable_cond = UNPRED_NONE; + enum mve_undefined undefined_cond = UNDEF_NONE; + + /* Most vector mve instruction are illegal in a it block. + There are a few exceptions; check for them. */ + if (ifthen_state && !is_mve_okay_in_it (insn->mve_op)) + { + is_unpredictable = TRUE; + unpredictable_cond = UNPRED_IT_BLOCK; + } + else if (is_mve_unpredictable (given, insn->mve_op, + &unpredictable_cond)) + is_unpredictable = TRUE; + + if (is_mve_undefined (given, insn->mve_op, &undefined_cond)) + is_undefined = TRUE; + + /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV, + i.e "VMOV Qd, Qm". */ + if ((insn->mve_op == MVE_VORR_REG) + && (arm_decode_field (given, 1, 3) + == arm_decode_field (given, 17, 19))) + continue; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case '%': + func (stream, "%%"); + break; + + case 'a': + /* Don't print anything for '+' as it is implied. */ + if (arm_decode_field (given, 23, 23) == 0) + func (stream, "-"); + break; + + case 'c': + if (ifthen_state) + func (stream, "%s", arm_conditional[IFTHEN_COND]); + break; + + case 'd': + print_mve_vld_str_addr (info, given, insn->mve_op); + break; + + case 'i': + { + long mve_mask = mve_extract_pred_mask (given); + func (stream, "%s", mve_predicatenames[mve_mask]); + } + break; + + case 'j': + { + unsigned int imm5 = 0; + imm5 |= arm_decode_field (given, 6, 7); + imm5 |= (arm_decode_field (given, 12, 14) << 2); + func (stream, "#%u", (imm5 == 0) ? 32 : imm5); + } + break; + + case 'k': + func (stream, "#%u", + (arm_decode_field (given, 7, 7) == 0) ? 64 : 48); + break; + + case 'n': + print_vec_condition (info, given, insn->mve_op); + break; + + case 'o': + if (arm_decode_field (given, 0, 0) == 1) + { + unsigned long size + = arm_decode_field (given, 4, 4) + | (arm_decode_field (given, 6, 6) << 1); + + func (stream, ", uxtw #%lu", size); + } + break; + + case 'm': + print_mve_rounding_mode (info, given, insn->mve_op); + break; + + case 's': + print_mve_vcvt_size (info, given, insn->mve_op); + break; + + case 'u': + { + unsigned long op1 = arm_decode_field (given, 21, 22); + + if ((insn->mve_op == MVE_VMOV_VEC_LANE_TO_GP)) + { + /* Check for signed. */ + if (arm_decode_field (given, 23, 23) == 0) + { + /* We don't print 's' for S32. */ + if ((arm_decode_field (given, 5, 6) == 0) + && ((op1 == 0) || (op1 == 1))) + ; + else + func (stream, "s"); + } + else + func (stream, "u"); + } + else + { + if (arm_decode_field (given, 28, 28) == 0) + func (stream, "s"); + else + func (stream, "u"); } - switch (size) - { - case 8: - func (stream, "#%ld\t; 0x%.2lx", value, value); - break; - - case 16: - func (stream, "#%ld\t; 0x%.4lx", value, value); - break; + } + break; - case 32: - if (isfloat) - { - unsigned char valbytes[4]; - double fvalue; - - /* Do this a byte at a time so we don't have to - worry about the host's endianness. */ - valbytes[0] = value & 0xff; - valbytes[1] = (value >> 8) & 0xff; - valbytes[2] = (value >> 16) & 0xff; - valbytes[3] = (value >> 24) & 0xff; - - floatformat_to_double - (& floatformat_ieee_single_little, valbytes, - & fvalue); - - func (stream, "#%.7g\t; 0x%.8lx", fvalue, - value); - } - else - func (stream, "#%ld\t; 0x%.8lx", - (long) (((value & 0x80000000L) != 0) - ? value | ~0xffffffffL : value), - value); - break; + case 'v': + print_instruction_predicate (info); + break; - case 64: - func (stream, "#0x%.8lx%.8lx", hival, value); - break; - - default: - abort (); - } - } + case 'w': + if (arm_decode_field (given, 21, 21) == 1) + func (stream, "!"); break; - - case 'F': - { - int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); - int num = (given >> 8) & 0x3; - - if (!num) - func (stream, "{d%d}", regno); - else if (num + regno >= 32) - func (stream, "{d%d-mve_op); + break; + + case 'E': + /* SIMD encoded constant for mov, mvn, vorr, vbic. */ + + print_simd_imm8 (info, given, 28, insn); + break; + + case 'N': + print_mve_vmov_index (info, given); + break; + + case 'T': + if (arm_decode_field (given, 12, 12) == 0) + func (stream, "b"); + else + func (stream, "t"); + break; + + case 'X': + if (arm_decode_field (given, 12, 12) == 1) + func (stream, "x"); break; - case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': @@ -2757,79 +9665,165 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) unsigned long value; c = arm_decode_bitfield (c, given, &value, &width); - + switch (*c) { - case 'r': - func (stream, "%s", arm_regnames[value]); + case 'Z': + if (value == 13) + is_unpredictable = TRUE; + else if (value == 15) + func (stream, "zr"); + else + func (stream, "%s", arm_regnames[value]); break; - case 'd': - func (stream, "%ld", value); - value_in_comment = value; + + case 'c': + func (stream, "%s", arm_conditional[value]); break; - case 'e': - func (stream, "%ld", (1ul << width) - value); + + case 'C': + value ^= 1; + func (stream, "%s", arm_conditional[value]); break; - + case 'S': - case 'T': - case 'U': - /* Various width encodings. */ + if (value == 13 || value == 15) + is_unpredictable = TRUE; + else + func (stream, "%s", arm_regnames[value]); + break; + + case 's': + print_mve_size (info, + value, + insn->mve_op); + break; + case 'I': + if (value == 1) + func (stream, "i"); + break; + case 'A': + if (value == 1) + func (stream, "a"); + break; + case 'h': { - int base = 8 << (*c - 'S'); /* 8,16 or 32 */ - int limit; - unsigned low, high; + unsigned int odd_reg = (value << 1) | 1; + func (stream, "%s", arm_regnames[odd_reg]); + } + break; + case 'i': + { + unsigned long imm + = arm_decode_field (given, 0, 6); + unsigned long mod_imm = imm; - c++; - if (*c >= '0' && *c <= '9') - limit = *c - '0'; - else if (*c >= 'a' && *c <= 'f') - limit = *c - 'a' + 10; - else - abort (); - low = limit >> 2; - high = limit & 3; + switch (insn->mve_op) + { + case MVE_VLDRW_GATHER_T5: + case MVE_VSTRW_SCATTER_T5: + mod_imm = mod_imm << 2; + break; + case MVE_VSTRD_SCATTER_T6: + case MVE_VLDRD_GATHER_T6: + mod_imm = mod_imm << 3; + break; + + default: + break; + } - if (value < low || value > high) - func (stream, "", base << value); - else - func (stream, "%d", base << value); + func (stream, "%lu", mod_imm); } break; - case 'R': - if (given & (1 << 6)) - goto Q; - /* FALLTHROUGH */ - case 'D': - func (stream, "d%ld", value); + case 'k': + func (stream, "%lu", 64 - value); break; - case 'Q': - Q: - if (value & 1) - func (stream, "", value >> 1); + case 'l': + { + unsigned int even_reg = value << 1; + func (stream, "%s", arm_regnames[even_reg]); + } + break; + case 'u': + switch (value) + { + case 0: + func (stream, "1"); + break; + case 1: + func (stream, "2"); + break; + case 2: + func (stream, "4"); + break; + case 3: + func (stream, "8"); + break; + default: + break; + } + break; + case 'o': + print_mve_rotate (info, value, width); + break; + case 'r': + func (stream, "%s", arm_regnames[value]); + break; + case 'd': + if (insn->mve_op == MVE_VQSHL_T2 + || insn->mve_op == MVE_VQSHLU_T3 + || insn->mve_op == MVE_VRSHR + || insn->mve_op == MVE_VRSHRN + || insn->mve_op == MVE_VSHL_T1 + || insn->mve_op == MVE_VSHLL_T1 + || insn->mve_op == MVE_VSHR + || insn->mve_op == MVE_VSHRN + || insn->mve_op == MVE_VSLI + || insn->mve_op == MVE_VSRI) + print_mve_shift_n (info, given, insn->mve_op); + else if (insn->mve_op == MVE_VSHLL_T2) + { + switch (value) + { + case 0x00: + func (stream, "8"); + break; + case 0x01: + func (stream, "16"); + break; + case 0x10: + print_mve_undefined (info, UNDEF_SIZE_0); + break; + default: + assert (0); + break; + } + } else - func (stream, "q%ld", value >> 1); + { + if (insn->mve_op == MVE_VSHLC && value == 0) + value = 32; + func (stream, "%ld", value); + value_in_comment = value; + } break; - - case '`': - c++; - if (value == 0) - func (stream, "%c", *c); + case 'F': + func (stream, "s%ld", value); break; - case '\'': - c++; - if (value == ((1ul << width) - 1)) - func (stream, "%c", *c); + case 'Q': + if (value & 0x8) + func (stream, "", value); + else + func (stream, "q%ld", value); break; - case '?': - func (stream, "%c", c[(1 << width) - (int) value]); - c += 1 << width; + case 'x': + func (stream, "0x%08lx", value); break; default: abort (); } break; - default: abort (); } @@ -2842,12 +9836,94 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) if (value_in_comment > 32 || value_in_comment < -16) func (stream, "\t; 0x%lx", value_in_comment); + if (is_unpredictable) + print_mve_unpredictable (info, unpredictable_cond); + + if (is_undefined) + print_mve_undefined (info, undefined_cond); + + if ((vpt_block_state.in_vpt_block == FALSE) + && !ifthen_state + && (is_vpt_instruction (given) == TRUE)) + mark_inside_vpt_block (given); + else if (vpt_block_state.in_vpt_block == TRUE) + update_vpt_block_state (); + return TRUE; } } return FALSE; } + +/* Return the name of a v7A special register. */ + +static const char * +banked_regname (unsigned reg) +{ + switch (reg) + { + case 15: return "CPSR"; + case 32: return "R8_usr"; + case 33: return "R9_usr"; + case 34: return "R10_usr"; + case 35: return "R11_usr"; + case 36: return "R12_usr"; + case 37: return "SP_usr"; + case 38: return "LR_usr"; + case 40: return "R8_fiq"; + case 41: return "R9_fiq"; + case 42: return "R10_fiq"; + case 43: return "R11_fiq"; + case 44: return "R12_fiq"; + case 45: return "SP_fiq"; + case 46: return "LR_fiq"; + case 48: return "LR_irq"; + case 49: return "SP_irq"; + case 50: return "LR_svc"; + case 51: return "SP_svc"; + case 52: return "LR_abt"; + case 53: return "SP_abt"; + case 54: return "LR_und"; + case 55: return "SP_und"; + case 60: return "LR_mon"; + case 61: return "SP_mon"; + case 62: return "ELR_hyp"; + case 63: return "SP_hyp"; + case 79: return "SPSR"; + case 110: return "SPSR_fiq"; + case 112: return "SPSR_irq"; + case 114: return "SPSR_svc"; + case 116: return "SPSR_abt"; + case 118: return "SPSR_und"; + case 124: return "SPSR_mon"; + case 126: return "SPSR_hyp"; + default: return NULL; + } +} + +/* Return the name of the DMB/DSB option. */ +static const char * +data_barrier_option (unsigned option) +{ + switch (option & 0xf) + { + case 0xf: return "sy"; + case 0xe: return "st"; + case 0xd: return "ld"; + case 0xb: return "ish"; + case 0xa: return "ishst"; + case 0x9: return "ishld"; + case 0x7: return "un"; + case 0x6: return "unst"; + case 0x5: return "nshld"; + case 0x3: return "osh"; + case 0x2: return "oshst"; + case 0x1: return "oshld"; + default: return NULL; + } +} + /* Print one ARM instruction from PC on INFO->STREAM. */ static void @@ -2864,12 +9940,15 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (print_insn_neon (info, given, FALSE)) return; + if (print_insn_generic_coprocessor (pc, info, given, FALSE)) + return; + for (insn = arm_opcodes; insn->assembler; insn++) { if ((given & insn->mask) != insn->value) continue; - - if ((insn->arch & private_data->features.core) == 0) + + if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) continue; /* Special case: an instruction with all bits set in the condition field @@ -2909,26 +9988,30 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'S': allow_unpredictable = TRUE; + /* Fall through. */ case 's': if ((given & 0x004f0000) == 0x004f0000) { /* PC relative with immediate offset. */ - int offset = ((given & 0xf00) >> 4) | (given & 0xf); - - if (NEGATIVE_BIT_SET) - offset = - offset; + bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); if (PRE_BIT_SET) { - if (offset) - func (stream, "[pc, #%d]\t; ", offset); + /* Elide positive zero offset. */ + if (offset || NEGATIVE_BIT_SET) + func (stream, "[pc, #%s%d]\t; ", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); else - func (stream, "[pc]\t; "); + func (stream, "[pc]\t; "); + if (NEGATIVE_BIT_SET) + offset = -offset; info->print_address_func (offset + pc + 8, info); } else { - func (stream, "[pc], #%d", offset); + /* Always show the offset. */ + func (stream, "[pc], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", (int) offset); if (! allow_unpredictable) is_unpredictable = TRUE; } @@ -2937,9 +10020,6 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { int offset = ((given & 0xf00) >> 4) | (given & 0xf); - if (NEGATIVE_BIT_SET) - offset = - offset; - func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); @@ -2947,13 +10027,15 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { if (IMMEDIATE_BIT_SET) { - if (WRITEBACK_BIT_SET) - /* Immediate Pre-indexed. */ - /* PR 10924: Offset must be printed, even if it is zero. */ - func (stream, ", #%d", offset); - else if (offset) - /* Immediate Offset: printing zero offset is optional. */ - func (stream, ", #%d", offset); + /* Elide offset for non-writeback + positive zero. */ + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET + || offset) + func (stream, ", #%s%d", + NEGATIVE_BIT_SET ? "-" : "", offset); + + if (NEGATIVE_BIT_SET) + offset = -offset; value_in_comment = offset; } @@ -2981,7 +10063,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { /* Immediate Post-indexed. */ /* PR 10924: Offset must be printed, even if it is zero. */ - func (stream, "], #%d", offset); + func (stream, "], #%s%d", + NEGATIVE_BIT_SET ? "-" : "", offset); + if (NEGATIVE_BIT_SET) + offset = -offset; value_in_comment = offset; } else @@ -3015,8 +10100,14 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'b': { - int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); - info->print_address_func (disp * 4 + pc + 8, info); + bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); + bfd_vma target = disp * 4 + pc + 8; + info->print_address_func (target, info); + + /* Fill in instruction information. */ + info->insn_info_valid = 1; + info->insn_type = dis_branch; + info->target = target; } break; @@ -3053,13 +10144,23 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'o': if ((given & 0x02000000) != 0) { - int rotate = (given & 0xf00) >> 7; - int immed = (given & 0xff); - - immed = (((immed << (32 - rotate)) - | (immed >> rotate)) & 0xffffffff); - func (stream, "#%d", immed); - value_in_comment = immed; + unsigned int rotate = (given & 0xf00) >> 7; + unsigned int immed = (given & 0xff); + unsigned int a, i; + + a = (immed << ((32 - rotate) & 31) + | immed >> rotate) & 0xffffffff; + /* If there is another encoding with smaller rotate, + the rotate should be specified directly. */ + for (i = 0; i < 32; i += 2) + if ((a << i | a >> ((32 - i) & 31)) <= 0xff) + break; + + if (i != rotate) + func (stream, "#%d, %d", immed, rotate); + else + func (stream, "#%d", a); + value_in_comment = a; } else arm_decode_shift (given, func, stream, TRUE); @@ -3068,11 +10169,17 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) case 'p': if ((given & 0x0000f000) == 0x0000f000) { + arm_feature_set arm_ext_v6 = + ARM_FEATURE_CORE_LOW (ARM_EXT_V6); + /* The p-variants of tst/cmp/cmn/teq are the pre-V6 mechanism for setting PSR flag bits. They are obsolete in V6 onwards. */ - if ((private_data->features.core & ARM_EXT_V6) == 0) + if (! ARM_CPU_HAS_FEATURE (private_data->features, \ + arm_ext_v6)) func (stream, "p"); + else + is_unpredictable = TRUE; } break; @@ -3095,7 +10202,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) { if (offset) func (stream, ", #%d]%s", - value_in_comment, + (int) value_in_comment, WRITEBACK_BIT_SET ? "!" : ""); else func (stream, "]"); @@ -3107,11 +10214,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (WRITEBACK_BIT_SET) { if (offset) - func (stream, ", #%d", value_in_comment); + func (stream, ", #%d", (int) value_in_comment); } else { - func (stream, ", {%d}", offset); + func (stream, ", {%d}", (int) offset); value_in_comment = offset; } } @@ -3138,31 +10245,61 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) address += 2; info->print_address_func (address, info); + + /* Fill in instruction information. */ + info->insn_info_valid = 1; + info->insn_type = dis_branch; + info->target = address; } break; case 'C': - func (stream, "_"); - if (given & 0x80000) - func (stream, "f"); - if (given & 0x40000) - func (stream, "s"); - if (given & 0x20000) - func (stream, "x"); - if (given & 0x10000) - func (stream, "c"); + if ((given & 0x02000200) == 0x200) + { + const char * name; + unsigned sysm = (given & 0x004f0000) >> 16; + + sysm |= (given & 0x300) >> 4; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } + else + { + func (stream, "%cPSR_", + (given & 0x00400000) ? 'S' : 'C'); + if (given & 0x80000) + func (stream, "f"); + if (given & 0x40000) + func (stream, "s"); + if (given & 0x20000) + func (stream, "x"); + if (given & 0x10000) + func (stream, "c"); + } break; case 'U': - switch (given & 0xf) + if ((given & 0xf0) == 0x60) { - case 0xf: func (stream, "sy"); break; - case 0x7: func (stream, "un"); break; - case 0xe: func (stream, "st"); break; - case 0x6: func (stream, "unst"); break; - default: - func (stream, "#%d", (int) given & 0xf); - break; + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } + } + else + { + const char * opt = data_barrier_option (given & 0xf); + if (opt != NULL) + func (stream, "%s", opt); + else + func (stream, "#%d", (int) given & 0xf); } break; @@ -3173,7 +10310,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) unsigned long value; c = arm_decode_bitfield (c, given, &value, &width); - + switch (*c) { case 'R': @@ -3181,6 +10318,11 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) is_unpredictable = TRUE; /* Fall through. */ case 'r': + case 'T': + /* We want register + 1 when decoding T. */ + if (*c == 'T') + value = (value + 1) & 0xf; + if (c[1] == 'u') { /* Eat the 'u' character. */ @@ -3244,49 +10386,65 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) default: abort (); } - break; + } + break; - case 'e': - { - int imm; + case 'e': + { + int imm; - imm = (given & 0xf) | ((given & 0xfff00) >> 4); - func (stream, "%d", imm); - value_in_comment = imm; - } - break; + imm = (given & 0xf) | ((given & 0xfff00) >> 4); + func (stream, "%d", imm); + value_in_comment = imm; + } + break; - case 'E': - /* LSB and WIDTH fields of BFI or BFC. The machine- - language instruction encodes LSB and MSB. */ - { - long msb = (given & 0x001f0000) >> 16; - long lsb = (given & 0x00000f80) >> 7; - long w = msb - lsb + 1; + case 'E': + /* LSB and WIDTH fields of BFI or BFC. The machine- + language instruction encodes LSB and MSB. */ + { + long msb = (given & 0x001f0000) >> 16; + long lsb = (given & 0x00000f80) >> 7; + long w = msb - lsb + 1; - if (w > 0) - func (stream, "#%lu, #%lu", lsb, w); - else - func (stream, "(invalid: %lu:%lu)", lsb, msb); - } - break; + if (w > 0) + func (stream, "#%lu, #%lu", lsb, w); + else + func (stream, "(invalid: %lu:%lu)", lsb, msb); + } + break; - case 'V': - /* 16-bit unsigned immediate from a MOVT or MOVW - instruction, encoded in bits 0:11 and 15:19. */ - { - long hi = (given & 0x000f0000) >> 4; - long lo = (given & 0x00000fff); - long imm16 = hi | lo; + case 'R': + /* Get the PSR/banked register name. */ + { + const char * name; + unsigned sysm = (given & 0x004f0000) >> 16; - func (stream, "#%lu", imm16); - value_in_comment = imm16; - } - break; + sysm |= (given & 0x300) >> 4; + name = banked_regname (sysm); - default: - abort (); + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } + break; + + case 'V': + /* 16-bit unsigned immediate from a MOVT or MOVW + instruction, encoded in bits 0:11 and 15:19. */ + { + long hi = (given & 0x000f0000) >> 4; + long lo = (given & 0x00000fff); + long imm16 = hi | lo; + + func (stream, "#%lu", imm16); + value_in_comment = imm16; } + break; + + default: + abort (); } } else @@ -3302,7 +10460,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) return; } } - abort (); + func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); + return; } /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ @@ -3426,14 +10585,14 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) if (started) func (stream, ", "); started = 1; - func (stream, arm_regnames[14] /* "lr" */); + func (stream, "%s", arm_regnames[14] /* "lr" */); } if (domaskpc) { if (started) func (stream, ", "); - func (stream, arm_regnames[15] /* "pc" */); + func (stream, "%s", arm_regnames[15] /* "pc" */); } func (stream, "}"); @@ -3446,7 +10605,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) mask. */ if ((given & (1 << ((given & 0x0700) >> 8))) == 0) func (stream, "!"); - break; + break; case 'b': /* Print ARM V6T2 CZB address: pc+4+6 bits. */ @@ -3455,6 +10614,11 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) + ((given & 0x00f8) >> 2) + ((given & 0x0200) >> 3)); info->print_address_func (address, info); + + /* Fill in instruction information. */ + info->insn_info_valid = 1; + info->insn_type = dis_branch; + info->target = address; } break; @@ -3482,7 +10646,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) { case '-': { - long reg; + bfd_vma reg; c++; while (*c >= '0' && *c <= '9') @@ -3499,17 +10663,17 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) break; case 'd': - func (stream, "%ld", reg); + func (stream, "%ld", (long) reg); value_in_comment = reg; break; case 'H': - func (stream, "%ld", reg << 1); + func (stream, "%ld", (long) (reg << 1)); value_in_comment = reg << 1; break; case 'W': - func (stream, "%ld", reg << 2); + func (stream, "%ld", (long) (reg << 2)); value_in_comment = reg << 2; break; @@ -3523,13 +10687,19 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) break; case 'x': - func (stream, "0x%04lx", reg); + func (stream, "0x%04lx", (long) reg); break; case 'B': reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - info->print_address_func (reg * 2 + pc + 4, info); + bfd_vma target = reg * 2 + pc + 4; + info->print_address_func (target, info); value_in_comment = 0; + + /* Fill in instruction information. */ + info->insn_info_valid = 1; + info->insn_type = dis_branch; + info->target = target; break; case 'c': @@ -3573,7 +10743,8 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) } /* No match. */ - abort (); + func (stream, UNKNOWN_INSTRUCTION_16BIT, (unsigned)given); + return; } /* Return the name of an V7M special register. */ @@ -3583,20 +10754,31 @@ psr_name (int regno) { switch (regno) { - case 0: return "APSR"; - case 1: return "IAPSR"; - case 2: return "EAPSR"; - case 3: return "PSR"; - case 5: return "IPSR"; - case 6: return "EPSR"; - case 7: return "IEPSR"; - case 8: return "MSP"; - case 9: return "PSP"; - case 16: return "PRIMASK"; - case 17: return "BASEPRI"; - case 18: return "BASEPRI_MASK"; - case 19: return "FAULTMASK"; - case 20: return "CONTROL"; + case 0x0: return "APSR"; + case 0x1: return "IAPSR"; + case 0x2: return "EAPSR"; + case 0x3: return "PSR"; + case 0x5: return "IPSR"; + case 0x6: return "EPSR"; + case 0x7: return "IEPSR"; + case 0x8: return "MSP"; + case 0x9: return "PSP"; + case 0xa: return "MSPLIM"; + case 0xb: return "PSPLIM"; + case 0x10: return "PRIMASK"; + case 0x11: return "BASEPRI"; + case 0x12: return "BASEPRI_MAX"; + case 0x13: return "FAULTMASK"; + case 0x14: return "CONTROL"; + case 0x88: return "MSP_NS"; + case 0x89: return "PSP_NS"; + case 0x8a: return "MSPLIM_NS"; + case 0x8b: return "PSPLIM_NS"; + case 0x90: return "PRIMASK_NS"; + case 0x91: return "BASEPRI_NS"; + case 0x93: return "FAULTMASK_NS"; + case 0x94: return "CONTROL_NS"; + case 0x98: return "SP_NS"; default: return ""; } } @@ -3609,16 +10791,27 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) const struct opcode32 *insn; void *stream = info->stream; fprintf_ftype func = info->fprintf_func; + bfd_boolean is_mve = is_mve_architecture (info); if (print_insn_coprocessor (pc, info, given, TRUE)) return; - if (print_insn_neon (info, given, TRUE)) + if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE)) + return; + + if (is_mve && print_insn_mve (info, given)) + return; + + if (print_insn_cde (info, given, TRUE)) + return; + + if (print_insn_generic_coprocessor (pc, info, given, TRUE)) return; for (insn = thumb32_opcodes; insn->assembler; insn++) if ((given & insn->mask) == insn->value) { + bfd_boolean is_clrm = FALSE; bfd_boolean is_unpredictable = FALSE; signed long value_in_comment = 0; const char *c = insn->assembler; @@ -3689,7 +10882,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = imm; } break; - + case 'J': { unsigned int imm = 0; @@ -3715,6 +10908,28 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'H': + { + unsigned int imm = 0; + + imm |= (given & 0x000f0000u) >> 4; + imm |= (given & 0x00000fffu) >> 0; + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + + case 'V': + { + unsigned int imm = 0; + + imm |= (given & 0x00000fffu); + imm |= (given & 0x000f0000u) >> 4; + func (stream, "#%u", imm); + value_in_comment = imm; + } + break; + case 'S': { unsigned int reg = (given & 0x0000000fu); @@ -3760,7 +10975,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) unsigned int i12 = (given & 0x00000fff); unsigned int i8 = (given & 0x000000ff); bfd_boolean writeback = FALSE, postind = FALSE; - int offset = 0; + bfd_vma offset = 0; func (stream, "[%s", arm_regnames[Rn]); if (U) /* 12-bit positive immediate offset. */ @@ -3818,11 +11033,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } if (postind) - func (stream, "], #%d", offset); + func (stream, "], #%d", (int) offset); else { if (offset) - func (stream, ", #%d", offset); + func (stream, ", #%d", (int) offset); func (stream, writeback ? "]!" : "]"); } @@ -3849,7 +11064,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) if (off || !U) { func (stream, ", #%c%u", U ? '+' : '-', off * 4); - value_in_comment = off * 4 * U ? 1 : -1; + value_in_comment = off * 4 * (U ? 1 : -1); } func (stream, "]"); if (W) @@ -3861,7 +11076,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) if (W) { func (stream, "#%c%u", U ? '+' : '-', off * 4); - value_in_comment = off * 4 * U ? 1 : -1; + value_in_comment = off * 4 * (U ? 1 : -1); } else { @@ -3892,6 +11107,9 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'n': + is_clrm = TRUE; + /* Fall through. */ case 'm': { int started = 0; @@ -3904,7 +11122,12 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) if (started) func (stream, ", "); started = 1; - func (stream, "%s", arm_regnames[reg]); + if (is_clrm && reg == 13) + func (stream, "(invalid: %s)", arm_regnames[reg]); + else if (is_clrm && reg == 15) + func (stream, "%s", "APSR"); + else + func (stream, "%s", arm_regnames[reg]); } func (stream, "}"); } @@ -3932,12 +11155,102 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'G': + { + unsigned int boff = (((given & 0x07800000) >> 23) << 1); + func (stream, "%x", boff); + } + break; + + case 'W': + { + unsigned int immA = (given & 0x001f0000u) >> 16; + unsigned int immB = (given & 0x000007feu) >> 1; + unsigned int immC = (given & 0x00000800u) >> 11; + bfd_vma offset = 0; + + offset |= immA << 12; + offset |= immB << 2; + offset |= immC << 1; + /* Sign extend. */ + offset = (offset & 0x10000) ? offset - (1 << 17) : offset; + + info->print_address_func (pc + 4 + offset, info); + } + break; + + case 'Y': + { + unsigned int immA = (given & 0x007f0000u) >> 16; + unsigned int immB = (given & 0x000007feu) >> 1; + unsigned int immC = (given & 0x00000800u) >> 11; + bfd_vma offset = 0; + + offset |= immA << 12; + offset |= immB << 2; + offset |= immC << 1; + /* Sign extend. */ + offset = (offset & 0x40000) ? offset - (1 << 19) : offset; + + info->print_address_func (pc + 4 + offset, info); + } + break; + + case 'Z': + { + unsigned int immA = (given & 0x00010000u) >> 16; + unsigned int immB = (given & 0x000007feu) >> 1; + unsigned int immC = (given & 0x00000800u) >> 11; + bfd_vma offset = 0; + + offset |= immA << 12; + offset |= immB << 2; + offset |= immC << 1; + /* Sign extend. */ + offset = (offset & 0x1000) ? offset - (1 << 13) : offset; + + info->print_address_func (pc + 4 + offset, info); + + unsigned int T = (given & 0x00020000u) >> 17; + unsigned int endoffset = (((given & 0x07800000) >> 23) << 1); + unsigned int boffset = (T == 1) ? 4 : 2; + func (stream, ", "); + func (stream, "%x", endoffset + boffset); + } + break; + + case 'Q': + { + unsigned int immh = (given & 0x000007feu) >> 1; + unsigned int imml = (given & 0x00000800u) >> 11; + bfd_vma imm32 = 0; + + imm32 |= immh << 2; + imm32 |= imml << 1; + + info->print_address_func (pc + 4 + imm32, info); + } + break; + + case 'P': + { + unsigned int immh = (given & 0x000007feu) >> 1; + unsigned int imml = (given & 0x00000800u) >> 11; + bfd_vma imm32 = 0; + + imm32 |= immh << 2; + imm32 |= imml << 1; + + info->print_address_func (pc + 4 - imm32, info); + } + break; + case 'b': { unsigned int S = (given & 0x04000000u) >> 26; unsigned int J1 = (given & 0x00002000u) >> 13; unsigned int J2 = (given & 0x00000800u) >> 11; - int offset = 0; + bfd_vma offset = 0; offset |= !S << 20; offset |= J2 << 19; @@ -3946,7 +11259,13 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) offset |= (given & 0x000007ff) << 1; offset -= (1 << 20); - info->print_address_func (pc + 4 + offset, info); + bfd_vma target = pc + 4 + offset; + info->print_address_func (target, info); + + /* Fill in instruction information. */ + info->insn_info_valid = 1; + info->insn_type = dis_branch; + info->target = target; } break; @@ -3955,7 +11274,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) unsigned int S = (given & 0x04000000u) >> 26; unsigned int I1 = (given & 0x00002000u) >> 13; unsigned int I2 = (given & 0x00000800u) >> 11; - int offset = 0; + bfd_vma offset = 0; offset |= !S << 24; offset |= !(I1 ^ S) << 23; @@ -3970,6 +11289,11 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) offset &= ~2u; info->print_address_func (offset, info); + + /* Fill in instruction information. */ + info->insn_info_valid = 1; + info->insn_type = dis_branch; + info->target = offset; } break; @@ -3997,16 +11321,24 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) break; case 'U': - switch (given & 0xf) + if ((given & 0xf0) == 0x60) { - case 0xf: func (stream, "sy"); break; - case 0x7: func (stream, "un"); break; - case 0xe: func (stream, "st"); break; - case 0x6: func (stream, "unst"); break; - default: - func (stream, "#%d", (int) given & 0xf); - break; + switch (given & 0xf) + { + case 0xf: func (stream, "sy"); break; + default: + func (stream, "#%d", (int) given & 0xf); + break; + } } + else + { + const char * opt = data_barrier_option (given & 0xf); + if (opt != NULL) + func (stream, "%s", opt); + else + func (stream, "#%d", (int) given & 0xf); + } break; case 'C': @@ -4022,17 +11354,44 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) if (given & 0x100) func (stream, "c"); } + else if ((given & 0x20) == 0x20) + { + char const* name; + unsigned sysm = (given & 0xf00) >> 8; + + sysm |= (given & 0x30); + sysm |= (given & 0x00100000) >> 14; + name = banked_regname (sysm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sysm); + } else { - func (stream, psr_name (given & 0xff)); + func (stream, "%s", psr_name (given & 0xff)); } break; case 'D': - if ((given & 0xff) == 0) - func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C'); + if (((given & 0xff) == 0) + || ((given & 0x20) == 0x20)) + { + char const* name; + unsigned sm = (given & 0xf0000) >> 16; + + sm |= (given & 0x30); + sm |= (given & 0x00100000) >> 14; + name = banked_regname (sm); + + if (name != NULL) + func (stream, "%s", name); + else + func (stream, "(UNDEF: %lu)", (unsigned long) sm); + } else - func (stream, psr_name (given & 0xff)); + func (stream, "%s", psr_name (given & 0xff)); break; case '0': case '1': case '2': case '3': case '4': @@ -4042,19 +11401,35 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) unsigned long val; c = arm_decode_bitfield (c, given, &val, &width); - + switch (*c) { + case 's': + if (val <= 3) + func (stream, "%s", mve_vec_sizename[val]); + else + func (stream, ""); + break; + case 'd': func (stream, "%lu", val); value_in_comment = val; break; + case 'D': + func (stream, "%lu", val + 1); + value_in_comment = val + 1; + break; + case 'W': func (stream, "%lu", val * 4); value_in_comment = val * 4; break; + case 'S': + if (val == 13) + is_unpredictable = TRUE; + /* Fall through. */ case 'R': if (val == 15) is_unpredictable = TRUE; @@ -4072,7 +11447,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) if (val == ((1ul << width) - 1)) func (stream, "%c", *c); break; - + case '`': c++; if (val == 0) @@ -4083,7 +11458,7 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "%c", c[(1 << width) - (int) val]); c += 1 << width; break; - + case 'x': func (stream, "0x%lx", val & 0xffffffffUL); break; @@ -4094,6 +11469,21 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } break; + case 'L': + /* PR binutils/12534 + If we have a PC relative offset in an LDRD or STRD + instructions then display the decoded address. */ + if (((given >> 16) & 0xf) == 0xf) + { + bfd_vma offset = (given & 0xff) * 4; + + if ((given & (1 << 23)) == 0) + offset = - offset; + func (stream, "\t; "); + info->print_address_func ((pc & ~3) + 4 + offset, info); + } + break; + default: abort (); } @@ -4109,7 +11499,8 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) } /* No match. */ - abort (); + func (stream, UNKNOWN_INSTRUCTION_32BIT, (unsigned)given); + return; } /* Print data bytes on INFO->STREAM. */ @@ -4136,79 +11527,94 @@ print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, } /* Disallow mapping symbols ($a, $b, $d, $t etc) from - being displayed in symbol relative addresses. */ + being displayed in symbol relative addresses. + + Also disallow private symbol, with __tagsym$$ prefix, + from ARM RVCT toolchain being displayed. */ bfd_boolean arm_symbol_is_valid (asymbol * sym, struct disassemble_info * info ATTRIBUTE_UNUSED) { const char * name; - + if (sym == NULL) return FALSE; name = bfd_asymbol_name (sym); - return (name && *name != '$'); + return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); } -/* Parse an individual disassembler option. */ +/* Parse the string of disassembler options. */ -void -parse_arm_disassembler_option (char *option) +static void +parse_arm_disassembler_options (const char *options) { - if (option == NULL) - return; + const char *opt; - if (CONST_STRNEQ (option, "reg-names-")) + FOR_EACH_DISASSEMBLER_OPTION (opt, options) { - int i; - - option += 10; - - for (i = NUM_ARM_REGNAMES; i--;) - if (strneq (option, regnames[i].name, strlen (regnames[i].name))) - { - regname_selected = i; - break; - } + if (CONST_STRNEQ (opt, "reg-names-")) + { + unsigned int i; + for (i = 0; i < NUM_ARM_OPTIONS; i++) + if (disassembler_options_cmp (opt, regnames[i].name) == 0) + { + regname_selected = i; + break; + } - if (i < 0) - /* XXX - should break 'option' at following delimiter. */ - fprintf (stderr, _("Unrecognised register name set: %s\n"), option); + if (i >= NUM_ARM_OPTIONS) + /* xgettext: c-format */ + opcodes_error_handler (_("unrecognised register name set: %s"), + opt); + } + else if (CONST_STRNEQ (opt, "force-thumb")) + force_thumb = 1; + else if (CONST_STRNEQ (opt, "no-force-thumb")) + force_thumb = 0; + else if (CONST_STRNEQ (opt, "coproc")) + { + const char *procptr = opt + sizeof ("coproc") - 1; + char *endptr; + uint8_t coproc_number = strtol (procptr, &endptr, 10); + if (endptr != procptr + 1 || coproc_number > 7) + { + opcodes_error_handler (_("cde coprocessor not between 0-7: %s"), + opt); + continue; + } + if (*endptr != '=') + { + opcodes_error_handler (_("coproc must have an argument: %s"), + opt); + continue; + } + endptr += 1; + if (CONST_STRNEQ (endptr, "generic")) + cde_coprocs &= ~(1 << coproc_number); + else if (CONST_STRNEQ (endptr, "cde") + || CONST_STRNEQ (endptr, "CDE")) + cde_coprocs |= (1 << coproc_number); + else + { + opcodes_error_handler ( + _("coprocN argument takes options \"generic\"," + " \"cde\", or \"CDE\": %s"), opt); + } + } + else + /* xgettext: c-format */ + opcodes_error_handler (_("unrecognised disassembler option: %s"), opt); } - else if (CONST_STRNEQ (option, "force-thumb")) - force_thumb = 1; - else if (CONST_STRNEQ (option, "no-force-thumb")) - force_thumb = 0; - else - /* XXX - should break 'option' at following delimiter. */ - fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); return; } -/* Parse the string of disassembler options, spliting it at whitespaces - or commas. (Whitespace separators supported for backwards compatibility). */ - -static void -parse_disassembler_options (char *options) -{ - if (options == NULL) - return; - - while (*options) - { - parse_arm_disassembler_option (options); - - /* Skip forward to next seperator. */ - while ((*options) && (! ISSPACE (*options)) && (*options != ',')) - ++ options; - /* Skip forward past seperators. */ - while (ISSPACE (*options) || (*options == ',')) - ++ options; - } -} +static bfd_boolean +mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, + enum map_type *map_symbol); /* Search back through the insn stream to determine if this instruction is conditionally executed. */ @@ -4272,9 +11678,15 @@ find_ifthen_state (bfd_vma pc, } if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) { - /* This could be an IT instruction. */ - seen_it = insn; - it_count = count >> 1; + enum map_type type = MAP_ARM; + bfd_boolean found = mapping_symbol_for_insn (addr, info, &type); + + if (!found || (found && type == MAP_THUMB)) + { + /* This could be an IT instruction. */ + seen_it = insn; + it_count = count >> 1; + } } if ((insn & 0xf800) >= 0xe800) count++; @@ -4346,18 +11758,149 @@ get_sym_code_type (struct disassemble_info *info, type = ELF_ST_TYPE (es->internal_elf_sym.st_info); /* If the symbol has function type then use that. */ - if (type == STT_FUNC || type == STT_ARM_TFUNC) + if (type == STT_FUNC || type == STT_GNU_IFUNC) { - *map_type = (type == STT_ARM_TFUNC) ? MAP_THUMB : MAP_ARM; + if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) + == ST_BRANCH_TO_THUMB) + *map_type = MAP_THUMB; + else + *map_type = MAP_ARM; return TRUE; } return FALSE; } +/* Search the mapping symbol state for instruction at pc. This is only + applicable for elf target. + + There is an assumption Here, info->private_data contains the correct AND + up-to-date information about current scan process. The information will be + used to speed this search process. + + Return TRUE if the mapping state can be determined, and map_symbol + will be updated accordingly. Otherwise, return FALSE. */ + +static bfd_boolean +mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, + enum map_type *map_symbol) +{ + bfd_vma addr, section_vma = 0; + int n, last_sym = -1; + bfd_boolean found = FALSE; + bfd_boolean can_use_search_opt_p = FALSE; + + /* Default to DATA. A text section is required by the ABI to contain an + INSN mapping symbol at the start. A data section has no such + requirement, hence if no mapping symbol is found the section must + contain only data. This however isn't very useful if the user has + fully stripped the binaries. If this is the case use the section + attributes to determine the default. If we have no section default to + INSN as well, as we may be disassembling some raw bytes on a baremetal + HEX file or similar. */ + enum map_type type = MAP_DATA; + if ((info->section && info->section->flags & SEC_CODE) || !info->section) + type = MAP_ARM; + struct arm_private_data *private_data; + + if (info->private_data == NULL + || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) + return FALSE; + + private_data = info->private_data; + + /* First, look for mapping symbols. */ + if (info->symtab_size != 0) + { + if (pc <= private_data->last_mapping_addr) + private_data->last_mapping_sym = -1; + + /* Start scanning at the start of the function, or wherever + we finished last time. */ + n = info->symtab_pos + 1; + + /* If the last stop offset is different from the current one it means we + are disassembling a different glob of bytes. As such the optimization + would not be safe and we should start over. */ + can_use_search_opt_p + = private_data->last_mapping_sym >= 0 + && info->stop_offset == private_data->last_stop_offset; + + if (n >= private_data->last_mapping_sym && can_use_search_opt_p) + n = private_data->last_mapping_sym; + + /* Look down while we haven't passed the location being disassembled. + The reason for this is that there's no defined order between a symbol + and an mapping symbol that may be at the same address. We may have to + look at least one position ahead. */ + for (; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > pc) + break; + if (get_map_sym_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + } + } + + if (!found) + { + n = info->symtab_pos; + if (n >= private_data->last_mapping_sym && can_use_search_opt_p) + n = private_data->last_mapping_sym; + + /* No mapping symbol found at this address. Look backwards + for a preceeding one, but don't go pass the section start + otherwise a data section with no mapping symbol can pick up + a text mapping symbol of a preceeding section. The documentation + says section can be NULL, in which case we will seek up all the + way to the top. */ + if (info->section) + section_vma = info->section->vma; + + for (; n >= 0; n--) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr < section_vma) + break; + + if (get_map_sym_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + break; + } + } + } + } + + /* If no mapping symbol was found, try looking up without a mapping + symbol. This is done by walking up from the current PC to the nearest + symbol. We don't actually have to loop here since symtab_pos will + contain the nearest symbol already. */ + if (!found) + { + n = info->symtab_pos; + if (n >= 0 && get_sym_code_type (info, n, &type)) + { + last_sym = n; + found = TRUE; + } + } + + private_data->last_mapping_sym = last_sym; + private_data->last_type = type; + private_data->last_stop_offset = info->stop_offset; + + *map_symbol = type; + return found; +} + /* Given a bfd_mach_arm_XXX value, this function fills in the fields of the supplied arm_feature_set structure with bitmasks indicating - the support base architectures and coprocessor extensions. + the supported base architectures and coprocessor extensions. FIXME: This could more efficiently implemented as a constant array, although it would also be less robust. */ @@ -4366,33 +11909,80 @@ static void select_arm_features (unsigned long mach, arm_feature_set * features) { -#undef ARM_FEATURE -#define ARM_FEATURE(ARCH,CEXT) \ - features->core = (ARCH); \ - features->coproc = (CEXT) | FPU_FPA; \ - return - + arm_feature_set arch_fset; + const arm_feature_set fpu_any = FPU_ANY; + +#undef ARM_SET_FEATURES +#define ARM_SET_FEATURES(FSET) \ + { \ + const arm_feature_set fset = FSET; \ + arch_fset = fset; \ + } + + /* When several architecture versions share the same bfd_mach_arm_XXX value + the most featureful is chosen. */ switch (mach) { - case bfd_mach_arm_2: ARM_ARCH_V2; - case bfd_mach_arm_2a: ARM_ARCH_V2S; - case bfd_mach_arm_3: ARM_ARCH_V3; - case bfd_mach_arm_3M: ARM_ARCH_V3M; - case bfd_mach_arm_4: ARM_ARCH_V4; - case bfd_mach_arm_4T: ARM_ARCH_V4T; - case bfd_mach_arm_5: ARM_ARCH_V5; - case bfd_mach_arm_5T: ARM_ARCH_V5T; - case bfd_mach_arm_5TE: ARM_ARCH_V5TE; - case bfd_mach_arm_XScale: ARM_ARCH_XSCALE; - case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK); - case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT; - case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2; - /* If the machine type is unknown allow all - architecture types and all extensions. */ - case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL); + case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; + case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; + case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; + case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; + case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; + case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; + case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; + case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; + case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; + case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; + case bfd_mach_arm_ep9312: + ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, + ARM_CEXT_MAVERICK | FPU_MAVERICK)); + break; + case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; + case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; + case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; + case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break; + case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break; + case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break; + case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break; + case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break; + case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break; + case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break; + case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break; + case bfd_mach_arm_8: + { + /* Add bits for extensions that Armv8.6-A recognizes. */ + arm_feature_set armv8_6_ext_fset + = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST); + ARM_SET_FEATURES (ARM_ARCH_V8_6A); + ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_6_ext_fset); + break; + } + case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break; + case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break; + case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break; + case bfd_mach_arm_8_1M_MAIN: + ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); + arm_feature_set mve_all + = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP); + ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, mve_all); + force_thumb = 1; + break; + /* If the machine type is unknown allow all architecture types and all + extensions, with the exception of MVE as that clashes with NEON. */ + case bfd_mach_arm_unknown: + ARM_SET_FEATURES (ARM_FEATURE (-1, + -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), + -1)); + break; default: abort (); } +#undef ARM_SET_FEATURES + + /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch + and thus on bfd_mach_arm_XXX value. Therefore for a given + bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */ + ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any); } @@ -4403,7 +11993,7 @@ static int print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) { unsigned char b[4]; - long given; + unsigned long given; int status; int is_thumb = FALSE; int is_data = FALSE; @@ -4413,9 +12003,17 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) bfd_boolean found = FALSE; struct arm_private_data *private_data; + /* Clear instruction information field. */ + info->insn_info_valid = 0; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_noninsn; + info->target = 0; + info->target2 = 0; + if (info->disassembler_options) { - parse_disassembler_options (info->disassembler_options); + parse_arm_disassembler_options (info->disassembler_options); /* To avoid repeated parsing of these options, we remove them here. */ info->disassembler_options = NULL; @@ -4429,7 +12027,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) /* If the user did not use the -m command line switch then default to disassembling all types of ARM instruction. - + The info->mach value has to be ignored as this will be based on the default archictecture for the target and/or hints in the notes section, but it will never be greater than the current largest arm @@ -4452,7 +12050,9 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) during disassembly.... */ select_arm_features (info->mach, & private.features); - private.has_mapping_symbols = -1; + private.last_mapping_sym = -1; + private.last_mapping_addr = 0; + private.last_stop_offset = 0; info->private_data = & private; } @@ -4469,113 +12069,15 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) { bfd_vma addr; - int n, start; + int n; int last_sym = -1; enum map_type type = MAP_ARM; - /* Start scanning at the start of the function, or wherever - we finished last time. */ - start = info->symtab_pos + 1; - if (start < last_mapping_sym) - start = last_mapping_sym; - found = FALSE; + found = mapping_symbol_for_insn (pc, info, &type); + last_sym = private_data->last_mapping_sym; - /* First, look for mapping symbols. */ - if (private_data->has_mapping_symbols != 0) - { - /* Scan up to the location being disassembled. */ - for (n = start; n < info->symtab_size; n++) - { - addr = bfd_asymbol_value (info->symtab[n]); - if (addr > pc) - break; - if (get_map_sym_type (info, n, &type)) - { - last_sym = n; - found = TRUE; - } - } - - if (!found) - { - /* No mapping symbol found at this address. Look backwards - for a preceeding one. */ - for (n = start - 1; n >= 0; n--) - { - if (get_map_sym_type (info, n, &type)) - { - last_sym = n; - found = TRUE; - break; - } - } - } - - if (found) - private_data->has_mapping_symbols = 1; - - /* No mapping symbols were found. A leading $d may be - omitted for sections which start with data; but for - compatibility with legacy and stripped binaries, only - assume the leading $d if there is at least one mapping - symbol in the file. */ - if (!found && private_data->has_mapping_symbols == -1) - { - /* Look for mapping symbols, in any section. */ - for (n = 0; n < info->symtab_size; n++) - if (is_mapping_symbol (info, n, &type)) - { - private_data->has_mapping_symbols = 1; - break; - } - if (private_data->has_mapping_symbols == -1) - private_data->has_mapping_symbols = 0; - } - - if (!found && private_data->has_mapping_symbols == 1) - { - type = MAP_DATA; - found = TRUE; - } - } - - /* Next search for function symbols to separate ARM from Thumb - in binaries without mapping symbols. */ - if (!found) - { - /* Scan up to the location being disassembled. */ - for (n = start; n < info->symtab_size; n++) - { - addr = bfd_asymbol_value (info->symtab[n]); - if (addr > pc) - break; - if (get_sym_code_type (info, n, &type)) - { - last_sym = n; - found = TRUE; - } - } - - if (!found) - { - /* No mapping symbol found at this address. Look backwards - for a preceeding one. */ - for (n = start - 1; n >= 0; n--) - { - if (get_sym_code_type (info, n, &type)) - { - last_sym = n; - found = TRUE; - break; - } - } - } - } - - last_mapping_sym = last_sym; - last_type = type; - is_thumb = (last_type == MAP_THUMB); - is_data = (last_type == MAP_DATA); + is_thumb = (private_data->last_type == MAP_THUMB); + is_data = (private_data->last_type == MAP_DATA); /* Look a little bit ahead to see if we should print out two or four bytes of data. If there's a symbol, @@ -4628,7 +12130,16 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) es = *(elf_symbol_type **)(info->symbols); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); - is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); + is_thumb = + ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) + == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); + } + else if (bfd_asymbol_flavour (*info->symbols) + == bfd_target_mach_o_flavour) + { + bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; + + is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); } } @@ -4670,9 +12181,9 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); if (little_code) - given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24); else - given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); + given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24); } else { @@ -4763,21 +12274,57 @@ print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) return print_insn (pc, info, TRUE); } +const disasm_options_and_args_t * +disassembler_options_arm (void) +{ + static disasm_options_and_args_t *opts_and_args; + + if (opts_and_args == NULL) + { + disasm_options_t *opts; + unsigned int i; + + opts_and_args = XNEW (disasm_options_and_args_t); + opts_and_args->args = NULL; + + opts = &opts_and_args->options; + opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); + opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); + opts->arg = NULL; + for (i = 0; i < NUM_ARM_OPTIONS; i++) + { + opts->name[i] = regnames[i].name; + if (regnames[i].description != NULL) + opts->description[i] = _(regnames[i].description); + else + opts->description[i] = NULL; + } + /* The array we return must be NULL terminated. */ + opts->name[i] = NULL; + opts->description[i] = NULL; + } + + return opts_and_args; +} + void print_arm_disassembler_options (FILE *stream) { - int i; - + unsigned int i, max_len = 0; fprintf (stream, _("\n\ The following ARM specific disassembler options are supported for use with\n\ the -M switch:\n")); - for (i = NUM_ARM_REGNAMES; i--;) - fprintf (stream, " reg-names-%s %*c%s\n", - regnames[i].name, - (int)(14 - strlen (regnames[i].name)), ' ', - regnames[i].description); + for (i = 0; i < NUM_ARM_OPTIONS; i++) + { + unsigned int len = strlen (regnames[i].name); + if (max_len < len) + max_len = len; + } - fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); - fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); + for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) + fprintf (stream, " %s%*c %s\n", + regnames[i].name, + (int)(max_len - strlen (regnames[i].name)), ' ', + _(regnames[i].description)); }