X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fcrx-dis.c;h=38347486169f107d74ffab7db86ed3dc176b9ce6;hb=660df28acfa1b58c978d65d9cb26d37023f791ce;hp=9c14537f0db17d0ebd6076e910b933ce06cbd0e5;hpb=2571583aed598dd3f9651b53434e5f177a0e3cf7;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/crx-dis.c b/opcodes/crx-dis.c
index 9c14537f0d..3834748616 100644
--- a/opcodes/crx-dis.c
+++ b/opcodes/crx-dis.c
@@ -1,5 +1,5 @@
 /* Disassembler code for CRX.
-   Copyright (C) 2004-2017 Free Software Foundation, Inc.
+   Copyright (C) 2004-2019 Free Software Foundation, Inc.
    Contributed by Tomer Levi, NSC, Israel.
    Written by Tomer Levi.
 
@@ -21,7 +21,7 @@
    MA 02110-1301, USA.  */
 
 #include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
 #include "opcode/crx.h"
 
 /* String to print when opcode was not matched.  */
@@ -31,11 +31,10 @@
 
 /* Extract 'n_bits' from 'a' starting from offset 'offs'.  */
 #define EXTRACT(a, offs, n_bits)	    \
-  (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL)   \
-  : (((a) >> (offs)) & ((1 << (n_bits)) -1)))
+  (((a) >> (offs)) & ((2ull << (n_bits - 1)) - 1))
 
 /* Set Bit Mask - a mask to set all bits starting from offset 'offs'.  */
-#define SBM(offs)  ((((1 << (32 - offs)) -1) << (offs)))
+#define SBM(offs)  ((-1u << (offs)) & 0xffffffff)
 
 typedef unsigned long dwordU;
 typedef unsigned short wordU;
@@ -58,7 +57,7 @@ typedef struct
 cinv_entry;
 
 /* CRX 'cinv' options.  */
-const cinv_entry crx_cinvs[] =
+static const cinv_entry crx_cinvs[] =
 {
   {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
   {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
@@ -81,40 +80,23 @@ typedef enum REG_ARG_TYPE
 REG_ARG_TYPE;
 
 /* Number of valid 'cinv' instruction options.  */
-int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0]));
+static int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0]));
 /* Current opcode table entry we're disassembling.  */
-const inst *instruction;
+static const inst *instruction;
 /* Current instruction we're disassembling.  */
-ins currInsn;
+static ins currInsn;
 /* The current instruction is read into 3 consecutive words.  */
-wordU words[3];
+static wordU words[3];
 /* Contains all words in appropriate order.  */
-ULONGLONG allWords;
+static ULONGLONG allWords;
 /* Holds the current processed argument number.  */
-int processing_argument_number;
+static int processing_argument_number;
 /* Nonzero means a CST4 instruction.  */
-int cst4flag;
+static int cst4flag;
 /* Nonzero means the instruction's original size is
    incremented (escape sequence is used).  */
-int size_changed;
-
-static int get_number_of_operands (void);
-static argtype getargtype     (operand_type);
-static int getbits	      (operand_type);
-static char *getregname	      (reg);
-static char *getcopregname    (copreg, reg_type);
-static char * getprocregname  (int);
-static char *gettrapstring    (unsigned);
-static char *getcinvstring    (unsigned);
-static void getregliststring  (int, char *, enum REG_ARG_TYPE);
-static wordU get_word_at_PC   (bfd_vma, struct disassemble_info *);
-static void get_words_at_PC   (bfd_vma, struct disassemble_info *);
-static unsigned long build_mask (void);
-static int powerof2	      (int);
-static int match_opcode	      (void);
-static void make_instruction  (void);
-static void print_arguments   (ins *, bfd_vma, struct disassemble_info *);
-static void print_arg	      (argument *, bfd_vma, struct disassemble_info *);
+static int size_changed;
+
 
 /* Retrieve the number of operands for the current assembled instruction.  */
 
@@ -183,7 +165,7 @@ getcinvstring (unsigned int num)
 
 /* Given a register enum value, retrieve its name.  */
 
-char *
+static char *
 getregname (reg r)
 {
   const reg_entry * regentry = &crx_regtab[r];
@@ -196,7 +178,7 @@ getregname (reg r)
 
 /* Given a coprocessor register enum value, retrieve its name.  */
 
-char *
+static char *
 getcopregname (copreg r, reg_type type)
 {
   const reg_entry * regentry;
@@ -241,10 +223,10 @@ powerof2 (int x)
 
 /* Transform a register bit mask to a register list.  */
 
-void
+static void
 getregliststring (int mask, char *string, enum REG_ARG_TYPE core_cop)
 {
-  char temp_string[5];
+  char temp_string[16];
   int i;
 
   string[0] = '{';
@@ -315,11 +297,11 @@ makelongparameter (ULONGLONG val, int start, int end)
 /* Build a mask of the instruction's 'constant' opcode,
    based on the instruction's printing flags.  */
 
-static unsigned long
+static unsigned int
 build_mask (void)
 {
   unsigned int print_flags;
-  unsigned long mask;
+  unsigned int mask;
 
   print_flags = instruction->flags & FMT_CRX;
   switch (print_flags)
@@ -352,10 +334,10 @@ build_mask (void)
 static int
 match_opcode (void)
 {
-  unsigned long mask;
+  unsigned int mask;
 
   /* The instruction 'constant' opcode doewsn't exceed 32 bits.  */
-  unsigned long doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff;
+  unsigned int doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff;
 
   /* Start searching from end of instruction table.  */
   instruction = &crx_instruction[NUMOPCODES - 2];