X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fcrx-dis.c;h=4abc7d2e7d220b75f2926d662c9a196500b4efa9;hb=d3ecddab5fc036fb57588a9bfff73575dc419052;hp=b2cf31210f62ef506ab512d447d423490fdff142;hpb=48c9f030c98a3b53b9cb962857ffc16c435a63db;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/crx-dis.c b/opcodes/crx-dis.c index b2cf31210f..4abc7d2e7d 100644 --- a/opcodes/crx-dis.c +++ b/opcodes/crx-dis.c @@ -1,26 +1,27 @@ /* Disassembler code for CRX. - Copyright 2004 Free Software Foundation, Inc. + Copyright (C) 2004-2019 Free Software Foundation, Inc. Contributed by Tomer Levi, NSC, Israel. Written by Tomer Levi. - This file is part of the GNU binutils and GDB, the GNU debugger. + This file is part of the GNU opcodes library. - This program is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License as published by the Free - Software Foundation; either version 2, or (at your option) + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) any later version. - This program is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ -#include "dis-asm.h" #include "sysdep.h" +#include "disassemble.h" #include "opcode/crx.h" /* String to print when opcode was not matched. */ @@ -30,7 +31,7 @@ /* Extract 'n_bits' from 'a' starting from offset 'offs'. */ #define EXTRACT(a, offs, n_bits) \ - (n_bits == 32 ? (((a) >> (offs)) & ~0L) \ + (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL) \ : (((a) >> (offs)) & ((1 << (n_bits)) -1))) /* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */ @@ -57,44 +58,45 @@ typedef struct cinv_entry; /* CRX 'cinv' options. */ -const cinv_entry crx_cinvs[] = +static const cinv_entry crx_cinvs[] = { - {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5}, - {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8}, - {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12}, + {"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5}, + {"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8}, + {"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12}, {"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15} }; -/* Enum to distinguish CO-Processor [special] registers arguments - from general purpose regidters. */ -typedef enum COP_ARG_TYPE +/* Enum to distinguish different registers argument types. */ +typedef enum REG_ARG_TYPE { - /* Not a CO-Processor argument (probably a general purpose reg.). */ - NO_COP_ARG = 0, - /* A CO-Processor argument (c). */ + /* General purpose register (r). */ + REG_ARG = 0, + /* User register (u). */ + USER_REG_ARG, + /* CO-Processor register (c). */ COP_ARG, - /* A CO-Processor special argument (cs). */ - COPS_ARG + /* CO-Processor special register (cs). */ + COPS_ARG } -COP_ARG_TYPE; +REG_ARG_TYPE; /* Number of valid 'cinv' instruction options. */ -int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0])); +static int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0])); /* Current opcode table entry we're disassembling. */ -const inst *instruction; +static const inst *instruction; /* Current instruction we're disassembling. */ -ins currInsn; +static ins currInsn; /* The current instruction is read into 3 consecutive words. */ -wordU words[3]; +static wordU words[3]; /* Contains all words in appropriate order. */ -ULONGLONG allWords; +static ULONGLONG allWords; /* Holds the current processed argument number. */ -int processing_argument_number; +static int processing_argument_number; /* Nonzero means a CST4 instruction. */ -int cst4flag; +static int cst4flag; /* Nonzero means the instruction's original size is incremented (escape sequence is used). */ -int size_changed; +static int size_changed; static int get_number_of_operands (void); static argtype getargtype (operand_type); @@ -104,15 +106,15 @@ static char *getcopregname (copreg, reg_type); static char * getprocregname (int); static char *gettrapstring (unsigned); static char *getcinvstring (unsigned); -static void getregliststring (int, char *, enum COP_ARG_TYPE); +static void getregliststring (int, char *, enum REG_ARG_TYPE); static wordU get_word_at_PC (bfd_vma, struct disassemble_info *); static void get_words_at_PC (bfd_vma, struct disassemble_info *); static unsigned long build_mask (void); static int powerof2 (int); static int match_opcode (void); static void make_instruction (void); -static void print_arguments (ins *, struct disassemble_info *); -static void print_arg (argument *, struct disassemble_info *); +static void print_arguments (ins *, bfd_vma, struct disassemble_info *); +static void print_arg (argument *, bfd_vma, struct disassemble_info *); /* Retrieve the number of operands for the current assembled instruction. */ @@ -153,12 +155,12 @@ getargtype (operand_type op) This routine is used when disassembling the 'excp' instruction. */ static char * -gettrapstring (unsigned int index) +gettrapstring (unsigned int trap_index) { const trap_entry *trap; for (trap = crx_traps; trap < crx_traps + NUMTRAPS; trap++) - if (trap->entry == index) + if (trap->entry == trap_index) return trap->name; return ILLEGAL; @@ -184,12 +186,12 @@ getcinvstring (unsigned int num) char * getregname (reg r) { - const reg_entry *reg = &crx_regtab[r]; + const reg_entry * regentry = &crx_regtab[r]; - if (reg->type != CRX_R_REGTYPE) + if (regentry->type != CRX_R_REGTYPE) return ILLEGAL; else - return reg->name; + return regentry->name; } /* Given a coprocessor register enum value, retrieve its name. */ @@ -197,28 +199,28 @@ getregname (reg r) char * getcopregname (copreg r, reg_type type) { - const reg_entry *reg; + const reg_entry * regentry; if (type == CRX_C_REGTYPE) - reg = &crx_copregtab[r]; + regentry = &crx_copregtab[r]; else if (type == CRX_CS_REGTYPE) - reg = &crx_copregtab[r+(cs0-c0)]; + regentry = &crx_copregtab[r+(cs0-c0)]; else return ILLEGAL; - return reg->name; + return regentry->name; } /* Getting a processor register name. */ static char * -getprocregname (int index) +getprocregname (int reg_index) { const reg_entry *r; for (r = crx_regtab; r < crx_regtab + NUMREGS; r++) - if (r->image == index) + if (r->image == reg_index) return r->name; return "ILLEGAL REGISTER"; @@ -240,37 +242,52 @@ powerof2 (int x) /* Transform a register bit mask to a register list. */ void -getregliststring (int trap, char *string, enum COP_ARG_TYPE core_cop) +getregliststring (int mask, char *string, enum REG_ARG_TYPE core_cop) { - char temp_string[5]; + char temp_string[16]; int i; string[0] = '{'; string[1] = '\0'; - for (i = 0; i < 16; i++) + + /* A zero mask means HI/LO registers. */ + if (mask == 0) + { + if (core_cop == USER_REG_ARG) + strcat (string, "ulo,uhi"); + else + strcat (string, "lo,hi"); + } + else { - if (trap & 0x1) + for (i = 0; i < 16; i++) { - switch (core_cop) + if (mask & 0x1) { - case NO_COP_ARG: - sprintf (temp_string, "r%d", i); - break; - case COP_ARG: - sprintf (temp_string, "c%d", i); - break; - case COPS_ARG: - sprintf (temp_string, "cs%d", i); - break; - default: - break; + switch (core_cop) + { + case REG_ARG: + sprintf (temp_string, "r%d", i); + break; + case USER_REG_ARG: + sprintf (temp_string, "u%d", i); + break; + case COP_ARG: + sprintf (temp_string, "c%d", i); + break; + case COPS_ARG: + sprintf (temp_string, "cs%d", i); + break; + default: + break; + } + strcat (string, temp_string); + if (mask & 0xfffe) + strcat (string, ","); } - strcat (string, temp_string); - if (trap & 0xfffe) - strcat (string, ","); - } - trap = trap >> 1; + mask >>= 1; + } } strcat (string, "}"); @@ -338,7 +355,7 @@ match_opcode (void) unsigned long mask; /* The instruction 'constant' opcode doewsn't exceed 32 bits. */ - unsigned long doubleWord = words[1] + (words[0] << 16); + unsigned long doubleWord = (words[1] + (words[0] << 16)) & 0xffffffff; /* Start searching from end of instruction table. */ instruction = &crx_instruction[NUMOPCODES - 2]; @@ -415,7 +432,7 @@ make_argument (argument * a, int start_bits) a->constant = p.val; break; - case arg_icr: + case arg_idxr: a->scale = 0; total_size = a->size + 10; /* sizeof(rbase + ridx + scl2) = 10. */ p = makelongparameter (allWords, inst_bit_size - total_size, @@ -480,10 +497,12 @@ make_argument (argument * a, int start_bits) /* Print a single argument. */ static void -print_arg (argument *a, struct disassemble_info *info) +print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info) { LONGLONG longdisp, mask; - char sign_flag; + int sign_flag = 0; + int relative = 0; + bfd_vma number; int op_index = 0; char string[200]; PTR stream = info->stream; @@ -515,34 +534,35 @@ print_arg (argument *a, struct disassemble_info *info) else if (INST_HAS_REG_LIST) { - COP_ARG_TYPE cop_ins = IS_INSN_TYPE (COP_REG_INS) ? - COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ? - COPS_ARG : NO_COP_ARG; + REG_ARG_TYPE reg_arg_type = IS_INSN_TYPE (COP_REG_INS) ? + COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ? + COPS_ARG : (instruction->flags & USER_REG) ? + USER_REG_ARG : REG_ARG; - if (cop_ins != NO_COP_ARG) + if ((reg_arg_type == COP_ARG) || (reg_arg_type == COPS_ARG)) { - /* Check for proper argument number. */ - if (processing_argument_number == 2) - { - getregliststring (a->constant, string, cop_ins); - func (stream, "%s", string); - } - else - func (stream, "$0x%x", a->constant); + /* Check for proper argument number. */ + if (processing_argument_number == 2) + { + getregliststring (a->constant, string, reg_arg_type); + func (stream, "%s", string); + } + else + func (stream, "$0x%lx", a->constant & 0xffffffff); } else { - getregliststring (a->constant, string, cop_ins); + getregliststring (a->constant, string, reg_arg_type); func (stream, "%s", string); } } else - func (stream, "$0x%x", a->constant); + func (stream, "$0x%lx", a->constant & 0xffffffff); break; - case arg_icr: - func (stream, "0x%x(%s,%s,%d)", a->constant, getregname (a->r), - getregname (a->i_r), powerof2 (a->scale)); + case arg_idxr: + func (stream, "0x%lx(%s,%s,%d)", a->constant & 0xffffffff, + getregname (a->r), getregname (a->i_r), powerof2 (a->scale)); break; case arg_rbase: @@ -550,7 +570,7 @@ print_arg (argument *a, struct disassemble_info *info) break; case arg_cr: - func (stream, "0x%x(%s)", a->constant, getregname (a->r)); + func (stream, "0x%lx(%s)", a->constant & 0xffffffff, getregname (a->r)); if (IS_INSN_TYPE (LD_STOR_INS_INC)) func (stream, "+"); @@ -564,10 +584,9 @@ print_arg (argument *a, struct disassemble_info *info) || IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (DCR_BRANCH_INS) || IS_INSN_TYPE (COP_BRANCH_INS)) { - func (stream, "%c", '*'); + relative = 1; longdisp = a->constant; longdisp <<= 1; - sign_flag = '+'; switch (a->size) { @@ -578,7 +597,7 @@ print_arg (argument *a, struct disassemble_info *info) mask = ((LONGLONG)1 << a->size) - 1; if (longdisp & ((LONGLONG)1 << a->size)) { - sign_flag = '-'; + sign_flag = 1; longdisp = ~(longdisp) + 1; } a->constant = (unsigned long int) (longdisp & mask); @@ -589,12 +608,11 @@ print_arg (argument *a, struct disassemble_info *info) break; } - func (stream, "%c", sign_flag); } /* For branch Neq instruction it is 2*offset + 2. */ - if (IS_INSN_TYPE (BRANCH_NEQ_INS)) + else if (IS_INSN_TYPE (BRANCH_NEQ_INS)) a->constant = 2 * a->constant + 2; - if (IS_INSN_TYPE (LD_STOR_INS_INC) + else if (IS_INSN_TYPE (LD_STOR_INS_INC) || IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (CSTBIT_INS)) @@ -603,7 +621,10 @@ print_arg (argument *a, struct disassemble_info *info) if (instruction->operands[op_index].op_type == abs16) a->constant |= 0xFFFF0000; } - func (stream, "0x%x", a->constant); + func (stream, "%s", "0x"); + number = (relative ? memaddr : 0) + + (sign_flag ? -a->constant : a->constant); + (*info->print_address_func) (number, info); break; default: break; @@ -613,17 +634,17 @@ print_arg (argument *a, struct disassemble_info *info) /* Print all the arguments of CURRINSN instruction. */ static void -print_arguments (ins *currInsn, struct disassemble_info *info) +print_arguments (ins *currentInsn, bfd_vma memaddr, struct disassemble_info *info) { int i; - for (i = 0; i < currInsn->nargs; i++) + for (i = 0; i < currentInsn->nargs; i++) { processing_argument_number = i; - print_arg (&currInsn->arg[i], info); + print_arg (¤tInsn->arg[i], memaddr, info); - if (i != currInsn->nargs - 1) + if (i != currentInsn->nargs - 1) info->fprintf_func (info->stream, ", "); } } @@ -634,14 +655,16 @@ static void make_instruction (void) { int i; - unsigned int temp_value, shift; - argument a; + unsigned int shift; for (i = 0; i < currInsn.nargs; i++) { + argument a; + + memset (&a, 0, sizeof (a)); a.type = getargtype (instruction->operands[i].op_type); if (instruction->operands[i].op_type == cst4 - || instruction->operands[i].op_type == rbase_cst4) + || instruction->operands[i].op_type == rbase_dispu4) cst4flag = 1; a.size = getbits (instruction->operands[i].op_type); shift = instruction->operands[i].shift; @@ -652,15 +675,8 @@ make_instruction (void) /* Calculate instruction size (in bytes). */ currInsn.size = instruction->size + (size_changed ? 1 : 0); + /* Now in bits. */ currInsn.size *= 2; - - /* Swapping first and second arguments. */ - if (IS_INSN_TYPE (COP_BRANCH_INS)) - { - temp_value = currInsn.arg[0].constant; - currInsn.arg[0].constant = currInsn.arg[1].constant; - currInsn.arg[1].constant = temp_value; - } } /* Retrieve a single word from a given memory address. */ @@ -698,9 +714,7 @@ get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info) /* Prints the instruction by calling print_arguments after proper matching. */ int -print_insn_crx (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_crx (bfd_vma memaddr, struct disassemble_info *info) { int is_decoded; /* Nonzero means instruction has a match. */ @@ -713,13 +727,13 @@ print_insn_crx (memaddr, info) /* Find a matching opcode in table. */ is_decoded = match_opcode (); /* If found, print the instruction's mnemonic and arguments. */ - if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0) + if (is_decoded > 0 && (words[0] != 0 || words[1] != 0)) { info->fprintf_func (info->stream, "%s", instruction->mnemonic); if ((currInsn.nargs = get_number_of_operands ()) != 0) info->fprintf_func (info->stream, "\t"); make_instruction (); - print_arguments (&currInsn, info); + print_arguments (&currInsn, memaddr, info); return currInsn.size; }