X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fi386-dis.c;h=2a0e765c55a88827d4dce0c626e1df3a705d18ec;hb=4a4c04f1f4a926f986a77e72277c16e1b90c2b73;hp=f453989b70791cf2d315aaa29077b0bcf2269288;hpb=5074ad8a66ab2e955cf3ae4dba5773d5aa67b29b;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index f453989b70..2a0e765c55 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,5 +1,5 @@ /* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988-2018 Free Software Foundation, Inc. + Copyright (C) 1988-2019 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -95,14 +95,12 @@ static void OP_XMM_VexW (int, int); static void OP_Rounding (int, int); static void OP_REG_VexI4 (int, int); static void PCLMUL_Fixup (int, int); -static void VZERO_Fixup (int, int); static void VCMP_Fixup (int, int); static void VPCMP_Fixup (int, int); static void VPCOM_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); -static void OP_Mwaitx (int, int); static void NOP_Fixup1 (int, int); static void NOP_Fixup2 (int, int); static void OP_3DNowSuffix (int, int); @@ -292,8 +290,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ #define Iv { OP_I, v_mode } #define sIv { OP_sI, v_mode } -#define Iq { OP_I, q_mode } #define Iv64 { OP_I64, v_mode } +#define Id { OP_I, d_mode } #define Iw { OP_I, w_mode } #define I1 { OP_I, const_1_mode } #define Jb { OP_J, b_mode } @@ -386,7 +384,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EXd { OP_EX, d_mode } #define EXdScalar { OP_EX, d_scalar_mode } #define EXdS { OP_EX, d_swap_mode } -#define EXdScalarS { OP_EX, d_scalar_swap_mode } #define EXq { OP_EX, q_mode } #define EXqScalar { OP_EX, q_scalar_mode } #define EXqScalarS { OP_EX, q_scalar_swap_mode } @@ -426,27 +423,22 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Vex128 { OP_VEX, vex128_mode } #define Vex256 { OP_VEX, vex256_mode } #define VexGdq { OP_VEX, dq_mode } -#define EXdVex { OP_EX_Vex, d_mode } -#define EXdVexS { OP_EX_Vex, d_swap_mode } #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } -#define EXqVex { OP_EX_Vex, q_mode } -#define EXqVexS { OP_EX_Vex, q_swap_mode } #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } #define EXVexW { OP_EX_VexW, x_mode } #define EXdVexW { OP_EX_VexW, d_mode } #define EXqVexW { OP_EX_VexW, q_mode } #define EXVexImmW { OP_EX_VexImmW, x_mode } -#define XMVex { OP_XMM_Vex, 0 } #define XMVexScalar { OP_XMM_Vex, scalar_mode } #define XMVexW { OP_XMM_VexW, 0 } #define XMVexI4 { OP_REG_VexI4, x_mode } #define PCLMUL { PCLMUL_Fixup, 0 } -#define VZERO { VZERO_Fixup, 0 } #define VCMP { VCMP_Fixup, 0 } #define VPCMP { VPCMP_Fixup, 0 } #define VPCOM { VPCOM_Fixup, 0 } #define EXxEVexR { OP_Rounding, evex_rounding_mode } +#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } #define EXxEVexS { OP_Rounding, evex_sae_mode } #define XMask { OP_Mask, mask_mode } @@ -630,6 +622,8 @@ enum /* Static rounding. */ evex_rounding_mode, + /* Static rounding, 64-bit mode only. */ + evex_rounding_64_mode, /* Supress all exceptions. */ evex_sae_mode, @@ -699,7 +693,8 @@ enum USE_VEX_C5_TABLE, USE_VEX_LEN_TABLE, USE_VEX_W_TABLE, - USE_EVEX_TABLE + USE_EVEX_TABLE, + USE_EVEX_LEN_TABLE }; #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 @@ -719,6 +714,7 @@ enum #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) +#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) enum { @@ -742,8 +738,8 @@ enum REG_0F01, REG_0F0D, REG_0F18, - REG_0F1C_MOD_0, - REG_0F1E_MOD_3, + REG_0F1C_P_0_MOD_0, + REG_0F1E_P_1_MOD_3, REG_0F71, REG_0F72, REG_0F73, @@ -839,7 +835,9 @@ enum MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, + MOD_0F38F8_PREFIX_1, MOD_0F38F8_PREFIX_2, + MOD_0F38F8_PREFIX_3, MOD_0F38F9_PREFIX_0, MOD_62_32BIT, MOD_C4_32BIT, @@ -897,12 +895,10 @@ enum MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, - MOD_VEX_W_0_0F92_P_3_LEN_0, - MOD_VEX_W_1_0F92_P_3_LEN_0, + MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, - MOD_VEX_W_0_0F93_P_3_LEN_0, - MOD_VEX_W_1_0F93_P_3_LEN_0, + MOD_VEX_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0, @@ -934,10 +930,6 @@ enum MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0, - MOD_EVEX_0F10_PREFIX_1, - MOD_EVEX_0F10_PREFIX_3, - MOD_EVEX_0F11_PREFIX_1, - MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, @@ -958,19 +950,21 @@ enum RM_0F01_REG_1, RM_0F01_REG_2, RM_0F01_REG_3, - RM_0F01_REG_5, - RM_0F01_REG_7, - RM_0F1E_MOD_3_REG_7, - RM_0FAE_REG_6, - RM_0FAE_REG_7 + RM_0F01_REG_5_MOD_3, + RM_0F01_REG_7_MOD_3, + RM_0F1E_P_1_MOD_3_REG_7, + RM_0FAE_REG_6_MOD_3_P_0, + RM_0FAE_REG_7_MOD_3, }; enum { PREFIX_90 = 0, - PREFIX_MOD_0_0F01_REG_5, - PREFIX_MOD_3_0F01_REG_5_RM_0, - PREFIX_MOD_3_0F01_REG_5_RM_2, + PREFIX_0F01_REG_5_MOD_0, + PREFIX_0F01_REG_5_MOD_3_RM_0, + PREFIX_0F01_REG_5_MOD_3_RM_2, + PREFIX_0F01_REG_7_MOD_3_RM_2, + PREFIX_0F01_REG_7_MOD_3_RM_3, PREFIX_0F09, PREFIX_0F10, PREFIX_0F11, @@ -1012,25 +1006,25 @@ enum PREFIX_0F7D, PREFIX_0F7E, PREFIX_0F7F, - PREFIX_0FAE_REG_0, - PREFIX_0FAE_REG_1, - PREFIX_0FAE_REG_2, - PREFIX_0FAE_REG_3, - PREFIX_MOD_0_0FAE_REG_4, - PREFIX_MOD_3_0FAE_REG_4, - PREFIX_MOD_0_0FAE_REG_5, - PREFIX_MOD_3_0FAE_REG_5, - PREFIX_MOD_0_0FAE_REG_6, - PREFIX_MOD_1_0FAE_REG_6, - PREFIX_0FAE_REG_7, + PREFIX_0FAE_REG_0_MOD_3, + PREFIX_0FAE_REG_1_MOD_3, + PREFIX_0FAE_REG_2_MOD_3, + PREFIX_0FAE_REG_3_MOD_3, + PREFIX_0FAE_REG_4_MOD_0, + PREFIX_0FAE_REG_4_MOD_3, + PREFIX_0FAE_REG_5_MOD_0, + PREFIX_0FAE_REG_5_MOD_3, + PREFIX_0FAE_REG_6_MOD_0, + PREFIX_0FAE_REG_6_MOD_3, + PREFIX_0FAE_REG_7_MOD_0, PREFIX_0FB8, PREFIX_0FBC, PREFIX_0FBD, PREFIX_0FC2, - PREFIX_MOD_0_0FC3, - PREFIX_MOD_0_0FC7_REG_6, - PREFIX_MOD_3_0FC7_REG_6, - PREFIX_MOD_3_0FC7_REG_7, + PREFIX_0FC3_MOD_0, + PREFIX_0FC7_REG_6_MOD_0, + PREFIX_0FC7_REG_6_MOD_3, + PREFIX_0FC7_REG_7_MOD_3, PREFIX_0FD0, PREFIX_0FD6, PREFIX_0FE6, @@ -1607,6 +1601,7 @@ enum PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, + PREFIX_EVEX_0F3868, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, @@ -1806,11 +1801,7 @@ enum enum { - VEX_LEN_0F10_P_1 = 0, - VEX_LEN_0F10_P_3, - VEX_LEN_0F11_P_1, - VEX_LEN_0F11_P_3, - VEX_LEN_0F12_P_0_M_0, + VEX_LEN_0F12_P_0_M_0 = 0, VEX_LEN_0F12_P_0_M_1, VEX_LEN_0F12_P_2, VEX_LEN_0F13_M_0, @@ -1818,16 +1809,6 @@ enum VEX_LEN_0F16_P_0_M_1, VEX_LEN_0F16_P_2, VEX_LEN_0F17_M_0, - VEX_LEN_0F2A_P_1, - VEX_LEN_0F2A_P_3, - VEX_LEN_0F2C_P_1, - VEX_LEN_0F2C_P_3, - VEX_LEN_0F2D_P_1, - VEX_LEN_0F2D_P_3, - VEX_LEN_0F2E_P_0, - VEX_LEN_0F2E_P_2, - VEX_LEN_0F2F_P_0, - VEX_LEN_0F2F_P_2, VEX_LEN_0F41_P_0, VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, @@ -1844,25 +1825,8 @@ enum VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, - VEX_LEN_0F51_P_1, - VEX_LEN_0F51_P_3, - VEX_LEN_0F52_P_1, - VEX_LEN_0F53_P_1, - VEX_LEN_0F58_P_1, - VEX_LEN_0F58_P_3, - VEX_LEN_0F59_P_1, - VEX_LEN_0F59_P_3, - VEX_LEN_0F5A_P_1, - VEX_LEN_0F5A_P_3, - VEX_LEN_0F5C_P_1, - VEX_LEN_0F5C_P_3, - VEX_LEN_0F5D_P_1, - VEX_LEN_0F5D_P_3, - VEX_LEN_0F5E_P_1, - VEX_LEN_0F5E_P_3, - VEX_LEN_0F5F_P_1, - VEX_LEN_0F5F_P_3, VEX_LEN_0F6E_P_2, + VEX_LEN_0F77_P_0, VEX_LEN_0F7E_P_1, VEX_LEN_0F7E_P_2, VEX_LEN_0F90_P_0, @@ -1881,8 +1845,6 @@ enum VEX_LEN_0F99_P_2, VEX_LEN_0FAE_R_2_M_0, VEX_LEN_0FAE_R_3_M_0, - VEX_LEN_0FC2_P_1, - VEX_LEN_0FC2_P_3, VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2, @@ -1909,8 +1871,6 @@ enum VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2, VEX_LEN_0F3A06_P_2, - VEX_LEN_0F3A0A_P_2, - VEX_LEN_0F3A0B_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2, VEX_LEN_0F3A16_P_2, @@ -1956,35 +1916,57 @@ enum enum { - VEX_W_0F10_P_0 = 0, - VEX_W_0F10_P_1, - VEX_W_0F10_P_2, - VEX_W_0F10_P_3, - VEX_W_0F11_P_0, - VEX_W_0F11_P_1, - VEX_W_0F11_P_2, - VEX_W_0F11_P_3, - VEX_W_0F12_P_0_M_0, - VEX_W_0F12_P_0_M_1, - VEX_W_0F12_P_1, - VEX_W_0F12_P_2, - VEX_W_0F12_P_3, - VEX_W_0F13_M_0, - VEX_W_0F14, - VEX_W_0F15, - VEX_W_0F16_P_0_M_0, - VEX_W_0F16_P_0_M_1, - VEX_W_0F16_P_1, - VEX_W_0F16_P_2, - VEX_W_0F17_M_0, - VEX_W_0F28, - VEX_W_0F29, - VEX_W_0F2B_M_0, - VEX_W_0F2E_P_0, - VEX_W_0F2E_P_2, - VEX_W_0F2F_P_0, - VEX_W_0F2F_P_2, - VEX_W_0F41_P_0_LEN_1, + EVEX_LEN_0F6E_P_2 = 0, + EVEX_LEN_0F7E_P_1, + EVEX_LEN_0F7E_P_2, + EVEX_LEN_0FD6_P_2, + EVEX_LEN_0F3819_P_2_W_0, + EVEX_LEN_0F3819_P_2_W_1, + EVEX_LEN_0F381A_P_2_W_0, + EVEX_LEN_0F381A_P_2_W_1, + EVEX_LEN_0F381B_P_2_W_0, + EVEX_LEN_0F381B_P_2_W_1, + EVEX_LEN_0F385A_P_2_W_0, + EVEX_LEN_0F385A_P_2_W_1, + EVEX_LEN_0F385B_P_2_W_0, + EVEX_LEN_0F385B_P_2_W_1, + EVEX_LEN_0F38C6_REG_1_PREFIX_2, + EVEX_LEN_0F38C6_REG_2_PREFIX_2, + EVEX_LEN_0F38C6_REG_5_PREFIX_2, + EVEX_LEN_0F38C6_REG_6_PREFIX_2, + EVEX_LEN_0F38C7_R_1_P_2_W_0, + EVEX_LEN_0F38C7_R_1_P_2_W_1, + EVEX_LEN_0F38C7_R_2_P_2_W_0, + EVEX_LEN_0F38C7_R_2_P_2_W_1, + EVEX_LEN_0F38C7_R_5_P_2_W_0, + EVEX_LEN_0F38C7_R_5_P_2_W_1, + EVEX_LEN_0F38C7_R_6_P_2_W_0, + EVEX_LEN_0F38C7_R_6_P_2_W_1, + EVEX_LEN_0F3A18_P_2_W_0, + EVEX_LEN_0F3A18_P_2_W_1, + EVEX_LEN_0F3A19_P_2_W_0, + EVEX_LEN_0F3A19_P_2_W_1, + EVEX_LEN_0F3A1A_P_2_W_0, + EVEX_LEN_0F3A1A_P_2_W_1, + EVEX_LEN_0F3A1B_P_2_W_0, + EVEX_LEN_0F3A1B_P_2_W_1, + EVEX_LEN_0F3A23_P_2_W_0, + EVEX_LEN_0F3A23_P_2_W_1, + EVEX_LEN_0F3A38_P_2_W_0, + EVEX_LEN_0F3A38_P_2_W_1, + EVEX_LEN_0F3A39_P_2_W_0, + EVEX_LEN_0F3A39_P_2_W_1, + EVEX_LEN_0F3A3A_P_2_W_0, + EVEX_LEN_0F3A3A_P_2_W_1, + EVEX_LEN_0F3A3B_P_2_W_0, + EVEX_LEN_0F3A3B_P_2_W_1, + EVEX_LEN_0F3A43_P_2_W_0, + EVEX_LEN_0F3A43_P_2_W_1 +}; + +enum +{ + VEX_W_0F41_P_0_LEN_1 = 0, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F42_P_2_LEN_1, @@ -2000,213 +1982,31 @@ enum VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, - VEX_W_0F50_M_0, - VEX_W_0F51_P_0, - VEX_W_0F51_P_1, - VEX_W_0F51_P_2, - VEX_W_0F51_P_3, - VEX_W_0F52_P_0, - VEX_W_0F52_P_1, - VEX_W_0F53_P_0, - VEX_W_0F53_P_1, - VEX_W_0F58_P_0, - VEX_W_0F58_P_1, - VEX_W_0F58_P_2, - VEX_W_0F58_P_3, - VEX_W_0F59_P_0, - VEX_W_0F59_P_1, - VEX_W_0F59_P_2, - VEX_W_0F59_P_3, - VEX_W_0F5A_P_0, - VEX_W_0F5A_P_1, - VEX_W_0F5A_P_3, - VEX_W_0F5B_P_0, - VEX_W_0F5B_P_1, - VEX_W_0F5B_P_2, - VEX_W_0F5C_P_0, - VEX_W_0F5C_P_1, - VEX_W_0F5C_P_2, - VEX_W_0F5C_P_3, - VEX_W_0F5D_P_0, - VEX_W_0F5D_P_1, - VEX_W_0F5D_P_2, - VEX_W_0F5D_P_3, - VEX_W_0F5E_P_0, - VEX_W_0F5E_P_1, - VEX_W_0F5E_P_2, - VEX_W_0F5E_P_3, - VEX_W_0F5F_P_0, - VEX_W_0F5F_P_1, - VEX_W_0F5F_P_2, - VEX_W_0F5F_P_3, - VEX_W_0F60_P_2, - VEX_W_0F61_P_2, - VEX_W_0F62_P_2, - VEX_W_0F63_P_2, - VEX_W_0F64_P_2, - VEX_W_0F65_P_2, - VEX_W_0F66_P_2, - VEX_W_0F67_P_2, - VEX_W_0F68_P_2, - VEX_W_0F69_P_2, - VEX_W_0F6A_P_2, - VEX_W_0F6B_P_2, - VEX_W_0F6C_P_2, - VEX_W_0F6D_P_2, - VEX_W_0F6F_P_1, - VEX_W_0F6F_P_2, - VEX_W_0F70_P_1, - VEX_W_0F70_P_2, - VEX_W_0F70_P_3, - VEX_W_0F71_R_2_P_2, - VEX_W_0F71_R_4_P_2, - VEX_W_0F71_R_6_P_2, - VEX_W_0F72_R_2_P_2, - VEX_W_0F72_R_4_P_2, - VEX_W_0F72_R_6_P_2, - VEX_W_0F73_R_2_P_2, - VEX_W_0F73_R_3_P_2, - VEX_W_0F73_R_6_P_2, - VEX_W_0F73_R_7_P_2, - VEX_W_0F74_P_2, - VEX_W_0F75_P_2, - VEX_W_0F76_P_2, - VEX_W_0F77_P_0, - VEX_W_0F7C_P_2, - VEX_W_0F7C_P_3, - VEX_W_0F7D_P_2, - VEX_W_0F7D_P_3, - VEX_W_0F7E_P_1, - VEX_W_0F7F_P_1, - VEX_W_0F7F_P_2, VEX_W_0F90_P_0_LEN_0, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F92_P_2_LEN_0, - VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F93_P_2_LEN_0, - VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, - VEX_W_0FAE_R_2_M_0, - VEX_W_0FAE_R_3_M_0, - VEX_W_0FC2_P_0, - VEX_W_0FC2_P_1, - VEX_W_0FC2_P_2, - VEX_W_0FC2_P_3, - VEX_W_0FC4_P_2, - VEX_W_0FC5_P_2, - VEX_W_0FD0_P_2, - VEX_W_0FD0_P_3, - VEX_W_0FD1_P_2, - VEX_W_0FD2_P_2, - VEX_W_0FD3_P_2, - VEX_W_0FD4_P_2, - VEX_W_0FD5_P_2, - VEX_W_0FD6_P_2, - VEX_W_0FD7_P_2_M_1, - VEX_W_0FD8_P_2, - VEX_W_0FD9_P_2, - VEX_W_0FDA_P_2, - VEX_W_0FDB_P_2, - VEX_W_0FDC_P_2, - VEX_W_0FDD_P_2, - VEX_W_0FDE_P_2, - VEX_W_0FDF_P_2, - VEX_W_0FE0_P_2, - VEX_W_0FE1_P_2, - VEX_W_0FE2_P_2, - VEX_W_0FE3_P_2, - VEX_W_0FE4_P_2, - VEX_W_0FE5_P_2, - VEX_W_0FE6_P_1, - VEX_W_0FE6_P_2, - VEX_W_0FE6_P_3, - VEX_W_0FE7_P_2_M_0, - VEX_W_0FE8_P_2, - VEX_W_0FE9_P_2, - VEX_W_0FEA_P_2, - VEX_W_0FEB_P_2, - VEX_W_0FEC_P_2, - VEX_W_0FED_P_2, - VEX_W_0FEE_P_2, - VEX_W_0FEF_P_2, - VEX_W_0FF0_P_3_M_0, - VEX_W_0FF1_P_2, - VEX_W_0FF2_P_2, - VEX_W_0FF3_P_2, - VEX_W_0FF4_P_2, - VEX_W_0FF5_P_2, - VEX_W_0FF6_P_2, - VEX_W_0FF7_P_2, - VEX_W_0FF8_P_2, - VEX_W_0FF9_P_2, - VEX_W_0FFA_P_2, - VEX_W_0FFB_P_2, - VEX_W_0FFC_P_2, - VEX_W_0FFD_P_2, - VEX_W_0FFE_P_2, - VEX_W_0F3800_P_2, - VEX_W_0F3801_P_2, - VEX_W_0F3802_P_2, - VEX_W_0F3803_P_2, - VEX_W_0F3804_P_2, - VEX_W_0F3805_P_2, - VEX_W_0F3806_P_2, - VEX_W_0F3807_P_2, - VEX_W_0F3808_P_2, - VEX_W_0F3809_P_2, - VEX_W_0F380A_P_2, - VEX_W_0F380B_P_2, VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2, VEX_W_0F380F_P_2, VEX_W_0F3816_P_2, - VEX_W_0F3817_P_2, VEX_W_0F3818_P_2, VEX_W_0F3819_P_2, VEX_W_0F381A_P_2_M_0, - VEX_W_0F381C_P_2, - VEX_W_0F381D_P_2, - VEX_W_0F381E_P_2, - VEX_W_0F3820_P_2, - VEX_W_0F3821_P_2, - VEX_W_0F3822_P_2, - VEX_W_0F3823_P_2, - VEX_W_0F3824_P_2, - VEX_W_0F3825_P_2, - VEX_W_0F3828_P_2, - VEX_W_0F3829_P_2, - VEX_W_0F382A_P_2_M_0, - VEX_W_0F382B_P_2, VEX_W_0F382C_P_2_M_0, VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0, VEX_W_0F382F_P_2_M_0, - VEX_W_0F3830_P_2, - VEX_W_0F3831_P_2, - VEX_W_0F3832_P_2, - VEX_W_0F3833_P_2, - VEX_W_0F3834_P_2, - VEX_W_0F3835_P_2, VEX_W_0F3836_P_2, - VEX_W_0F3837_P_2, - VEX_W_0F3838_P_2, - VEX_W_0F3839_P_2, - VEX_W_0F383A_P_2, - VEX_W_0F383B_P_2, - VEX_W_0F383C_P_2, - VEX_W_0F383D_P_2, - VEX_W_0F383E_P_2, - VEX_W_0F383F_P_2, - VEX_W_0F3840_P_2, - VEX_W_0F3841_P_2, VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2, @@ -2214,60 +2014,37 @@ enum VEX_W_0F3878_P_2, VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, - VEX_W_0F38DB_P_2, VEX_W_0F3A00_P_2, VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2, VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2, - VEX_W_0F3A08_P_2, - VEX_W_0F3A09_P_2, - VEX_W_0F3A0A_P_2, - VEX_W_0F3A0B_P_2, - VEX_W_0F3A0C_P_2, - VEX_W_0F3A0D_P_2, - VEX_W_0F3A0E_P_2, - VEX_W_0F3A0F_P_2, - VEX_W_0F3A14_P_2, - VEX_W_0F3A15_P_2, VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, - VEX_W_0F3A20_P_2, - VEX_W_0F3A21_P_2, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2, VEX_W_0F3A39_P_2, - VEX_W_0F3A40_P_2, - VEX_W_0F3A41_P_2, - VEX_W_0F3A42_P_2, VEX_W_0F3A46_P_2, VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2, - VEX_W_0F3A62_P_2, - VEX_W_0F3A63_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, - VEX_W_0F3ADF_P_2, EVEX_W_0F10_P_0, - EVEX_W_0F10_P_1_M_0, - EVEX_W_0F10_P_1_M_1, + EVEX_W_0F10_P_1, EVEX_W_0F10_P_2, - EVEX_W_0F10_P_3_M_0, - EVEX_W_0F10_P_3_M_1, + EVEX_W_0F10_P_3, EVEX_W_0F11_P_0, - EVEX_W_0F11_P_1_M_0, - EVEX_W_0F11_P_1_M_1, + EVEX_W_0F11_P_1, EVEX_W_0F11_P_2, - EVEX_W_0F11_P_3_M_0, - EVEX_W_0F11_P_3_M_1, + EVEX_W_0F11_P_3, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, @@ -2289,7 +2066,6 @@ enum EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, - EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, @@ -2346,7 +2122,6 @@ enum EVEX_W_0F6B_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, - EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F6F_P_3, @@ -2363,11 +2138,9 @@ enum EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_2, EVEX_W_0F7A_P_3, - EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_2, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, - EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0F7F_P_3, @@ -2437,6 +2210,7 @@ enum EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, + EVEX_W_0F3852_P_1, EVEX_W_0F3854_P_2, EVEX_W_0F3855_P_2, EVEX_W_0F3858_P_2, @@ -2446,9 +2220,12 @@ enum EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3866_P_2, + EVEX_W_0F3868_P_3, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, + EVEX_W_0F3872_P_1, EVEX_W_0F3872_P_2, + EVEX_W_0F3872_P_3, EVEX_W_0F3873_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, @@ -2475,14 +2252,12 @@ enum EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, - EVEX_W_0F3A16_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, - EVEX_W_0F3A22_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, @@ -3661,7 +3436,7 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F18_REG_6) }, { MOD_TABLE (MOD_0F18_REG_7) }, }, - /* REG_0F1C_MOD_0 */ + /* REG_0F1C_P_0_MOD_0 */ { { "cldemote", { Mb }, 0 }, { "nopQ", { Ev }, 0 }, @@ -3672,7 +3447,7 @@ static const struct dis386 reg_table[][8] = { { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, }, - /* REG_0F1E_MOD_3 */ + /* REG_0F1E_P_1_MOD_3 */ { { "nopQ", { Ev }, 0 }, { "rdsspK", { Rdq }, PREFIX_OPCODE }, @@ -3681,7 +3456,7 @@ static const struct dis386 reg_table[][8] = { { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, - { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, + { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, }, /* REG_0F71 */ { @@ -3814,33 +3589,32 @@ static const struct dis386 reg_table[][8] = { }, /* REG_XOP_LWP */ { - { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, - { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, + { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, + { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, }, /* REG_XOP_TBM_01 */ { { Bad_Opcode }, - { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, }, /* REG_XOP_TBM_02 */ { { Bad_Opcode }, - { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, }, -#define NEED_REG_TABLE -#include "i386-dis-evex.h" -#undef NEED_REG_TABLE + +#include "i386-dis-evex-reg.h" }; static const struct dis386 prefix_table[][4] = { @@ -3852,24 +3626,35 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, - /* PREFIX_MOD_0_0F01_REG_5 */ + /* PREFIX_0F01_REG_5_MOD_0 */ { { Bad_Opcode }, { "rstorssp", { Mq }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ + /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ { { Bad_Opcode }, { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ + /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ { { Bad_Opcode }, { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, }, + /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ + { + { "monitorx", { { OP_Monitor, 0 } }, 0 }, + { "mcommit", { Skip_MODRM }, 0 }, + }, + + /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ + { + { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, + }, + /* PREFIX_0F09 */ { { "wbinvd", { XX }, 0 }, @@ -3942,9 +3727,9 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2A */ { { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, - { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, + { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, - { "cvtsi2sd%LQ", { XM, Ev }, 0 }, + { "cvtsi2sd%LQ", { XM, Edq }, 0 }, }, /* PREFIX_0F2B */ @@ -3958,17 +3743,17 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2C */ { { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, + { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, + { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2D */ { { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, + { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, + { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2E */ @@ -4178,69 +3963,69 @@ static const struct dis386 prefix_table[][4] = { { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_0 */ + /* PREFIX_0FAE_REG_0_MOD_3 */ { { Bad_Opcode }, { "rdfsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_1 */ + /* PREFIX_0FAE_REG_1_MOD_3 */ { { Bad_Opcode }, { "rdgsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_2 */ + /* PREFIX_0FAE_REG_2_MOD_3 */ { { Bad_Opcode }, { "wrfsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_3 */ + /* PREFIX_0FAE_REG_3_MOD_3 */ { { Bad_Opcode }, { "wrgsbase", { Ev }, 0 }, }, - /* PREFIX_MOD_0_0FAE_REG_4 */ + /* PREFIX_0FAE_REG_4_MOD_0 */ { { "xsave", { FXSAVE }, 0 }, { "ptwrite%LQ", { Edq }, 0 }, }, - /* PREFIX_MOD_3_0FAE_REG_4 */ + /* PREFIX_0FAE_REG_4_MOD_3 */ { { Bad_Opcode }, { "ptwrite%LQ", { Edq }, 0 }, }, - /* PREFIX_MOD_0_0FAE_REG_5 */ + /* PREFIX_0FAE_REG_5_MOD_0 */ { { "xrstor", { FXSAVE }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_3_0FAE_REG_5 */ + /* PREFIX_0FAE_REG_5_MOD_3 */ { { "lfence", { Skip_MODRM }, 0 }, { "incsspK", { Rdq }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_0_0FAE_REG_6 */ + /* PREFIX_0FAE_REG_6_MOD_0 */ { { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, { "clrssbsy", { Mq }, PREFIX_OPCODE }, { "clwb", { Mb }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_1_0FAE_REG_6 */ + /* PREFIX_0FAE_REG_6_MOD_3 */ { - { RM_TABLE (RM_0FAE_REG_6) }, + { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, { "umonitor", { Eva }, PREFIX_OPCODE }, { "tpause", { Edq }, PREFIX_OPCODE }, { "umwait", { Edq }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_7 */ + /* PREFIX_0FAE_REG_7_MOD_0 */ { { "clflush", { Mb }, 0 }, { Bad_Opcode }, @@ -4275,26 +4060,26 @@ static const struct dis386 prefix_table[][4] = { { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_0_0FC3 */ + /* PREFIX_0FC3_MOD_0 */ { - { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, + { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_0_0FC7_REG_6 */ + /* PREFIX_0FC7_REG_6_MOD_0 */ { { "vmptrld",{ Mq }, 0 }, { "vmxon", { Mq }, 0 }, { "vmclear",{ Mq }, 0 }, }, - /* PREFIX_MOD_3_0FC7_REG_6 */ + /* PREFIX_0FC7_REG_6_MOD_3 */ { { "rdrand", { Ev }, 0 }, { Bad_Opcode }, { "rdrand", { Ev }, 0 } }, - /* PREFIX_MOD_3_0FC7_REG_7 */ + /* PREFIX_0FC7_REG_7_MOD_3 */ { { "rdseed", { Ev }, 0 }, { "rdpid", { Em }, 0 }, @@ -4691,8 +4476,9 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F38F8 */ { { Bad_Opcode }, - { Bad_Opcode }, + { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, + { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, }, /* PREFIX_0F38F9 */ @@ -4882,71 +4668,71 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F10 */ { - { VEX_W_TABLE (VEX_W_0F10_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, - { VEX_W_TABLE (VEX_W_0F10_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, + { "vmovups", { XM, EXx }, 0 }, + { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, + { "vmovupd", { XM, EXx }, 0 }, + { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F11 */ { - { VEX_W_TABLE (VEX_W_0F11_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, - { VEX_W_TABLE (VEX_W_0F11_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, + { "vmovups", { EXxS, XM }, 0 }, + { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, + { "vmovupd", { EXxS, XM }, 0 }, + { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, }, /* PREFIX_VEX_0F12 */ { { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, - { VEX_W_TABLE (VEX_W_0F12_P_1) }, + { "vmovsldup", { XM, EXx }, 0 }, { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, - { VEX_W_TABLE (VEX_W_0F12_P_3) }, + { "vmovddup", { XM, EXymmq }, 0 }, }, /* PREFIX_VEX_0F16 */ { { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, - { VEX_W_TABLE (VEX_W_0F16_P_1) }, + { "vmovshdup", { XM, EXx }, 0 }, { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, }, /* PREFIX_VEX_0F2A */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, }, /* PREFIX_VEX_0F2C */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, + { "vcvttss2si", { Gdq, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, + { "vcvttsd2si", { Gdq, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2D */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, + { "vcvtss2si", { Gdq, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, + { "vcvtsd2si", { Gdq, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2E */ { - { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, + { "vucomiss", { XMScalar, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, + { "vucomisd", { XMScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2F */ { - { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, + { "vcomiss", { XMScalar, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, + { "vcomisd", { XMScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F41 */ @@ -5007,183 +4793,183 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F51 */ { - { VEX_W_TABLE (VEX_W_0F51_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, - { VEX_W_TABLE (VEX_W_0F51_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, + { "vsqrtps", { XM, EXx }, 0 }, + { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vsqrtpd", { XM, EXx }, 0 }, + { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F52 */ { - { VEX_W_TABLE (VEX_W_0F52_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, + { "vrsqrtps", { XM, EXx }, 0 }, + { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, /* PREFIX_VEX_0F53 */ { - { VEX_W_TABLE (VEX_W_0F53_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, + { "vrcpps", { XM, EXx }, 0 }, + { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, /* PREFIX_VEX_0F58 */ { - { VEX_W_TABLE (VEX_W_0F58_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, - { VEX_W_TABLE (VEX_W_0F58_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, + { "vaddps", { XM, Vex, EXx }, 0 }, + { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vaddpd", { XM, Vex, EXx }, 0 }, + { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F59 */ { - { VEX_W_TABLE (VEX_W_0F59_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, - { VEX_W_TABLE (VEX_W_0F59_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, + { "vmulps", { XM, Vex, EXx }, 0 }, + { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vmulpd", { XM, Vex, EXx }, 0 }, + { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5A */ { - { VEX_W_TABLE (VEX_W_0F5A_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, - { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, - { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, + { "vcvtps2pd", { XM, EXxmmq }, 0 }, + { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, + { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5B */ { - { VEX_W_TABLE (VEX_W_0F5B_P_0) }, - { VEX_W_TABLE (VEX_W_0F5B_P_1) }, - { VEX_W_TABLE (VEX_W_0F5B_P_2) }, + { "vcvtdq2ps", { XM, EXx }, 0 }, + { "vcvttps2dq", { XM, EXx }, 0 }, + { "vcvtps2dq", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F5C */ { - { VEX_W_TABLE (VEX_W_0F5C_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, - { VEX_W_TABLE (VEX_W_0F5C_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, + { "vsubps", { XM, Vex, EXx }, 0 }, + { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vsubpd", { XM, Vex, EXx }, 0 }, + { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5D */ { - { VEX_W_TABLE (VEX_W_0F5D_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, - { VEX_W_TABLE (VEX_W_0F5D_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, + { "vminps", { XM, Vex, EXx }, 0 }, + { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vminpd", { XM, Vex, EXx }, 0 }, + { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5E */ { - { VEX_W_TABLE (VEX_W_0F5E_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, - { VEX_W_TABLE (VEX_W_0F5E_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, + { "vdivps", { XM, Vex, EXx }, 0 }, + { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vdivpd", { XM, Vex, EXx }, 0 }, + { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5F */ { - { VEX_W_TABLE (VEX_W_0F5F_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, - { VEX_W_TABLE (VEX_W_0F5F_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, + { "vmaxps", { XM, Vex, EXx }, 0 }, + { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vmaxpd", { XM, Vex, EXx }, 0 }, + { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F60 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F60_P_2) }, + { "vpunpcklbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F61 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F61_P_2) }, + { "vpunpcklwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F62 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F62_P_2) }, + { "vpunpckldq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F63 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F63_P_2) }, + { "vpacksswb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F64 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F64_P_2) }, + { "vpcmpgtb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F65 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F65_P_2) }, + { "vpcmpgtw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F66 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F66_P_2) }, + { "vpcmpgtd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F67 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F67_P_2) }, + { "vpackuswb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F68 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F68_P_2) }, + { "vpunpckhbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F69 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F69_P_2) }, + { "vpunpckhwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6A_P_2) }, + { "vpunpckhdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6B_P_2) }, + { "vpackssdw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6C_P_2) }, + { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6D_P_2) }, + { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6E */ @@ -5196,128 +4982,128 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F6F */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6F_P_1) }, - { VEX_W_TABLE (VEX_W_0F6F_P_2) }, + { "vmovdqu", { XM, EXx }, 0 }, + { "vmovdqa", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F70 */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F70_P_1) }, - { VEX_W_TABLE (VEX_W_0F70_P_2) }, - { VEX_W_TABLE (VEX_W_0F70_P_3) }, + { "vpshufhw", { XM, EXx, Ib }, 0 }, + { "vpshufd", { XM, EXx, Ib }, 0 }, + { "vpshuflw", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, + { "vpsrlw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, + { "vpsraw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, + { "vpsllw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, + { "vpsrld", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, + { "vpsrad", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, + { "vpslld", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, + { "vpsrlq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, + { "vpsrldq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, + { "vpsllq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_7 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, + { "vpslldq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F74 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F74_P_2) }, + { "vpcmpeqb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F75 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F75_P_2) }, + { "vpcmpeqw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F76 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F76_P_2) }, + { "vpcmpeqd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F77 */ { - { VEX_W_TABLE (VEX_W_0F77_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, }, /* PREFIX_VEX_0F7C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7C_P_2) }, - { VEX_W_TABLE (VEX_W_0F7C_P_3) }, + { "vhaddpd", { XM, Vex, EXx }, 0 }, + { "vhaddps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F7D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7D_P_2) }, - { VEX_W_TABLE (VEX_W_0F7D_P_3) }, + { "vhsubpd", { XM, Vex, EXx }, 0 }, + { "vhsubps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F7E */ @@ -5330,8 +5116,8 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F7F */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7F_P_1) }, - { VEX_W_TABLE (VEX_W_0F7F_P_2) }, + { "vmovdqu", { EXxS, XM }, 0 }, + { "vmovdqa", { EXxS, XM }, 0 }, }, /* PREFIX_VEX_0F90 */ @@ -5380,10 +5166,10 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0FC2 */ { - { VEX_W_TABLE (VEX_W_0FC2_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, - { VEX_W_TABLE (VEX_W_0FC2_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, + { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, + { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, + { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, + { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, }, /* PREFIX_VEX_0FC4 */ @@ -5404,43 +5190,43 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD0_P_2) }, - { VEX_W_TABLE (VEX_W_0FD0_P_3) }, + { "vaddsubpd", { XM, Vex, EXx }, 0 }, + { "vaddsubps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD1 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD1_P_2) }, + { "vpsrlw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD2_P_2) }, + { "vpsrld", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD3_P_2) }, + { "vpsrlq", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD4_P_2) }, + { "vpaddq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD5_P_2) }, + { "vpmullw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD6 */ @@ -5461,106 +5247,106 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD8_P_2) }, + { "vpsubusb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD9_P_2) }, + { "vpsubusw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDA_P_2) }, + { "vpminub", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDB_P_2) }, + { "vpand", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDC_P_2) }, + { "vpaddusb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDD */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDD_P_2) }, + { "vpaddusw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDE_P_2) }, + { "vpmaxub", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDF */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDF_P_2) }, + { "vpandn", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE0 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE0_P_2) }, + { "vpavgb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE1 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE1_P_2) }, + { "vpsraw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FE2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE2_P_2) }, + { "vpsrad", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FE3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE3_P_2) }, + { "vpavgw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE4_P_2) }, + { "vpmulhuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE5_P_2) }, + { "vpmulhw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE6 */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE6_P_1) }, - { VEX_W_TABLE (VEX_W_0FE6_P_2) }, - { VEX_W_TABLE (VEX_W_0FE6_P_3) }, + { "vcvtdq2pd", { XM, EXxmmq }, 0 }, + { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, + { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, }, /* PREFIX_VEX_0FE7 */ @@ -5574,56 +5360,56 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE8_P_2) }, + { "vpsubsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE9_P_2) }, + { "vpsubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEA_P_2) }, + { "vpminsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEB_P_2) }, + { "vpor", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEC_P_2) }, + { "vpaddsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FED */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FED_P_2) }, + { "vpaddsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEE_P_2) }, + { "vpmaxsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEF */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEF_P_2) }, + { "vpxor", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF0 */ @@ -5638,42 +5424,42 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF1_P_2) }, + { "vpsllw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF2_P_2) }, + { "vpslld", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF3_P_2) }, + { "vpsllq", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF4_P_2) }, + { "vpmuludq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF5_P_2) }, + { "vpmaddwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF6_P_2) }, + { "vpsadbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF7 */ @@ -5687,133 +5473,133 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF8_P_2) }, + { "vpsubb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF9_P_2) }, + { "vpsubw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFA_P_2) }, + { "vpsubd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFB_P_2) }, + { "vpsubq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFC_P_2) }, + { "vpaddb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFD */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFD_P_2) }, + { "vpaddw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFE_P_2) }, + { "vpaddd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3800 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3800_P_2) }, + { "vpshufb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3801 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3801_P_2) }, + { "vphaddw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3802 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3802_P_2) }, + { "vphaddd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3803 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3803_P_2) }, + { "vphaddsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3804 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3804_P_2) }, + { "vpmaddubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3805 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3805_P_2) }, + { "vphsubw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3806 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3806_P_2) }, + { "vphsubd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3807 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3807_P_2) }, + { "vphsubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3808 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3808_P_2) }, + { "vpsignb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3809 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3809_P_2) }, + { "vpsignw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F380A_P_2) }, + { "vpsignd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F380B_P_2) }, + { "vpmulhrsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380C */ @@ -5862,7 +5648,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3817_P_2) }, + { "vptest", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F3818 */ @@ -5890,77 +5676,77 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381C_P_2) }, + { "vpabsb", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F381D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381D_P_2) }, + { "vpabsw", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F381E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381E_P_2) }, + { "vpabsd", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F3820 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3820_P_2) }, + { "vpmovsxbw", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3821 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3821_P_2) }, + { "vpmovsxbd", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3822 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3822_P_2) }, + { "vpmovsxbq", { XM, EXxmmdw }, 0 }, }, /* PREFIX_VEX_0F3823 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3823_P_2) }, + { "vpmovsxwd", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3824 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3824_P_2) }, + { "vpmovsxwq", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3825 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3825_P_2) }, + { "vpmovsxdq", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3828 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3828_P_2) }, + { "vpmuldq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3829 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3829_P_2) }, + { "vpcmpeqq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F382A */ @@ -5974,7 +5760,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F382B_P_2) }, + { "vpackusdw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F382C */ @@ -6009,42 +5795,42 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3830_P_2) }, + { "vpmovzxbw", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3831 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3831_P_2) }, + { "vpmovzxbd", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3832 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3832_P_2) }, + { "vpmovzxbq", { XM, EXxmmdw }, 0 }, }, /* PREFIX_VEX_0F3833 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3833_P_2) }, + { "vpmovzxwd", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3834 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3834_P_2) }, + { "vpmovzxwq", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3835 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3835_P_2) }, + { "vpmovzxdq", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3836 */ @@ -6058,70 +5844,70 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3837_P_2) }, + { "vpcmpgtq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3838 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3838_P_2) }, + { "vpminsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3839 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3839_P_2) }, + { "vpminsd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383A_P_2) }, + { "vpminuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383B_P_2) }, + { "vpminud", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383C_P_2) }, + { "vpmaxsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383D_P_2) }, + { "vpmaxsd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383E_P_2) }, + { "vpmaxuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383F */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383F_P_2) }, + { "vpmaxud", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3840 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3840_P_2) }, + { "vpmulld", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3841 */ @@ -6572,56 +6358,56 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, + { "vroundps", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A09 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, + { "vroundpd", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, + { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, + { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, + { "vblendps", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, + { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, + { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0F */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, + { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A14 */ @@ -6740,7 +6526,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, + { "vdpps", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A41 */ @@ -6754,7 +6540,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, + { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A44 */ @@ -7005,9 +6791,7 @@ static const struct dis386 prefix_table[][4] = { { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, }, -#define NEED_PREFIX_TABLE -#include "i386-dis-evex.h" -#undef NEED_PREFIX_TABLE +#include "i386-dis-evex-prefix.h" }; static const struct dis386 x86_64_table[][2] = { @@ -8370,7 +8154,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { "bextr", { Gv, Ev, Iq }, 0 }, + { "bextrS", { Gdq, Edq, Id }, 0 }, { Bad_Opcode }, { REG_TABLE (REG_XOP_LWP) }, { Bad_Opcode }, @@ -8668,8 +8452,8 @@ static const struct dis386 vex_table[][256] = { { PREFIX_TABLE (PREFIX_VEX_0F11) }, { PREFIX_TABLE (PREFIX_VEX_0F12) }, { MOD_TABLE (MOD_VEX_0F13) }, - { VEX_W_TABLE (VEX_W_0F14) }, - { VEX_W_TABLE (VEX_W_0F15) }, + { "vunpcklpX", { XM, Vex, EXx }, 0 }, + { "vunpckhpX", { XM, Vex, EXx }, 0 }, { PREFIX_TABLE (PREFIX_VEX_0F16) }, { MOD_TABLE (MOD_VEX_0F17) }, /* 18 */ @@ -8691,8 +8475,8 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 28 */ - { VEX_W_TABLE (VEX_W_0F28) }, - { VEX_W_TABLE (VEX_W_0F29) }, + { "vmovapX", { XM, EXx }, 0 }, + { "vmovapX", { EXxS, XM }, 0 }, { PREFIX_TABLE (PREFIX_VEX_0F2A) }, { MOD_TABLE (MOD_VEX_0F2B) }, { PREFIX_TABLE (PREFIX_VEX_0F2C) }, @@ -9518,166 +9302,81 @@ static const struct dis386 vex_table[][256] = { }, }; -#define NEED_OPCODE_TABLE #include "i386-dis-evex.h" -#undef NEED_OPCODE_TABLE -static const struct dis386 vex_len_table[][2] = { - /* VEX_LEN_0F10_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F10_P_1) }, - { VEX_W_TABLE (VEX_W_0F10_P_1) }, - }, - - /* VEX_LEN_0F10_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F10_P_3) }, - { VEX_W_TABLE (VEX_W_0F10_P_3) }, - }, - - /* VEX_LEN_0F11_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F11_P_1) }, - { VEX_W_TABLE (VEX_W_0F11_P_1) }, - }, - - /* VEX_LEN_0F11_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F11_P_3) }, - { VEX_W_TABLE (VEX_W_0F11_P_3) }, - }, +static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F12_P_0_M_0 */ { - { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, + { "vmovlps", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F12_P_0_M_1 */ { - { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, + { "vmovhlps", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F12_P_2 */ { - { VEX_W_TABLE (VEX_W_0F12_P_2) }, + { "vmovlpd", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F13_M_0 */ { - { VEX_W_TABLE (VEX_W_0F13_M_0) }, + { "vmovlpX", { EXq, XM }, 0 }, }, /* VEX_LEN_0F16_P_0_M_0 */ { - { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, + { "vmovhps", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F16_P_0_M_1 */ { - { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, + { "vmovlhps", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F16_P_2 */ { - { VEX_W_TABLE (VEX_W_0F16_P_2) }, + { "vmovhpd", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F17_M_0 */ { - { VEX_W_TABLE (VEX_W_0F17_M_0) }, + { "vmovhpX", { EXq, XM }, 0 }, }, - /* VEX_LEN_0F2A_P_1 */ + /* VEX_LEN_0F41_P_0 */ { - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, }, - - /* VEX_LEN_0F2A_P_3 */ + /* VEX_LEN_0F41_P_2 */ { - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, }, - - /* VEX_LEN_0F2C_P_1 */ + /* VEX_LEN_0F42_P_0 */ { - { "vcvttss2si", { Gv, EXdScalar }, 0 }, - { "vcvttss2si", { Gv, EXdScalar }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, }, - - /* VEX_LEN_0F2C_P_3 */ + /* VEX_LEN_0F42_P_2 */ { - { "vcvttsd2si", { Gv, EXqScalar }, 0 }, - { "vcvttsd2si", { Gv, EXqScalar }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, }, - - /* VEX_LEN_0F2D_P_1 */ + /* VEX_LEN_0F44_P_0 */ { - { "vcvtss2si", { Gv, EXdScalar }, 0 }, - { "vcvtss2si", { Gv, EXdScalar }, 0 }, + { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, }, - - /* VEX_LEN_0F2D_P_3 */ + /* VEX_LEN_0F44_P_2 */ { - { "vcvtsd2si", { Gv, EXqScalar }, 0 }, - { "vcvtsd2si", { Gv, EXqScalar }, 0 }, + { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, }, - - /* VEX_LEN_0F2E_P_0 */ + /* VEX_LEN_0F45_P_0 */ { - { VEX_W_TABLE (VEX_W_0F2E_P_0) }, - { VEX_W_TABLE (VEX_W_0F2E_P_0) }, - }, - - /* VEX_LEN_0F2E_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F2E_P_2) }, - { VEX_W_TABLE (VEX_W_0F2E_P_2) }, - }, - - /* VEX_LEN_0F2F_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F2F_P_0) }, - { VEX_W_TABLE (VEX_W_0F2F_P_0) }, - }, - - /* VEX_LEN_0F2F_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F2F_P_2) }, - { VEX_W_TABLE (VEX_W_0F2F_P_2) }, - }, - - /* VEX_LEN_0F41_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, - }, - /* VEX_LEN_0F41_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, - }, - /* VEX_LEN_0F42_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, - }, - /* VEX_LEN_0F42_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, - }, - /* VEX_LEN_0F44_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, - }, - /* VEX_LEN_0F44_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, - }, - /* VEX_LEN_0F45_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, }, /* VEX_LEN_0F45_P_2 */ { @@ -9725,130 +9424,25 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, }, - /* VEX_LEN_0F51_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F51_P_1) }, - { VEX_W_TABLE (VEX_W_0F51_P_1) }, - }, - - /* VEX_LEN_0F51_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F51_P_3) }, - { VEX_W_TABLE (VEX_W_0F51_P_3) }, - }, - - /* VEX_LEN_0F52_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F52_P_1) }, - { VEX_W_TABLE (VEX_W_0F52_P_1) }, - }, - - /* VEX_LEN_0F53_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F53_P_1) }, - { VEX_W_TABLE (VEX_W_0F53_P_1) }, - }, - - /* VEX_LEN_0F58_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F58_P_1) }, - { VEX_W_TABLE (VEX_W_0F58_P_1) }, - }, - - /* VEX_LEN_0F58_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F58_P_3) }, - { VEX_W_TABLE (VEX_W_0F58_P_3) }, - }, - - /* VEX_LEN_0F59_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F59_P_1) }, - { VEX_W_TABLE (VEX_W_0F59_P_1) }, - }, - - /* VEX_LEN_0F59_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F59_P_3) }, - { VEX_W_TABLE (VEX_W_0F59_P_3) }, - }, - - /* VEX_LEN_0F5A_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5A_P_1) }, - { VEX_W_TABLE (VEX_W_0F5A_P_1) }, - }, - - /* VEX_LEN_0F5A_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5A_P_3) }, - { VEX_W_TABLE (VEX_W_0F5A_P_3) }, - }, - - /* VEX_LEN_0F5C_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5C_P_1) }, - { VEX_W_TABLE (VEX_W_0F5C_P_1) }, - }, - - /* VEX_LEN_0F5C_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5C_P_3) }, - { VEX_W_TABLE (VEX_W_0F5C_P_3) }, - }, - - /* VEX_LEN_0F5D_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5D_P_1) }, - { VEX_W_TABLE (VEX_W_0F5D_P_1) }, - }, - - /* VEX_LEN_0F5D_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5D_P_3) }, - { VEX_W_TABLE (VEX_W_0F5D_P_3) }, - }, - - /* VEX_LEN_0F5E_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5E_P_1) }, - { VEX_W_TABLE (VEX_W_0F5E_P_1) }, - }, - - /* VEX_LEN_0F5E_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5E_P_3) }, - { VEX_W_TABLE (VEX_W_0F5E_P_3) }, - }, - - /* VEX_LEN_0F5F_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5F_P_1) }, - { VEX_W_TABLE (VEX_W_0F5F_P_1) }, - }, - - /* VEX_LEN_0F5F_P_3 */ + /* VEX_LEN_0F6E_P_2 */ { - { VEX_W_TABLE (VEX_W_0F5F_P_3) }, - { VEX_W_TABLE (VEX_W_0F5F_P_3) }, + { "vmovK", { XMScalar, Edq }, 0 }, }, - /* VEX_LEN_0F6E_P_2 */ + /* VEX_LEN_0F77_P_1 */ { - { "vmovK", { XMScalar, Edq }, 0 }, - { "vmovK", { XMScalar, Edq }, 0 }, + { "vzeroupper", { XX }, 0 }, + { "vzeroall", { XX }, 0 }, }, /* VEX_LEN_0F7E_P_1 */ { - { VEX_W_TABLE (VEX_W_0F7E_P_1) }, - { VEX_W_TABLE (VEX_W_0F7E_P_1) }, + { "vmovq", { XMScalar, EXqScalar }, 0 }, }, /* VEX_LEN_0F7E_P_2 */ { { "vmovK", { Edq, XMScalar }, 0 }, - { "vmovK", { Edq, XMScalar }, 0 }, }, /* VEX_LEN_0F90_P_0 */ @@ -9883,7 +9477,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F92_P_3 */ { - { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, }, /* VEX_LEN_0F93_P_0 */ @@ -9898,7 +9492,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F93_P_3 */ { - { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, }, /* VEX_LEN_0F98_P_0 */ @@ -9923,45 +9517,32 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0FAE_R_2_M_0 */ { - { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, + { "vldmxcsr", { Md }, 0 }, }, /* VEX_LEN_0FAE_R_3_M_0 */ { - { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, - }, - - /* VEX_LEN_0FC2_P_1 */ - { - { VEX_W_TABLE (VEX_W_0FC2_P_1) }, - { VEX_W_TABLE (VEX_W_0FC2_P_1) }, - }, - - /* VEX_LEN_0FC2_P_3 */ - { - { VEX_W_TABLE (VEX_W_0FC2_P_3) }, - { VEX_W_TABLE (VEX_W_0FC2_P_3) }, + { "vstmxcsr", { Md }, 0 }, }, /* VEX_LEN_0FC4_P_2 */ { - { VEX_W_TABLE (VEX_W_0FC4_P_2) }, + { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, }, /* VEX_LEN_0FC5_P_2 */ { - { VEX_W_TABLE (VEX_W_0FC5_P_2) }, + { "vpextrw", { Gdq, XS, Ib }, 0 }, }, /* VEX_LEN_0FD6_P_2 */ { - { VEX_W_TABLE (VEX_W_0FD6_P_2) }, - { VEX_W_TABLE (VEX_W_0FD6_P_2) }, + { "vmovq", { EXqScalarS, XMScalar }, 0 }, }, /* VEX_LEN_0FF7_P_2 */ { - { VEX_W_TABLE (VEX_W_0FF7_P_2) }, + { "vmaskmovdqu", { XM, XS }, 0 }, }, /* VEX_LEN_0F3816_P_2 */ @@ -9990,7 +9571,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3841_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3841_P_2) }, + { "vphminposuw", { XM, EXx }, 0 }, }, /* VEX_LEN_0F385A_P_2_M_0 */ @@ -10001,7 +9582,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F38DB_P_2 */ { - { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, + { "vaesimc", { XM, EXx }, 0 }, }, /* VEX_LEN_0F38F2_P_0 */ @@ -10082,26 +9663,14 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, }, - /* VEX_LEN_0F3A0A_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, - { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, - }, - - /* VEX_LEN_0F3A0B_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, - { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, - }, - /* VEX_LEN_0F3A14_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, + { "vpextrb", { Edqb, XM, Ib }, 0 }, }, /* VEX_LEN_0F3A15_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, + { "vpextrw", { Edqw, XM, Ib }, 0 }, }, /* VEX_LEN_0F3A16_P_2 */ @@ -10128,12 +9697,12 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A20_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, + { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, }, /* VEX_LEN_0F3A21_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, + { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, }, /* VEX_LEN_0F3A22_P_2 */ @@ -10175,7 +9744,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A41_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, + { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0F3A46_P_2 */ @@ -10196,12 +9765,12 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A62_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, + { "vpcmpistrm", { XM, EXx, Ib }, 0 }, }, /* VEX_LEN_0F3A63_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, + { "vpcmpistri", { XM, EXx, Ib }, 0 }, }, /* VEX_LEN_0F3A6A_P_2 */ @@ -10246,7 +9815,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3ADF_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, + { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, }, /* VEX_LEN_0F3AF0_P_3 */ @@ -10307,119 +9876,9 @@ static const struct dis386 vex_len_table[][2] = { }, }; +#include "i386-dis-evex-len.h" + static const struct dis386 vex_w_table[][2] = { - { - /* VEX_W_0F10_P_0 */ - { "vmovups", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F10_P_1 */ - { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F10_P_2 */ - { "vmovupd", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F10_P_3 */ - { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F11_P_0 */ - { "vmovups", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F11_P_1 */ - { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, - }, - { - /* VEX_W_0F11_P_2 */ - { "vmovupd", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F11_P_3 */ - { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, - }, - { - /* VEX_W_0F12_P_0_M_0 */ - { "vmovlps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_0_M_1 */ - { "vmovhlps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_1 */ - { "vmovsldup", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F12_P_2 */ - { "vmovlpd", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_3 */ - { "vmovddup", { XM, EXymmq }, 0 }, - }, - { - /* VEX_W_0F13_M_0 */ - { "vmovlpX", { EXq, XM }, 0 }, - }, - { - /* VEX_W_0F14 */ - { "vunpcklpX", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F15 */ - { "vunpckhpX", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F16_P_0_M_0 */ - { "vmovhps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F16_P_0_M_1 */ - { "vmovlhps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F16_P_1 */ - { "vmovshdup", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F16_P_2 */ - { "vmovhpd", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F17_M_0 */ - { "vmovhpX", { EXq, XM }, 0 }, - }, - { - /* VEX_W_0F28 */ - { "vmovapX", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F29 */ - { "vmovapX", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F2B_M_0 */ - { "vmovntpX", { Mx, XM }, 0 }, - }, - { - /* VEX_W_0F2E_P_0 */ - { "vucomiss", { XMScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F2E_P_2 */ - { "vucomisd", { XMScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F2F_P_0 */ - { "vcomiss", { XMScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F2F_P_2 */ - { "vcomisd", { XMScalar, EXqScalar }, 0 }, - }, { /* VEX_W_0F41_P_0_LEN_1 */ { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, @@ -10500,842 +9959,112 @@ static const struct dis386 vex_w_table[][2] = { { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, }, { - /* VEX_W_0F50_M_0 */ - { "vmovmskpX", { Gdq, XS }, 0 }, - }, - { - /* VEX_W_0F51_P_0 */ - { "vsqrtps", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F51_P_1 */ - { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F51_P_2 */ - { "vsqrtpd", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F51_P_3 */ - { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F52_P_0 */ - { "vrsqrtps", { XM, EXx }, 0 }, + /* VEX_W_0F90_P_0_LEN_0 */ + { "kmovw", { MaskG, MaskE }, 0 }, + { "kmovq", { MaskG, MaskE }, 0 }, }, { - /* VEX_W_0F52_P_1 */ - { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, + /* VEX_W_0F90_P_2_LEN_0 */ + { "kmovb", { MaskG, MaskBDE }, 0 }, + { "kmovd", { MaskG, MaskBDE }, 0 }, }, { - /* VEX_W_0F53_P_0 */ - { "vrcpps", { XM, EXx }, 0 }, + /* VEX_W_0F91_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, }, { - /* VEX_W_0F53_P_1 */ - { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, + /* VEX_W_0F91_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, }, { - /* VEX_W_0F58_P_0 */ - { "vaddps", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F92_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, }, { - /* VEX_W_0F58_P_1 */ - { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, + /* VEX_W_0F92_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, }, { - /* VEX_W_0F58_P_2 */ - { "vaddpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F58_P_3 */ - { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F59_P_0 */ - { "vmulps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F59_P_1 */ - { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F59_P_2 */ - { "vmulpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F59_P_3 */ - { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5A_P_0 */ - { "vcvtps2pd", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F5A_P_1 */ - { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5A_P_3 */ - { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5B_P_0 */ - { "vcvtdq2ps", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5B_P_1 */ - { "vcvttps2dq", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5B_P_2 */ - { "vcvtps2dq", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_0 */ - { "vsubps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_1 */ - { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5C_P_2 */ - { "vsubpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_3 */ - { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5D_P_0 */ - { "vminps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5D_P_1 */ - { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5D_P_2 */ - { "vminpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5D_P_3 */ - { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5E_P_0 */ - { "vdivps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5E_P_1 */ - { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5E_P_2 */ - { "vdivpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5E_P_3 */ - { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5F_P_0 */ - { "vmaxps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5F_P_1 */ - { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5F_P_2 */ - { "vmaxpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5F_P_3 */ - { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F60_P_2 */ - { "vpunpcklbw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F61_P_2 */ - { "vpunpcklwd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F62_P_2 */ - { "vpunpckldq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F63_P_2 */ - { "vpacksswb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F64_P_2 */ - { "vpcmpgtb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F65_P_2 */ - { "vpcmpgtw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F66_P_2 */ - { "vpcmpgtd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F67_P_2 */ - { "vpackuswb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F68_P_2 */ - { "vpunpckhbw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F69_P_2 */ - { "vpunpckhwd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6A_P_2 */ - { "vpunpckhdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6B_P_2 */ - { "vpackssdw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6C_P_2 */ - { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6D_P_2 */ - { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6F_P_1 */ - { "vmovdqu", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F6F_P_2 */ - { "vmovdqa", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F70_P_1 */ - { "vpshufhw", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F70_P_2 */ - { "vpshufd", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F70_P_3 */ - { "vpshuflw", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_2_P_2 */ - { "vpsrlw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_4_P_2 */ - { "vpsraw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_6_P_2 */ - { "vpsllw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_2_P_2 */ - { "vpsrld", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_4_P_2 */ - { "vpsrad", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_6_P_2 */ - { "vpslld", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_2_P_2 */ - { "vpsrlq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_3_P_2 */ - { "vpsrldq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_6_P_2 */ - { "vpsllq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_7_P_2 */ - { "vpslldq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F74_P_2 */ - { "vpcmpeqb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F75_P_2 */ - { "vpcmpeqw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F76_P_2 */ - { "vpcmpeqd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F77_P_0 */ - { "", { VZERO }, 0 }, - }, - { - /* VEX_W_0F7C_P_2 */ - { "vhaddpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7C_P_3 */ - { "vhaddps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7D_P_2 */ - { "vhsubpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7D_P_3 */ - { "vhsubps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7E_P_1 */ - { "vmovq", { XMScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F7F_P_1 */ - { "vmovdqu", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F7F_P_2 */ - { "vmovdqa", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F90_P_0_LEN_0 */ - { "kmovw", { MaskG, MaskE }, 0 }, - { "kmovq", { MaskG, MaskE }, 0 }, - }, - { - /* VEX_W_0F90_P_2_LEN_0 */ - { "kmovb", { MaskG, MaskBDE }, 0 }, - { "kmovd", { MaskG, MaskBDE }, 0 }, - }, - { - /* VEX_W_0F91_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, - }, - { - /* VEX_W_0F91_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, - }, - { - /* VEX_W_0F92_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, - }, - { - /* VEX_W_0F92_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, - }, - { - /* VEX_W_0F92_P_3_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, - }, - { - /* VEX_W_0F93_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, + /* VEX_W_0F93_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, }, { /* VEX_W_0F93_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, - }, - { - /* VEX_W_0F93_P_3_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, - }, - { - /* VEX_W_0F98_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, - }, - { - /* VEX_W_0F98_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, - }, - { - /* VEX_W_0F99_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, - }, - { - /* VEX_W_0F99_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, - }, - { - /* VEX_W_0FAE_R_2_M_0 */ - { "vldmxcsr", { Md }, 0 }, - }, - { - /* VEX_W_0FAE_R_3_M_0 */ - { "vstmxcsr", { Md }, 0 }, - }, - { - /* VEX_W_0FC2_P_0 */ - { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, - }, - { - /* VEX_W_0FC2_P_1 */ - { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, - }, - { - /* VEX_W_0FC2_P_2 */ - { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, - }, - { - /* VEX_W_0FC2_P_3 */ - { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, - }, - { - /* VEX_W_0FC4_P_2 */ - { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, - }, - { - /* VEX_W_0FC5_P_2 */ - { "vpextrw", { Gdq, XS, Ib }, 0 }, - }, - { - /* VEX_W_0FD0_P_2 */ - { "vaddsubpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD0_P_3 */ - { "vaddsubps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD1_P_2 */ - { "vpsrlw", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FD2_P_2 */ - { "vpsrld", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FD3_P_2 */ - { "vpsrlq", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FD4_P_2 */ - { "vpaddq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD5_P_2 */ - { "vpmullw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD6_P_2 */ - { "vmovq", { EXqScalarS, XMScalar }, 0 }, - }, - { - /* VEX_W_0FD7_P_2_M_1 */ - { "vpmovmskb", { Gdq, XS }, 0 }, - }, - { - /* VEX_W_0FD8_P_2 */ - { "vpsubusb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD9_P_2 */ - { "vpsubusw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDA_P_2 */ - { "vpminub", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDB_P_2 */ - { "vpand", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDC_P_2 */ - { "vpaddusb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDD_P_2 */ - { "vpaddusw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDE_P_2 */ - { "vpmaxub", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDF_P_2 */ - { "vpandn", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE0_P_2 */ - { "vpavgb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE1_P_2 */ - { "vpsraw", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FE2_P_2 */ - { "vpsrad", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FE3_P_2 */ - { "vpavgw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE4_P_2 */ - { "vpmulhuw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE5_P_2 */ - { "vpmulhw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE6_P_1 */ - { "vcvtdq2pd", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0FE6_P_2 */ - { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, - }, - { - /* VEX_W_0FE6_P_3 */ - { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, - }, - { - /* VEX_W_0FE7_P_2_M_0 */ - { "vmovntdq", { Mx, XM }, 0 }, - }, - { - /* VEX_W_0FE8_P_2 */ - { "vpsubsb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE9_P_2 */ - { "vpsubsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEA_P_2 */ - { "vpminsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEB_P_2 */ - { "vpor", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEC_P_2 */ - { "vpaddsb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FED_P_2 */ - { "vpaddsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEE_P_2 */ - { "vpmaxsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEF_P_2 */ - { "vpxor", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF0_P_3_M_0 */ - { "vlddqu", { XM, M }, 0 }, - }, - { - /* VEX_W_0FF1_P_2 */ - { "vpsllw", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FF2_P_2 */ - { "vpslld", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FF3_P_2 */ - { "vpsllq", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FF4_P_2 */ - { "vpmuludq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF5_P_2 */ - { "vpmaddwd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF6_P_2 */ - { "vpsadbw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF7_P_2 */ - { "vmaskmovdqu", { XM, XS }, 0 }, - }, - { - /* VEX_W_0FF8_P_2 */ - { "vpsubb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF9_P_2 */ - { "vpsubw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFA_P_2 */ - { "vpsubd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFB_P_2 */ - { "vpsubq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFC_P_2 */ - { "vpaddb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFD_P_2 */ - { "vpaddw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFE_P_2 */ - { "vpaddd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3800_P_2 */ - { "vpshufb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3801_P_2 */ - { "vphaddw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3802_P_2 */ - { "vphaddd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3803_P_2 */ - { "vphaddsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3804_P_2 */ - { "vpmaddubsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3805_P_2 */ - { "vphsubw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3806_P_2 */ - { "vphsubd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3807_P_2 */ - { "vphsubsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3808_P_2 */ - { "vpsignb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3809_P_2 */ - { "vpsignw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F380A_P_2 */ - { "vpsignd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F380B_P_2 */ - { "vpmulhrsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F380C_P_2 */ - { "vpermilps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F380D_P_2 */ - { "vpermilpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F380E_P_2 */ - { "vtestps", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F380F_P_2 */ - { "vtestpd", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F3816_P_2 */ - { "vpermps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3817_P_2 */ - { "vptest", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F3818_P_2 */ - { "vbroadcastss", { XM, EXxmm_md }, 0 }, - }, - { - /* VEX_W_0F3819_P_2 */ - { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, - }, - { - /* VEX_W_0F381A_P_2_M_0 */ - { "vbroadcastf128", { XM, Mxmm }, 0 }, - }, - { - /* VEX_W_0F381C_P_2 */ - { "vpabsb", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F381D_P_2 */ - { "vpabsw", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F381E_P_2 */ - { "vpabsd", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F3820_P_2 */ - { "vpmovsxbw", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F3821_P_2 */ - { "vpmovsxbd", { XM, EXxmmqd }, 0 }, - }, - { - /* VEX_W_0F3822_P_2 */ - { "vpmovsxbq", { XM, EXxmmdw }, 0 }, - }, - { - /* VEX_W_0F3823_P_2 */ - { "vpmovsxwd", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F3824_P_2 */ - { "vpmovsxwq", { XM, EXxmmqd }, 0 }, - }, - { - /* VEX_W_0F3825_P_2 */ - { "vpmovsxdq", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F3828_P_2 */ - { "vpmuldq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3829_P_2 */ - { "vpcmpeqq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F382A_P_2_M_0 */ - { "vmovntdqa", { XM, Mx }, 0 }, - }, - { - /* VEX_W_0F382B_P_2 */ - { "vpackusdw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F382C_P_2_M_0 */ - { "vmaskmovps", { XM, Vex, Mx }, 0 }, - }, - { - /* VEX_W_0F382D_P_2_M_0 */ - { "vmaskmovpd", { XM, Vex, Mx }, 0 }, - }, - { - /* VEX_W_0F382E_P_2_M_0 */ - { "vmaskmovps", { Mx, Vex, XM }, 0 }, - }, - { - /* VEX_W_0F382F_P_2_M_0 */ - { "vmaskmovpd", { Mx, Vex, XM }, 0 }, - }, - { - /* VEX_W_0F3830_P_2 */ - { "vpmovzxbw", { XM, EXxmmq }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, }, { - /* VEX_W_0F3831_P_2 */ - { "vpmovzxbd", { XM, EXxmmqd }, 0 }, + /* VEX_W_0F98_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, }, { - /* VEX_W_0F3832_P_2 */ - { "vpmovzxbq", { XM, EXxmmdw }, 0 }, + /* VEX_W_0F98_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, }, { - /* VEX_W_0F3833_P_2 */ - { "vpmovzxwd", { XM, EXxmmq }, 0 }, + /* VEX_W_0F99_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, }, { - /* VEX_W_0F3834_P_2 */ - { "vpmovzxwq", { XM, EXxmmqd }, 0 }, + /* VEX_W_0F99_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, }, { - /* VEX_W_0F3835_P_2 */ - { "vpmovzxdq", { XM, EXxmmq }, 0 }, + /* VEX_W_0F380C_P_2 */ + { "vpermilps", { XM, Vex, EXx }, 0 }, }, { - /* VEX_W_0F3836_P_2 */ - { "vpermd", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F380D_P_2 */ + { "vpermilpd", { XM, Vex, EXx }, 0 }, }, { - /* VEX_W_0F3837_P_2 */ - { "vpcmpgtq", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F380E_P_2 */ + { "vtestps", { XM, EXx }, 0 }, }, { - /* VEX_W_0F3838_P_2 */ - { "vpminsb", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F380F_P_2 */ + { "vtestpd", { XM, EXx }, 0 }, }, { - /* VEX_W_0F3839_P_2 */ - { "vpminsd", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F3816_P_2 */ + { "vpermps", { XM, Vex, EXx }, 0 }, }, { - /* VEX_W_0F383A_P_2 */ - { "vpminuw", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F3818_P_2 */ + { "vbroadcastss", { XM, EXxmm_md }, 0 }, }, { - /* VEX_W_0F383B_P_2 */ - { "vpminud", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F3819_P_2 */ + { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, }, { - /* VEX_W_0F383C_P_2 */ - { "vpmaxsb", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F381A_P_2_M_0 */ + { "vbroadcastf128", { XM, Mxmm }, 0 }, }, { - /* VEX_W_0F383D_P_2 */ - { "vpmaxsd", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F382C_P_2_M_0 */ + { "vmaskmovps", { XM, Vex, Mx }, 0 }, }, { - /* VEX_W_0F383E_P_2 */ - { "vpmaxuw", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F382D_P_2_M_0 */ + { "vmaskmovpd", { XM, Vex, Mx }, 0 }, }, { - /* VEX_W_0F383F_P_2 */ - { "vpmaxud", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F382E_P_2_M_0 */ + { "vmaskmovps", { Mx, Vex, XM }, 0 }, }, { - /* VEX_W_0F3840_P_2 */ - { "vpmulld", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F382F_P_2_M_0 */ + { "vmaskmovpd", { Mx, Vex, XM }, 0 }, }, { - /* VEX_W_0F3841_P_2 */ - { "vphminposuw", { XM, EXx }, 0 }, + /* VEX_W_0F3836_P_2 */ + { "vpermd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3846_P_2 */ @@ -11365,10 +10094,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F38CF_P_2 */ { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, }, - { - /* VEX_W_0F38DB_P_2 */ - { "vaesimc", { XM, EXx }, 0 }, - }, { /* VEX_W_0F3A00_P_2 */ { Bad_Opcode }, @@ -11395,46 +10120,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A06_P_2 */ { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, }, - { - /* VEX_W_0F3A08_P_2 */ - { "vroundps", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A09_P_2 */ - { "vroundpd", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0A_P_2 */ - { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0B_P_2 */ - { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0C_P_2 */ - { "vblendps", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0D_P_2 */ - { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0E_P_2 */ - { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0F_P_2 */ - { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A14_P_2 */ - { "vpextrb", { Edqb, XM, Ib }, 0 }, - }, - { - /* VEX_W_0F3A15_P_2 */ - { "vpextrw", { Edqw, XM, Ib }, 0 }, - }, { /* VEX_W_0F3A18_P_2 */ { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, @@ -11443,14 +10128,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A19_P_2 */ { "vextractf128", { EXxmm, XM, Ib }, 0 }, }, - { - /* VEX_W_0F3A20_P_2 */ - { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, - }, - { - /* VEX_W_0F3A21_P_2 */ - { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, - }, { /* VEX_W_0F3A30_P_2_LEN_0 */ { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, @@ -11479,18 +10156,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A39_P_2 */ { "vextracti128", { EXxmm, XM, Ib }, 0 }, }, - { - /* VEX_W_0F3A40_P_2 */ - { "vdpps", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A41_P_2 */ - { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A42_P_2 */ - { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, - }, { /* VEX_W_0F3A46_P_2 */ { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, @@ -11517,14 +10182,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A4C_P_2 */ { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, }, - { - /* VEX_W_0F3A62_P_2 */ - { "vpcmpistrm", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A63_P_2 */ - { "vpcmpistri", { XM, EXx, Ib }, 0 }, - }, { /* VEX_W_0F3ACE_P_2 */ { Bad_Opcode }, @@ -11535,13 +10192,8 @@ static const struct dis386 vex_w_table[][2] = { { Bad_Opcode }, { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, }, - { - /* VEX_W_0F3ADF_P_2 */ - { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, - }, -#define NEED_VEX_W_TABLE -#include "i386-dis-evex.h" -#undef NEED_VEX_W_TABLE + +#include "i386-dis-evex-w.h" }; static const struct dis386 mod_table[][2] = { @@ -11589,13 +10241,13 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F01_REG_5 */ - { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, - { RM_TABLE (RM_0F01_REG_5) }, + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, + { RM_TABLE (RM_0F01_REG_5_MOD_3) }, }, { /* MOD_0F01_REG_7 */ { "invlpg", { Mb }, 0 }, - { RM_TABLE (RM_0F01_REG_7) }, + { RM_TABLE (RM_0F01_REG_7_MOD_3) }, }, { /* MOD_0F12_PREFIX_0 */ @@ -11664,13 +10316,13 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F1C_PREFIX_0 */ - { REG_TABLE (REG_0F1C_MOD_0) }, + { REG_TABLE (REG_0F1C_P_0_MOD_0) }, { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1E_PREFIX_1 */ { "nopQ", { Ev }, 0 }, - { REG_TABLE (REG_0F1E_MOD_3) }, + { REG_TABLE (REG_0F1E_P_1_MOD_3) }, }, { /* MOD_0F24 */ @@ -11756,42 +10408,42 @@ static const struct dis386 mod_table[][2] = { { /* MOD_0FAE_REG_0 */ { "fxsave", { FXSAVE }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, }, { /* MOD_0FAE_REG_1 */ { "fxrstor", { FXSAVE }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, }, { /* MOD_0FAE_REG_2 */ { "ldmxcsr", { Md }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, }, { /* MOD_0FAE_REG_3 */ { "stmxcsr", { Md }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, }, { /* MOD_0FAE_REG_4 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, - { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, }, { /* MOD_0FAE_REG_5 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, - { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, }, { /* MOD_0FAE_REG_6 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) }, - { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, }, { /* MOD_0FAE_REG_7 */ - { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, - { RM_TABLE (RM_0FAE_REG_7) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, + { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, }, { /* MOD_0FB2 */ @@ -11807,7 +10459,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FC3 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, + { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, }, { /* MOD_0FC7_REG_3 */ @@ -11823,13 +10475,13 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FC7_REG_6 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, - { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } + { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } }, { /* MOD_0FC7_REG_7 */ { "vmptrst", { Mq }, 0 }, - { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } + { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } }, { /* MOD_0FD7 */ @@ -11856,13 +10508,21 @@ static const struct dis386 mod_table[][2] = { /* MOD_0F38F6_PREFIX_0 */ { "wrssK", { M, Gdq }, PREFIX_OPCODE }, }, + { + /* MOD_0F38F8_PREFIX_1 */ + { "enqcmds", { Gva, M }, PREFIX_OPCODE }, + }, { /* MOD_0F38F8_PREFIX_2 */ { "movdir64b", { Gva, M }, PREFIX_OPCODE }, }, + { + /* MOD_0F38F8_PREFIX_3 */ + { "enqcmd", { Gva, M }, PREFIX_OPCODE }, + }, { /* MOD_0F38F9_PREFIX_0 */ - { "movdiri", { Em, Gv }, PREFIX_OPCODE }, + { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, }, { /* MOD_62_32BIT */ @@ -11899,7 +10559,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_VEX_0F2B */ - { VEX_W_TABLE (VEX_W_0F2B_M_0) }, + { "vmovntpX", { Mx, XM }, 0 }, }, { /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ @@ -12059,7 +10719,7 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_0F50 */ { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F50_M_0) }, + { "vmovmskpX", { Gdq, XS }, 0 }, }, { /* MOD_VEX_0F71_REG_2 */ @@ -12142,14 +10802,9 @@ static const struct dis386 mod_table[][2] = { { "kmovb", { MaskG, Rdq }, 0 }, }, { - /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ - { Bad_Opcode }, - { "kmovd", { MaskG, Rdq }, 0 }, - }, - { - /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ + /* MOD_VEX_0F92_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovq", { MaskG, Rdq }, 0 }, + { "kmovK", { MaskG, Rdq }, 0 }, }, { /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ @@ -12162,14 +10817,9 @@ static const struct dis386 mod_table[][2] = { { "kmovb", { Gdq, MaskR }, 0 }, }, { - /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ - { Bad_Opcode }, - { "kmovd", { Gdq, MaskR }, 0 }, - }, - { - /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ + /* MOD_VEX_0F93_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovq", { Gdq, MaskR }, 0 }, + { "kmovK", { Gdq, MaskR }, 0 }, }, { /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ @@ -12222,15 +10872,15 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_0FD7_PREFIX_2 */ { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, + { "vpmovmskb", { Gdq, XS }, 0 }, }, { /* MOD_VEX_0FE7_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, + { "vmovntdq", { Mx, XM }, 0 }, }, { /* MOD_VEX_0FF0_PREFIX_3 */ - { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, + { "vlddqu", { XM, M }, 0 }, }, { /* MOD_VEX_0F381A_PREFIX_2 */ @@ -12238,7 +10888,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_VEX_0F382A_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, + { "vmovntdqa", { XM, Mx }, 0 }, }, { /* MOD_VEX_0F382C_PREFIX_2 */ @@ -12308,9 +10958,8 @@ static const struct dis386 mod_table[][2] = { { Bad_Opcode }, { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, }, -#define NEED_MOD_TABLE -#include "i386-dis-evex.h" -#undef NEED_MOD_TABLE + +#include "i386-dis-evex-mod.h" }; static const struct dis386 rm_table[][8] = { @@ -12324,7 +10973,7 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_0F01_REG_0 */ - { Bad_Opcode }, + { "enclv", { Skip_MODRM }, 0 }, { "vmcall", { Skip_MODRM }, 0 }, { "vmlaunch", { Skip_MODRM }, 0 }, { "vmresume", { Skip_MODRM }, 0 }, @@ -12365,10 +11014,10 @@ static const struct dis386 rm_table[][8] = { { "invlpga", { Skip_MODRM }, 0 }, }, { - /* RM_0F01_REG_5 */ - { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, + /* RM_0F01_REG_5_MOD_3 */ + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -12376,15 +11025,16 @@ static const struct dis386 rm_table[][8] = { { "wrpkru", { Skip_MODRM }, 0 }, }, { - /* RM_0F01_REG_7 */ + /* RM_0F01_REG_7_MOD_3 */ { "swapgs", { Skip_MODRM }, 0 }, { "rdtscp", { Skip_MODRM }, 0 }, - { "monitorx", { { OP_Monitor, 0 } }, 0 }, - { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, { "clzero", { Skip_MODRM }, 0 }, + { "rdpru", { Skip_MODRM }, 0 }, }, { - /* RM_0F1E_MOD_3_REG_7 */ + /* RM_0F1E_P_1_MOD_3_REG_7 */ { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, @@ -12395,11 +11045,11 @@ static const struct dis386 rm_table[][8] = { { "nopQ", { Ev }, 0 }, }, { - /* RM_0FAE_REG_6 */ + /* RM_0FAE_REG_6_MOD_3 */ { "mfence", { Skip_MODRM }, 0 }, }, { - /* RM_0FAE_REG_7 */ + /* RM_0FAE_REG_7_MOD_3 */ { "sfence", { Skip_MODRM }, 0 }, }, @@ -12855,6 +11505,29 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) dp = &vex_len_table[dp->op[1].bytemode][vindex]; break; + case USE_EVEX_LEN_TABLE: + if (!vex.evex) + abort (); + + switch (vex.length) + { + case 128: + vindex = 0; + break; + case 256: + vindex = 1; + break; + case 512: + vindex = 2; + break; + default: + abort (); + break; + } + + dp = &evex_len_table[dp->op[1].bytemode][vindex]; + break; + case USE_XOP_8F_TABLE: FETCH_DATA (info, codep + 3); /* All bits in the REX prefix are ignored. */ @@ -13466,6 +12139,14 @@ print_insn (bfd_vma pc, disassemble_info *info) } } + /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which + are all 0s in inverted form. */ + if (need_vex && vex.register_specifier != 0) + { + (*info->fprintf_func) (info->stream, "(bad)"); + return end_codep - priv.the_buffer; + } + /* Check if the REX prefix is used. */ if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) all_prefixes[last_rex_prefix] = 0; @@ -15239,6 +13920,13 @@ OP_E_memory (int bytemode, int sizeflag) case db_mode: shift = 0; break; + case dq_mode: + if (address_mode != mode_64bit) + { + shift = 2; + break; + } + /* fall through */ case vex_vsib_d_w_dq_mode: case vex_vsib_d_w_d_mode: case vex_vsib_q_w_dq_mode: @@ -15484,7 +14172,7 @@ OP_E_memory (int bytemode, int sizeflag) } } - if ((havebase || haveindex || needaddr32 || riprel) + if ((havebase || haveindex || needindex || needaddr32 || riprel) && (bytemode != v_bnd_mode) && (bytemode != v_bndmk_mode) && (bytemode != bnd_mode) @@ -16010,13 +14698,6 @@ OP_I (int bytemode, int sizeflag) op = *codep++; mask = 0xff; break; - case q_mode: - if (address_mode == mode_64bit) - { - op = get32s (); - break; - } - /* Fall through. */ case v_mode: USED_REX (REX_W); if (rex & REX_W) @@ -16036,6 +14717,10 @@ OP_I (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case d_mode: + mask = 0xffffffff; + op = get32 (); + break; case w_mode: mask = 0xfffff; op = get16 (); @@ -16059,53 +14744,16 @@ OP_I (int bytemode, int sizeflag) static void OP_I64 (int bytemode, int sizeflag) { - bfd_signed_vma op; - bfd_signed_vma mask = -1; - - if (address_mode != mode_64bit) + if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) { OP_I (bytemode, sizeflag); return; } - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - mask = 0xff; - break; - case v_mode: - USED_REX (REX_W); - if (rex & REX_W) - op = get64 (); - else - { - if (sizeflag & DFLAG) - { - op = get32 (); - mask = 0xffffffff; - } - else - { - op = get16 (); - mask = 0xfffff; - } - used_prefixes |= (prefixes & PREFIX_DATA); - } - break; - case w_mode: - mask = 0xfffff; - op = get16 (); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } + USED_REX (REX_W); - op &= mask; scratchbuf[0] = '$'; - print_operand_value (scratchbuf + 1, 1, op); + print_operand_value (scratchbuf + 1, 1, get64 ()); oappend_maybe_intel (scratchbuf); scratchbuf[0] = '\0'; } @@ -16869,35 +15517,15 @@ CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) } static void -OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - /* mwaitx %eax,%ecx,%ebx */ - if (!intel_syntax) - { - const char **names = (address_mode == mode_64bit - ? names64 : names32); - strcpy (op_out[0], names[0]); - strcpy (op_out[1], names[1]); - strcpy (op_out[2], names[3]); - two_source_ops = 1; - } - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; -} - -static void -OP_Mwait (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) +OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { - /* mwait %eax,%ecx */ + /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ if (!intel_syntax) { - const char **names = (address_mode == mode_64bit - ? names64 : names32); - strcpy (op_out[0], names[0]); - strcpy (op_out[1], names[1]); + strcpy (op_out[0], names32[0]); + strcpy (op_out[1], names32[1]); + if (bytemode == eBX_reg) + strcpy (op_out[2], names32[3]); two_source_ops = 1; } /* Skip mod/rm byte. */ @@ -16909,27 +15537,25 @@ static void OP_Monitor (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { - /* monitor %eax,%ecx,%edx" */ + /* monitor %{e,r,}ax,%ecx,%edx" */ if (!intel_syntax) { - const char **op1_names; const char **names = (address_mode == mode_64bit ? names64 : names32); - if (!(prefixes & PREFIX_ADDR)) - op1_names = (address_mode == mode_16bit - ? names16 : names); - else + if (prefixes & PREFIX_ADDR) { /* Remove "addr16/addr32". */ all_prefixes[last_addr_prefix] = 0; - op1_names = (address_mode != mode_32bit - ? names32 : names16); + names = (address_mode != mode_32bit + ? names32 : names16); used_prefixes |= PREFIX_ADDR; } - strcpy (op_out[0], op1_names[0]); - strcpy (op_out[1], names[1]); - strcpy (op_out[2], names[2]); + else if (address_mode == mode_16bit) + names = names16; + strcpy (op_out[0], names[0]); + strcpy (op_out[1], names32[1]); + strcpy (op_out[2], names32[2]); two_source_ops = 1; } /* Skip mod/rm byte. */ @@ -17220,6 +15846,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) return; reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; else if (vex.evex && !vex.v) @@ -17503,6 +16130,7 @@ OP_Vex_2src_1 (int bytemode, int sizeflag) if (vex.w) { unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; @@ -17520,6 +16148,7 @@ OP_Vex_2src_2 (int bytemode, int sizeflag) else { unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; @@ -17597,11 +16226,7 @@ static void OP_EX_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) - { - if (vex.register_specifier != 0) - BadOp (); - need_vex_reg = 0; - } + need_vex_reg = 0; OP_EX (bytemode, sizeflag); } @@ -17609,30 +16234,10 @@ static void OP_XMM_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) - { - if (vex.register_specifier != 0) - BadOp (); - need_vex_reg = 0; - } + need_vex_reg = 0; OP_XMM (bytemode, sizeflag); } -static void -VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - switch (vex.length) - { - case 128: - mnemonicendp = stpcpy (obuf, "vzeroupper"); - break; - case 256: - mnemonicendp = stpcpy (obuf, "vzeroall"); - break; - default: - abort (); - } -} - static struct op vex_cmp_op[] = { { STRING_COMMA_LEN ("eq") }, @@ -17909,6 +16514,7 @@ OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { const char **names; unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (rex & REX_W) names = names64; @@ -17942,11 +16548,19 @@ OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { if (!vex.evex || (bytemode != evex_rounding_mode + && bytemode != evex_rounding_64_mode && bytemode != evex_sae_mode)) abort (); if (modrm.mod == 3 && vex.b) switch (bytemode) { + case evex_rounding_64_mode: + if (address_mode != mode_64bit) + { + oappend ("(bad)"); + break; + } + /* Fall through. */ case evex_rounding_mode: oappend (names_rounding[vex.ll]); break;