X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fi386-dis.c;h=ae18cf2dee03f31883bf064c56d6e5a4465cb195;hb=99ba51255402201c6e193d803ee1f1fc3f2de0e6;hp=828dc2415df6683a99f761519470cfbfabf4fda4;hpb=4b95cf5c0c75d6efc1b2f96af72317aecca079f1;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 828dc2415d..ae18cf2dee 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,5 +1,5 @@ /* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988-2014 Free Software Foundation, Inc. + Copyright (C) 1988-2015 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -102,6 +102,7 @@ static void VPCMP_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); +static void OP_Mwaitx (int, int); static void NOP_Fixup1 (int, int); static void NOP_Fixup2 (int, int); static void OP_3DNowSuffix (int, int); @@ -131,7 +132,7 @@ struct dis_private { bfd_byte the_buffer[MAX_MNEM_SIZE]; bfd_vma insn_start; int orig_sizeflag; - jmp_buf bailout; + OPCODES_SIGJMP_BUF bailout; }; enum address_mode @@ -214,15 +215,33 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) STATUS. */ if (priv->max_fetched == priv->the_buffer) (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); + OPCODES_SIGLONGJMP (priv->bailout, 1); } else priv->max_fetched = addr; return 1; } +/* Possible values for prefix requirement. */ +#define PREFIX_IGNORED_SHIFT 16 +#define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) +#define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) +#define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) +#define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) +#define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) + +/* Opcode prefixes. */ +#define PREFIX_OPCODE (PREFIX_REPZ \ + | PREFIX_REPNZ \ + | PREFIX_DATA) + +/* Prefixes ignored. */ +#define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ + | PREFIX_IGNORED_REPNZ \ + | PREFIX_IGNORED_DATA) + #define XX { NULL, 0 } -#define Bad_Opcode NULL, { { NULL, 0 } } +#define Bad_Opcode NULL, { { NULL, 0 } }, 0 #define Eb { OP_E, b_mode } #define Ebnd { OP_E, bnd_mode } @@ -233,7 +252,10 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Ed { OP_E, d_mode } #define Edq { OP_E, dq_mode } #define Edqw { OP_E, dqw_mode } +#define EdqwS { OP_E, dqw_swap_mode } #define Edqb { OP_E, dqb_mode } +#define Edb { OP_E, db_mode } +#define Edw { OP_E, dw_mode } #define Edqd { OP_E, dqd_mode } #define Eq { OP_E, q_mode } #define indirEv { OP_indirE, stack_v_mode } @@ -423,11 +445,14 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define XMask { OP_Mask, mask_mode } #define MaskG { OP_G, mask_mode } #define MaskE { OP_E, mask_mode } +#define MaskBDE { OP_E, mask_bd_mode } #define MaskR { OP_R, mask_mode } #define MaskVex { OP_VEX, mask_mode } #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } +#define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } +#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } /* Used handle "rep" prefix for string instructions. */ #define Xbr { REP_Fixup, eSI_reg } @@ -531,6 +556,7 @@ enum dq_mode, /* registers like dq_mode, memory like w_mode. */ dqw_mode, + dqw_swap_mode, bnd_mode, /* 4- or 6-byte pointer operand */ f_mode, @@ -543,6 +569,10 @@ enum o_mode, /* registers like dq_mode, memory like b_mode. */ dqb_mode, + /* registers like d_mode, memory like b_mode. */ + db_mode, + /* registers like d_mode, memory like w_mode. */ + dw_mode, /* registers like dq_mode, memory like d_mode. */ dqd_mode, /* normal vex mode */ @@ -556,8 +586,12 @@ enum /* Similar to vex_w_dq_mode, with VSIB dword indices. */ vex_vsib_d_w_dq_mode, + /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ + vex_vsib_d_w_d_mode, /* Similar to vex_w_dq_mode, with VSIB qword indices. */ vex_vsib_q_w_dq_mode, + /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ + vex_vsib_q_w_d_mode, /* scalar, ignore vector length. */ scalar_mode, @@ -581,6 +615,8 @@ enum /* Mask register operand. */ mask_mode, + /* Mask register operand. */ + mask_bd_mode, es_reg, cs_reg, @@ -646,15 +682,17 @@ enum USE_EVEX_TABLE }; -#define FLOAT NULL, { { NULL, FLOATCODE } } +#define FLOAT NULL, { { NULL, FLOATCODE } }, 0 -#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } } +#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 +#define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) +#define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) @@ -702,6 +740,7 @@ enum REG_XOP_TBM_01, REG_XOP_TBM_02, + REG_EVEX_0F71, REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, @@ -735,10 +774,6 @@ enum MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0, MOD_0F1B_PREFIX_1, - MOD_0F20, - MOD_0F21, - MOD_0F22, - MOD_0F23, MOD_0F24, MOD_0F26, MOD_0F2B_PREFIX_0, @@ -767,6 +802,7 @@ enum MOD_0FB2, MOD_0FB4, MOD_0FB5, + MOD_0FC3, MOD_0FC7_REG_3, MOD_0FC7_REG_4, MOD_0FC7_REG_5, @@ -784,6 +820,37 @@ enum MOD_VEX_0F16_PREFIX_0, MOD_VEX_0F17, MOD_VEX_0F2B, + MOD_VEX_W_0_0F41_P_0_LEN_1, + MOD_VEX_W_1_0F41_P_0_LEN_1, + MOD_VEX_W_0_0F41_P_2_LEN_1, + MOD_VEX_W_1_0F41_P_2_LEN_1, + MOD_VEX_W_0_0F42_P_0_LEN_1, + MOD_VEX_W_1_0F42_P_0_LEN_1, + MOD_VEX_W_0_0F42_P_2_LEN_1, + MOD_VEX_W_1_0F42_P_2_LEN_1, + MOD_VEX_W_0_0F44_P_0_LEN_1, + MOD_VEX_W_1_0F44_P_0_LEN_1, + MOD_VEX_W_0_0F44_P_2_LEN_1, + MOD_VEX_W_1_0F44_P_2_LEN_1, + MOD_VEX_W_0_0F45_P_0_LEN_1, + MOD_VEX_W_1_0F45_P_0_LEN_1, + MOD_VEX_W_0_0F45_P_2_LEN_1, + MOD_VEX_W_1_0F45_P_2_LEN_1, + MOD_VEX_W_0_0F46_P_0_LEN_1, + MOD_VEX_W_1_0F46_P_0_LEN_1, + MOD_VEX_W_0_0F46_P_2_LEN_1, + MOD_VEX_W_1_0F46_P_2_LEN_1, + MOD_VEX_W_0_0F47_P_0_LEN_1, + MOD_VEX_W_1_0F47_P_0_LEN_1, + MOD_VEX_W_0_0F47_P_2_LEN_1, + MOD_VEX_W_1_0F47_P_2_LEN_1, + MOD_VEX_W_0_0F4A_P_0_LEN_1, + MOD_VEX_W_1_0F4A_P_0_LEN_1, + MOD_VEX_W_0_0F4A_P_2_LEN_1, + MOD_VEX_W_1_0F4A_P_2_LEN_1, + MOD_VEX_W_0_0F4B_P_0_LEN_1, + MOD_VEX_W_1_0F4B_P_0_LEN_1, + MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_0F50, MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, @@ -795,6 +862,26 @@ enum MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6, MOD_VEX_0F73_REG_7, + MOD_VEX_W_0_0F91_P_0_LEN_0, + MOD_VEX_W_1_0F91_P_0_LEN_0, + MOD_VEX_W_0_0F91_P_2_LEN_0, + MOD_VEX_W_1_0F91_P_2_LEN_0, + MOD_VEX_W_0_0F92_P_0_LEN_0, + MOD_VEX_W_0_0F92_P_2_LEN_0, + MOD_VEX_W_0_0F92_P_3_LEN_0, + MOD_VEX_W_1_0F92_P_3_LEN_0, + MOD_VEX_W_0_0F93_P_0_LEN_0, + MOD_VEX_W_0_0F93_P_2_LEN_0, + MOD_VEX_W_0_0F93_P_3_LEN_0, + MOD_VEX_W_1_0F93_P_3_LEN_0, + MOD_VEX_W_0_0F98_P_0_LEN_0, + MOD_VEX_W_1_0F98_P_0_LEN_0, + MOD_VEX_W_0_0F98_P_2_LEN_0, + MOD_VEX_W_1_0F98_P_2_LEN_0, + MOD_VEX_W_0_0F99_P_0_LEN_0, + MOD_VEX_W_1_0F99_P_0_LEN_0, + MOD_VEX_W_0_0F99_P_2_LEN_0, + MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_0FAE_REG_2, MOD_VEX_0FAE_REG_3, MOD_VEX_0FD7_PREFIX_2, @@ -809,6 +896,14 @@ enum MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2, MOD_VEX_0F388E_PREFIX_2, + MOD_VEX_W_0_0F3A30_P_2_LEN_0, + MOD_VEX_W_1_0F3A30_P_2_LEN_0, + MOD_VEX_W_0_0F3A31_P_2_LEN_0, + MOD_VEX_W_1_0F3A31_P_2_LEN_0, + MOD_VEX_W_0_0F3A32_P_2_LEN_0, + MOD_VEX_W_1_0F3A32_P_2_LEN_0, + MOD_VEX_W_0_0F3A33_P_2_LEN_0, + MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, @@ -885,13 +980,17 @@ enum PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, + PREFIX_0FAE_REG_6, PREFIX_0FAE_REG_7, + PREFIX_RM_0_0FAE_REG_7, PREFIX_0FB8, PREFIX_0FBC, PREFIX_0FBD, PREFIX_0FC2, - PREFIX_0FC3, - PREFIX_0FC7_REG_6, + PREFIX_MOD_0_0FC3, + PREFIX_MOD_0_0FC7_REG_6, + PREFIX_MOD_3_0FC7_REG_6, + PREFIX_MOD_3_0FC7_REG_7, PREFIX_0FD0, PREFIX_0FD6, PREFIX_0FE6, @@ -985,6 +1084,7 @@ enum PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, + PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F51, PREFIX_VEX_0F52, @@ -1037,6 +1137,7 @@ enum PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, + PREFIX_VEX_0F99, PREFIX_VEX_0FC2, PREFIX_VEX_0FC4, PREFIX_VEX_0FC5, @@ -1225,7 +1326,9 @@ enum PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30, + PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, + PREFIX_VEX_0F3A33, PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40, @@ -1282,6 +1385,10 @@ enum PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, + PREFIX_EVEX_0F54, + PREFIX_EVEX_0F55, + PREFIX_EVEX_0F56, + PREFIX_EVEX_0F57, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, @@ -1290,21 +1397,37 @@ enum PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, + PREFIX_EVEX_0F60, + PREFIX_EVEX_0F61, PREFIX_EVEX_0F62, + PREFIX_EVEX_0F63, + PREFIX_EVEX_0F64, + PREFIX_EVEX_0F65, PREFIX_EVEX_0F66, + PREFIX_EVEX_0F67, + PREFIX_EVEX_0F68, + PREFIX_EVEX_0F69, PREFIX_EVEX_0F6A, + PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, + PREFIX_EVEX_0F71_REG_2, + PREFIX_EVEX_0F71_REG_4, + PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, + PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6, + PREFIX_EVEX_0F73_REG_7, + PREFIX_EVEX_0F74, + PREFIX_EVEX_0F75, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, @@ -1313,26 +1436,58 @@ enum PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, + PREFIX_EVEX_0FC4, + PREFIX_EVEX_0FC5, PREFIX_EVEX_0FC6, + PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, + PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD6, + PREFIX_EVEX_0FD8, + PREFIX_EVEX_0FD9, + PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDB, + PREFIX_EVEX_0FDC, + PREFIX_EVEX_0FDD, + PREFIX_EVEX_0FDE, PREFIX_EVEX_0FDF, + PREFIX_EVEX_0FE0, + PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE2, + PREFIX_EVEX_0FE3, + PREFIX_EVEX_0FE4, + PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE6, PREFIX_EVEX_0FE7, + PREFIX_EVEX_0FE8, + PREFIX_EVEX_0FE9, + PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEB, + PREFIX_EVEX_0FEC, + PREFIX_EVEX_0FED, + PREFIX_EVEX_0FEE, PREFIX_EVEX_0FEF, + PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, + PREFIX_EVEX_0FF5, + PREFIX_EVEX_0FF6, + PREFIX_EVEX_0FF8, + PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, + PREFIX_EVEX_0FFC, + PREFIX_EVEX_0FFD, PREFIX_EVEX_0FFE, + PREFIX_EVEX_0F3800, + PREFIX_EVEX_0F3804, + PREFIX_EVEX_0F380B, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, + PREFIX_EVEX_0F3810, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, @@ -1343,19 +1498,25 @@ enum PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, + PREFIX_EVEX_0F381C, + PREFIX_EVEX_0F381D, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, + PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, + PREFIX_EVEX_0F3826, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, + PREFIX_EVEX_0F382B, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, + PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, @@ -1363,10 +1524,13 @@ enum PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, + PREFIX_EVEX_0F3838, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, + PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383D, + PREFIX_EVEX_0F383E, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, @@ -1385,15 +1549,24 @@ enum PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, + PREFIX_EVEX_0F3866, + PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, + PREFIX_EVEX_0F3878, + PREFIX_EVEX_0F3879, + PREFIX_EVEX_0F387A, + PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, + PREFIX_EVEX_0F387D, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, + PREFIX_EVEX_0F3883, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, + PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, @@ -1422,6 +1595,8 @@ enum PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, + PREFIX_EVEX_0F38B4, + PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, @@ -1456,6 +1631,10 @@ enum PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, + PREFIX_EVEX_0F3A0F, + PREFIX_EVEX_0F3A14, + PREFIX_EVEX_0F3A15, + PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, @@ -1464,7 +1643,9 @@ enum PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, + PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A21, + PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, @@ -1473,9 +1654,18 @@ enum PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, + PREFIX_EVEX_0F3A3E, + PREFIX_EVEX_0F3A3F, + PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, + PREFIX_EVEX_0F3A50, + PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55, + PREFIX_EVEX_0F3A56, + PREFIX_EVEX_0F3A57, + PREFIX_EVEX_0F3A66, + PREFIX_EVEX_0F3A67 }; enum @@ -1503,6 +1693,8 @@ enum X86_64_CE, X86_64_D4, X86_64_D5, + X86_64_E8, + X86_64_E9, X86_64_EA, X86_64_0F01_REG_0, X86_64_0F01_REG_1, @@ -1563,11 +1755,20 @@ enum VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2, VEX_LEN_0F41_P_0, + VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, + VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_0, + VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0, + VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, + VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_0, + VEX_LEN_0F47_P_2, + VEX_LEN_0F4A_P_0, + VEX_LEN_0F4A_P_2, + VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, @@ -1591,10 +1792,19 @@ enum VEX_LEN_0F7E_P_1, VEX_LEN_0F7E_P_2, VEX_LEN_0F90_P_0, + VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0, + VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, + VEX_LEN_0F92_P_2, + VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, + VEX_LEN_0F93_P_2, + VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, + VEX_LEN_0F98_P_2, + VEX_LEN_0F99_P_0, + VEX_LEN_0F99_P_2, VEX_LEN_0FAE_R_2_M_0, VEX_LEN_0FAE_R_3_M_0, VEX_LEN_0FC2_P_1, @@ -1641,7 +1851,9 @@ enum VEX_LEN_0F3A21_P_2, VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, + VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A32_P_2, + VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2, VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, @@ -1704,11 +1916,20 @@ enum VEX_W_0F2F_P_0, VEX_W_0F2F_P_2, VEX_W_0F41_P_0_LEN_1, + VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, + VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0, + VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1, + VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1, + VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1, + VEX_W_0F47_P_2_LEN_1, + VEX_W_0F4A_P_0_LEN_1, + VEX_W_0F4A_P_2_LEN_1, + VEX_W_0F4B_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F50_M_0, VEX_W_0F51_P_0, @@ -1790,10 +2011,19 @@ enum VEX_W_0F7F_P_1, VEX_W_0F7F_P_2, VEX_W_0F90_P_0_LEN_0, + VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, + VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, + VEX_W_0F92_P_2_LEN_0, + VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_0_LEN_0, + VEX_W_0F93_P_2_LEN_0, + VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_0_LEN_0, + VEX_W_0F98_P_2_LEN_0, + VEX_W_0F99_P_0_LEN_0, + VEX_W_0F99_P_2_LEN_0, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0, VEX_W_0FC2_P_0, @@ -1940,7 +2170,9 @@ enum VEX_W_0F3A20_P_2, VEX_W_0F3A21_P_2, VEX_W_0F3A30_P_2_LEN_0, + VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0, + VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2, VEX_W_0F3A39_P_2, VEX_W_0F3A40_P_2, @@ -2004,6 +2236,14 @@ enum EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, + EVEX_W_0F54_P_0, + EVEX_W_0F54_P_2, + EVEX_W_0F55_P_0, + EVEX_W_0F55_P_2, + EVEX_W_0F56_P_0, + EVEX_W_0F56_P_2, + EVEX_W_0F57_P_0, + EVEX_W_0F57_P_2, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, @@ -2038,11 +2278,13 @@ enum EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, + EVEX_W_0F6B_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, + EVEX_W_0F6F_P_3, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, @@ -2050,15 +2292,20 @@ enum EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, + EVEX_W_0F78_P_2, EVEX_W_0F79_P_0, + EVEX_W_0F79_P_2, EVEX_W_0F7A_P_1, + EVEX_W_0F7A_P_2, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, + EVEX_W_0F7B_P_2, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, + EVEX_W_0F7F_P_3, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, @@ -2081,8 +2328,12 @@ enum EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, + EVEX_W_0F3810_P_1, + EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_1, + EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_1, + EVEX_W_0F3812_P_2, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, @@ -2093,16 +2344,23 @@ enum EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, + EVEX_W_0F3820_P_1, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, + EVEX_W_0F3826_P_1, + EVEX_W_0F3826_P_2, + EVEX_W_0F3828_P_1, EVEX_W_0F3828_P_2, + EVEX_W_0F3829_P_1, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, + EVEX_W_0F382B_P_2, + EVEX_W_0F3830_P_1, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, @@ -2110,12 +2368,23 @@ enum EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, + EVEX_W_0F3838_P_1, + EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, + EVEX_W_0F3866_P_2, + EVEX_W_0F3875_P_2, + EVEX_W_0F3878_P_2, + EVEX_W_0F3879_P_2, + EVEX_W_0F387A_P_2, + EVEX_W_0F387B_P_2, + EVEX_W_0F387D_P_2, + EVEX_W_0F3883_P_2, + EVEX_W_0F388D_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, @@ -2133,18 +2402,29 @@ enum EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, + EVEX_W_0F3A16_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, + EVEX_W_0F3A22_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, + EVEX_W_0F3A3E_P_2, + EVEX_W_0F3A3F_P_2, + EVEX_W_0F3A42_P_2, EVEX_W_0F3A43_P_2, + EVEX_W_0F3A50_P_2, + EVEX_W_0F3A51_P_2, + EVEX_W_0F3A56_P_2, + EVEX_W_0F3A57_P_2, + EVEX_W_0F3A66_P_2, + EVEX_W_0F3A67_P_2 }; typedef void (*op_rtn) (int bytemode, int sizeflag); @@ -2156,6 +2436,7 @@ struct dis386 { op_rtn rtn; int bytemode; } op[MAX_OPERANDS]; + unsigned int prefix_requirement; }; /* Upper case letters in the instruction names here are macros. @@ -2183,9 +2464,12 @@ struct dis386 { is true 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 'S' => print 'w', 'l' or 'q' if suffix_always is true - 'T' => print 'q' in 64bit mode and behave as 'P' otherwise - 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise - 'V' => print 'q' in 64bit mode and behave as 'S' otherwise + 'T' => print 'q' in 64bit mode if instruction has no operand size + prefix and behave as 'P' otherwise + 'U' => print 'q' in 64bit mode if instruction has no operand size + prefix and behave as 'Q' otherwise + 'V' => print 'q' in 64bit mode if instruction has no operand size + prefix and behave as 'S' otherwise 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 'X' => print 's', 'd' depending on data16 prefix (for XMM) 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and @@ -2193,10 +2477,16 @@ struct dis386 { 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise '!' => change condition from true to false or from false to true. '%' => add 1 upper case letter to the macro. + '^' => print 'w' or 'l' depending on operand size prefix or + suffix_always is true (lcall/ljmp). + '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending + on operand size prefix. 2 upper case letter macros: - "XY" => print 'x' or 'y' if no register operands or suffix_always - is true. + "XY" => print 'x' or 'y' if suffix_always is true or no register + operands and no broadcast. + "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no + register operands and no broadcast. "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand or suffix_always is true @@ -2204,6 +2494,9 @@ struct dis386 { "LS" => print "abs" in 64bit mode and behave as 'S' otherwise "LV" => print "abs" for 64bit operand and behave as 'S' otherwise "LW" => print 'd', 'q' depending on the VEX.W bit + "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has + an operand size prefix, or suffix_always is true. print + 'q' if rex prefix is present. Many of the above letters print nothing in Intel mode. See "putop" for the details. @@ -2213,113 +2506,113 @@ struct dis386 { static const struct dis386 dis386[] = { /* 00 */ - { "addB", { Ebh1, Gb } }, - { "addS", { Evh1, Gv } }, - { "addB", { Gb, EbS } }, - { "addS", { Gv, EvS } }, - { "addB", { AL, Ib } }, - { "addS", { eAX, Iv } }, + { "addB", { Ebh1, Gb }, 0 }, + { "addS", { Evh1, Gv }, 0 }, + { "addB", { Gb, EbS }, 0 }, + { "addS", { Gv, EvS }, 0 }, + { "addB", { AL, Ib }, 0 }, + { "addS", { eAX, Iv }, 0 }, { X86_64_TABLE (X86_64_06) }, { X86_64_TABLE (X86_64_07) }, /* 08 */ - { "orB", { Ebh1, Gb } }, - { "orS", { Evh1, Gv } }, - { "orB", { Gb, EbS } }, - { "orS", { Gv, EvS } }, - { "orB", { AL, Ib } }, - { "orS", { eAX, Iv } }, + { "orB", { Ebh1, Gb }, 0 }, + { "orS", { Evh1, Gv }, 0 }, + { "orB", { Gb, EbS }, 0 }, + { "orS", { Gv, EvS }, 0 }, + { "orB", { AL, Ib }, 0 }, + { "orS", { eAX, Iv }, 0 }, { X86_64_TABLE (X86_64_0D) }, { Bad_Opcode }, /* 0x0f extended opcode escape */ /* 10 */ - { "adcB", { Ebh1, Gb } }, - { "adcS", { Evh1, Gv } }, - { "adcB", { Gb, EbS } }, - { "adcS", { Gv, EvS } }, - { "adcB", { AL, Ib } }, - { "adcS", { eAX, Iv } }, + { "adcB", { Ebh1, Gb }, 0 }, + { "adcS", { Evh1, Gv }, 0 }, + { "adcB", { Gb, EbS }, 0 }, + { "adcS", { Gv, EvS }, 0 }, + { "adcB", { AL, Ib }, 0 }, + { "adcS", { eAX, Iv }, 0 }, { X86_64_TABLE (X86_64_16) }, { X86_64_TABLE (X86_64_17) }, /* 18 */ - { "sbbB", { Ebh1, Gb } }, - { "sbbS", { Evh1, Gv } }, - { "sbbB", { Gb, EbS } }, - { "sbbS", { Gv, EvS } }, - { "sbbB", { AL, Ib } }, - { "sbbS", { eAX, Iv } }, + { "sbbB", { Ebh1, Gb }, 0 }, + { "sbbS", { Evh1, Gv }, 0 }, + { "sbbB", { Gb, EbS }, 0 }, + { "sbbS", { Gv, EvS }, 0 }, + { "sbbB", { AL, Ib }, 0 }, + { "sbbS", { eAX, Iv }, 0 }, { X86_64_TABLE (X86_64_1E) }, { X86_64_TABLE (X86_64_1F) }, /* 20 */ - { "andB", { Ebh1, Gb } }, - { "andS", { Evh1, Gv } }, - { "andB", { Gb, EbS } }, - { "andS", { Gv, EvS } }, - { "andB", { AL, Ib } }, - { "andS", { eAX, Iv } }, + { "andB", { Ebh1, Gb }, 0 }, + { "andS", { Evh1, Gv }, 0 }, + { "andB", { Gb, EbS }, 0 }, + { "andS", { Gv, EvS }, 0 }, + { "andB", { AL, Ib }, 0 }, + { "andS", { eAX, Iv }, 0 }, { Bad_Opcode }, /* SEG ES prefix */ { X86_64_TABLE (X86_64_27) }, /* 28 */ - { "subB", { Ebh1, Gb } }, - { "subS", { Evh1, Gv } }, - { "subB", { Gb, EbS } }, - { "subS", { Gv, EvS } }, - { "subB", { AL, Ib } }, - { "subS", { eAX, Iv } }, + { "subB", { Ebh1, Gb }, 0 }, + { "subS", { Evh1, Gv }, 0 }, + { "subB", { Gb, EbS }, 0 }, + { "subS", { Gv, EvS }, 0 }, + { "subB", { AL, Ib }, 0 }, + { "subS", { eAX, Iv }, 0 }, { Bad_Opcode }, /* SEG CS prefix */ { X86_64_TABLE (X86_64_2F) }, /* 30 */ - { "xorB", { Ebh1, Gb } }, - { "xorS", { Evh1, Gv } }, - { "xorB", { Gb, EbS } }, - { "xorS", { Gv, EvS } }, - { "xorB", { AL, Ib } }, - { "xorS", { eAX, Iv } }, + { "xorB", { Ebh1, Gb }, 0 }, + { "xorS", { Evh1, Gv }, 0 }, + { "xorB", { Gb, EbS }, 0 }, + { "xorS", { Gv, EvS }, 0 }, + { "xorB", { AL, Ib }, 0 }, + { "xorS", { eAX, Iv }, 0 }, { Bad_Opcode }, /* SEG SS prefix */ { X86_64_TABLE (X86_64_37) }, /* 38 */ - { "cmpB", { Eb, Gb } }, - { "cmpS", { Ev, Gv } }, - { "cmpB", { Gb, EbS } }, - { "cmpS", { Gv, EvS } }, - { "cmpB", { AL, Ib } }, - { "cmpS", { eAX, Iv } }, + { "cmpB", { Eb, Gb }, 0 }, + { "cmpS", { Ev, Gv }, 0 }, + { "cmpB", { Gb, EbS }, 0 }, + { "cmpS", { Gv, EvS }, 0 }, + { "cmpB", { AL, Ib }, 0 }, + { "cmpS", { eAX, Iv }, 0 }, { Bad_Opcode }, /* SEG DS prefix */ { X86_64_TABLE (X86_64_3F) }, /* 40 */ - { "inc{S|}", { RMeAX } }, - { "inc{S|}", { RMeCX } }, - { "inc{S|}", { RMeDX } }, - { "inc{S|}", { RMeBX } }, - { "inc{S|}", { RMeSP } }, - { "inc{S|}", { RMeBP } }, - { "inc{S|}", { RMeSI } }, - { "inc{S|}", { RMeDI } }, + { "inc{S|}", { RMeAX }, 0 }, + { "inc{S|}", { RMeCX }, 0 }, + { "inc{S|}", { RMeDX }, 0 }, + { "inc{S|}", { RMeBX }, 0 }, + { "inc{S|}", { RMeSP }, 0 }, + { "inc{S|}", { RMeBP }, 0 }, + { "inc{S|}", { RMeSI }, 0 }, + { "inc{S|}", { RMeDI }, 0 }, /* 48 */ - { "dec{S|}", { RMeAX } }, - { "dec{S|}", { RMeCX } }, - { "dec{S|}", { RMeDX } }, - { "dec{S|}", { RMeBX } }, - { "dec{S|}", { RMeSP } }, - { "dec{S|}", { RMeBP } }, - { "dec{S|}", { RMeSI } }, - { "dec{S|}", { RMeDI } }, + { "dec{S|}", { RMeAX }, 0 }, + { "dec{S|}", { RMeCX }, 0 }, + { "dec{S|}", { RMeDX }, 0 }, + { "dec{S|}", { RMeBX }, 0 }, + { "dec{S|}", { RMeSP }, 0 }, + { "dec{S|}", { RMeBP }, 0 }, + { "dec{S|}", { RMeSI }, 0 }, + { "dec{S|}", { RMeDI }, 0 }, /* 50 */ - { "pushV", { RMrAX } }, - { "pushV", { RMrCX } }, - { "pushV", { RMrDX } }, - { "pushV", { RMrBX } }, - { "pushV", { RMrSP } }, - { "pushV", { RMrBP } }, - { "pushV", { RMrSI } }, - { "pushV", { RMrDI } }, + { "pushV", { RMrAX }, 0 }, + { "pushV", { RMrCX }, 0 }, + { "pushV", { RMrDX }, 0 }, + { "pushV", { RMrBX }, 0 }, + { "pushV", { RMrSP }, 0 }, + { "pushV", { RMrBP }, 0 }, + { "pushV", { RMrSI }, 0 }, + { "pushV", { RMrDI }, 0 }, /* 58 */ - { "popV", { RMrAX } }, - { "popV", { RMrCX } }, - { "popV", { RMrDX } }, - { "popV", { RMrBX } }, - { "popV", { RMrSP } }, - { "popV", { RMrBP } }, - { "popV", { RMrSI } }, - { "popV", { RMrDI } }, + { "popV", { RMrAX }, 0 }, + { "popV", { RMrCX }, 0 }, + { "popV", { RMrDX }, 0 }, + { "popV", { RMrBX }, 0 }, + { "popV", { RMrSP }, 0 }, + { "popV", { RMrBP }, 0 }, + { "popV", { RMrSI }, 0 }, + { "popV", { RMrDI }, 0 }, /* 60 */ { X86_64_TABLE (X86_64_60) }, { X86_64_TABLE (X86_64_61) }, @@ -2330,122 +2623,122 @@ static const struct dis386 dis386[] = { { Bad_Opcode }, /* op size prefix */ { Bad_Opcode }, /* adr size prefix */ /* 68 */ - { "pushT", { sIv } }, - { "imulS", { Gv, Ev, Iv } }, - { "pushT", { sIbT } }, - { "imulS", { Gv, Ev, sIb } }, - { "ins{b|}", { Ybr, indirDX } }, + { "pushT", { sIv }, 0 }, + { "imulS", { Gv, Ev, Iv }, 0 }, + { "pushT", { sIbT }, 0 }, + { "imulS", { Gv, Ev, sIb }, 0 }, + { "ins{b|}", { Ybr, indirDX }, 0 }, { X86_64_TABLE (X86_64_6D) }, - { "outs{b|}", { indirDXr, Xb } }, + { "outs{b|}", { indirDXr, Xb }, 0 }, { X86_64_TABLE (X86_64_6F) }, /* 70 */ - { "joH", { Jb, BND, cond_jump_flag } }, - { "jnoH", { Jb, BND, cond_jump_flag } }, - { "jbH", { Jb, BND, cond_jump_flag } }, - { "jaeH", { Jb, BND, cond_jump_flag } }, - { "jeH", { Jb, BND, cond_jump_flag } }, - { "jneH", { Jb, BND, cond_jump_flag } }, - { "jbeH", { Jb, BND, cond_jump_flag } }, - { "jaH", { Jb, BND, cond_jump_flag } }, + { "joH", { Jb, BND, cond_jump_flag }, 0 }, + { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, + { "jbH", { Jb, BND, cond_jump_flag }, 0 }, + { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, + { "jeH", { Jb, BND, cond_jump_flag }, 0 }, + { "jneH", { Jb, BND, cond_jump_flag }, 0 }, + { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, + { "jaH", { Jb, BND, cond_jump_flag }, 0 }, /* 78 */ - { "jsH", { Jb, BND, cond_jump_flag } }, - { "jnsH", { Jb, BND, cond_jump_flag } }, - { "jpH", { Jb, BND, cond_jump_flag } }, - { "jnpH", { Jb, BND, cond_jump_flag } }, - { "jlH", { Jb, BND, cond_jump_flag } }, - { "jgeH", { Jb, BND, cond_jump_flag } }, - { "jleH", { Jb, BND, cond_jump_flag } }, - { "jgH", { Jb, BND, cond_jump_flag } }, + { "jsH", { Jb, BND, cond_jump_flag }, 0 }, + { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, + { "jpH", { Jb, BND, cond_jump_flag }, 0 }, + { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, + { "jlH", { Jb, BND, cond_jump_flag }, 0 }, + { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, + { "jleH", { Jb, BND, cond_jump_flag }, 0 }, + { "jgH", { Jb, BND, cond_jump_flag }, 0 }, /* 80 */ { REG_TABLE (REG_80) }, { REG_TABLE (REG_81) }, { Bad_Opcode }, { REG_TABLE (REG_82) }, - { "testB", { Eb, Gb } }, - { "testS", { Ev, Gv } }, - { "xchgB", { Ebh2, Gb } }, - { "xchgS", { Evh2, Gv } }, + { "testB", { Eb, Gb }, 0 }, + { "testS", { Ev, Gv }, 0 }, + { "xchgB", { Ebh2, Gb }, 0 }, + { "xchgS", { Evh2, Gv }, 0 }, /* 88 */ - { "movB", { Ebh3, Gb } }, - { "movS", { Evh3, Gv } }, - { "movB", { Gb, EbS } }, - { "movS", { Gv, EvS } }, - { "movD", { Sv, Sw } }, + { "movB", { Ebh3, Gb }, 0 }, + { "movS", { Evh3, Gv }, 0 }, + { "movB", { Gb, EbS }, 0 }, + { "movS", { Gv, EvS }, 0 }, + { "movD", { Sv, Sw }, 0 }, { MOD_TABLE (MOD_8D) }, - { "movD", { Sw, Sv } }, + { "movD", { Sw, Sv }, 0 }, { REG_TABLE (REG_8F) }, /* 90 */ { PREFIX_TABLE (PREFIX_90) }, - { "xchgS", { RMeCX, eAX } }, - { "xchgS", { RMeDX, eAX } }, - { "xchgS", { RMeBX, eAX } }, - { "xchgS", { RMeSP, eAX } }, - { "xchgS", { RMeBP, eAX } }, - { "xchgS", { RMeSI, eAX } }, - { "xchgS", { RMeDI, eAX } }, + { "xchgS", { RMeCX, eAX }, 0 }, + { "xchgS", { RMeDX, eAX }, 0 }, + { "xchgS", { RMeBX, eAX }, 0 }, + { "xchgS", { RMeSP, eAX }, 0 }, + { "xchgS", { RMeBP, eAX }, 0 }, + { "xchgS", { RMeSI, eAX }, 0 }, + { "xchgS", { RMeDI, eAX }, 0 }, /* 98 */ - { "cW{t|}R", { XX } }, - { "cR{t|}O", { XX } }, + { "cW{t|}R", { XX }, 0 }, + { "cR{t|}O", { XX }, 0 }, { X86_64_TABLE (X86_64_9A) }, { Bad_Opcode }, /* fwait */ - { "pushfT", { XX } }, - { "popfT", { XX } }, - { "sahf", { XX } }, - { "lahf", { XX } }, + { "pushfT", { XX }, 0 }, + { "popfT", { XX }, 0 }, + { "sahf", { XX }, 0 }, + { "lahf", { XX }, 0 }, /* a0 */ - { "mov%LB", { AL, Ob } }, - { "mov%LS", { eAX, Ov } }, - { "mov%LB", { Ob, AL } }, - { "mov%LS", { Ov, eAX } }, - { "movs{b|}", { Ybr, Xb } }, - { "movs{R|}", { Yvr, Xv } }, - { "cmps{b|}", { Xb, Yb } }, - { "cmps{R|}", { Xv, Yv } }, + { "mov%LB", { AL, Ob }, 0 }, + { "mov%LS", { eAX, Ov }, 0 }, + { "mov%LB", { Ob, AL }, 0 }, + { "mov%LS", { Ov, eAX }, 0 }, + { "movs{b|}", { Ybr, Xb }, 0 }, + { "movs{R|}", { Yvr, Xv }, 0 }, + { "cmps{b|}", { Xb, Yb }, 0 }, + { "cmps{R|}", { Xv, Yv }, 0 }, /* a8 */ - { "testB", { AL, Ib } }, - { "testS", { eAX, Iv } }, - { "stosB", { Ybr, AL } }, - { "stosS", { Yvr, eAX } }, - { "lodsB", { ALr, Xb } }, - { "lodsS", { eAXr, Xv } }, - { "scasB", { AL, Yb } }, - { "scasS", { eAX, Yv } }, + { "testB", { AL, Ib }, 0 }, + { "testS", { eAX, Iv }, 0 }, + { "stosB", { Ybr, AL }, 0 }, + { "stosS", { Yvr, eAX }, 0 }, + { "lodsB", { ALr, Xb }, 0 }, + { "lodsS", { eAXr, Xv }, 0 }, + { "scasB", { AL, Yb }, 0 }, + { "scasS", { eAX, Yv }, 0 }, /* b0 */ - { "movB", { RMAL, Ib } }, - { "movB", { RMCL, Ib } }, - { "movB", { RMDL, Ib } }, - { "movB", { RMBL, Ib } }, - { "movB", { RMAH, Ib } }, - { "movB", { RMCH, Ib } }, - { "movB", { RMDH, Ib } }, - { "movB", { RMBH, Ib } }, + { "movB", { RMAL, Ib }, 0 }, + { "movB", { RMCL, Ib }, 0 }, + { "movB", { RMDL, Ib }, 0 }, + { "movB", { RMBL, Ib }, 0 }, + { "movB", { RMAH, Ib }, 0 }, + { "movB", { RMCH, Ib }, 0 }, + { "movB", { RMDH, Ib }, 0 }, + { "movB", { RMBH, Ib }, 0 }, /* b8 */ - { "mov%LV", { RMeAX, Iv64 } }, - { "mov%LV", { RMeCX, Iv64 } }, - { "mov%LV", { RMeDX, Iv64 } }, - { "mov%LV", { RMeBX, Iv64 } }, - { "mov%LV", { RMeSP, Iv64 } }, - { "mov%LV", { RMeBP, Iv64 } }, - { "mov%LV", { RMeSI, Iv64 } }, - { "mov%LV", { RMeDI, Iv64 } }, + { "mov%LV", { RMeAX, Iv64 }, 0 }, + { "mov%LV", { RMeCX, Iv64 }, 0 }, + { "mov%LV", { RMeDX, Iv64 }, 0 }, + { "mov%LV", { RMeBX, Iv64 }, 0 }, + { "mov%LV", { RMeSP, Iv64 }, 0 }, + { "mov%LV", { RMeBP, Iv64 }, 0 }, + { "mov%LV", { RMeSI, Iv64 }, 0 }, + { "mov%LV", { RMeDI, Iv64 }, 0 }, /* c0 */ { REG_TABLE (REG_C0) }, { REG_TABLE (REG_C1) }, - { "retT", { Iw, BND } }, - { "retT", { BND } }, + { "retT", { Iw, BND }, 0 }, + { "retT", { BND }, 0 }, { X86_64_TABLE (X86_64_C4) }, { X86_64_TABLE (X86_64_C5) }, { REG_TABLE (REG_C6) }, { REG_TABLE (REG_C7) }, /* c8 */ - { "enterT", { Iw, Ib } }, - { "leaveT", { XX } }, - { "Jret{|f}P", { Iw } }, - { "Jret{|f}P", { XX } }, - { "int3", { XX } }, - { "int", { Ib } }, + { "enterT", { Iw, Ib }, 0 }, + { "leaveT", { XX }, 0 }, + { "Jret{|f}P", { Iw }, 0 }, + { "Jret{|f}P", { XX }, 0 }, + { "int3", { XX }, 0 }, + { "int", { Ib }, 0 }, { X86_64_TABLE (X86_64_CE) }, - { "iretP", { XX } }, + { "iret%LP", { XX }, 0 }, /* d0 */ { REG_TABLE (REG_D0) }, { REG_TABLE (REG_D1) }, @@ -2454,7 +2747,7 @@ static const struct dis386 dis386[] = { { X86_64_TABLE (X86_64_D4) }, { X86_64_TABLE (X86_64_D5) }, { Bad_Opcode }, - { "xlat", { DSBX } }, + { "xlat", { DSBX }, 0 }, /* d8 */ { FLOAT }, { FLOAT }, @@ -2465,39 +2758,39 @@ static const struct dis386 dis386[] = { { FLOAT }, { FLOAT }, /* e0 */ - { "loopneFH", { Jb, XX, loop_jcxz_flag } }, - { "loopeFH", { Jb, XX, loop_jcxz_flag } }, - { "loopFH", { Jb, XX, loop_jcxz_flag } }, - { "jEcxzH", { Jb, XX, loop_jcxz_flag } }, - { "inB", { AL, Ib } }, - { "inG", { zAX, Ib } }, - { "outB", { Ib, AL } }, - { "outG", { Ib, zAX } }, + { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, + { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, + { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, + { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, + { "inB", { AL, Ib }, 0 }, + { "inG", { zAX, Ib }, 0 }, + { "outB", { Ib, AL }, 0 }, + { "outG", { Ib, zAX }, 0 }, /* e8 */ - { "callT", { Jv, BND } }, - { "jmpT", { Jv, BND } }, + { X86_64_TABLE (X86_64_E8) }, + { X86_64_TABLE (X86_64_E9) }, { X86_64_TABLE (X86_64_EA) }, - { "jmp", { Jb, BND } }, - { "inB", { AL, indirDX } }, - { "inG", { zAX, indirDX } }, - { "outB", { indirDX, AL } }, - { "outG", { indirDX, zAX } }, + { "jmp", { Jb, BND }, 0 }, + { "inB", { AL, indirDX }, 0 }, + { "inG", { zAX, indirDX }, 0 }, + { "outB", { indirDX, AL }, 0 }, + { "outG", { indirDX, zAX }, 0 }, /* f0 */ { Bad_Opcode }, /* lock prefix */ - { "icebp", { XX } }, + { "icebp", { XX }, 0 }, { Bad_Opcode }, /* repne */ { Bad_Opcode }, /* repz */ - { "hlt", { XX } }, - { "cmc", { XX } }, + { "hlt", { XX }, 0 }, + { "cmc", { XX }, 0 }, { REG_TABLE (REG_F6) }, { REG_TABLE (REG_F7) }, /* f8 */ - { "clc", { XX } }, - { "stc", { XX } }, - { "cli", { XX } }, - { "sti", { XX } }, - { "cld", { XX } }, - { "std", { XX } }, + { "clc", { XX }, 0 }, + { "stc", { XX }, 0 }, + { "cli", { XX }, 0 }, + { "sti", { XX }, 0 }, + { "cld", { XX }, 0 }, + { "std", { XX }, 0 }, { REG_TABLE (REG_FE) }, { REG_TABLE (REG_FF) }, }; @@ -2506,51 +2799,51 @@ static const struct dis386 dis386_twobyte[] = { /* 00 */ { REG_TABLE (REG_0F00 ) }, { REG_TABLE (REG_0F01 ) }, - { "larS", { Gv, Ew } }, - { "lslS", { Gv, Ew } }, + { "larS", { Gv, Ew }, 0 }, + { "lslS", { Gv, Ew }, 0 }, { Bad_Opcode }, - { "syscall", { XX } }, - { "clts", { XX } }, - { "sysretP", { XX } }, + { "syscall", { XX }, 0 }, + { "clts", { XX }, 0 }, + { "sysret%LP", { XX }, 0 }, /* 08 */ - { "invd", { XX } }, - { "wbinvd", { XX } }, + { "invd", { XX }, 0 }, + { "wbinvd", { XX }, 0 }, { Bad_Opcode }, - { "ud2", { XX } }, + { "ud2", { XX }, 0 }, { Bad_Opcode }, { REG_TABLE (REG_0F0D) }, - { "femms", { XX } }, - { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */ + { "femms", { XX }, 0 }, + { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ /* 10 */ { PREFIX_TABLE (PREFIX_0F10) }, { PREFIX_TABLE (PREFIX_0F11) }, { PREFIX_TABLE (PREFIX_0F12) }, { MOD_TABLE (MOD_0F13) }, - { "unpcklpX", { XM, EXx } }, - { "unpckhpX", { XM, EXx } }, + { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, + { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F16) }, { MOD_TABLE (MOD_0F17) }, /* 18 */ { REG_TABLE (REG_0F18) }, - { "nopQ", { Ev } }, + { "nopQ", { Ev }, 0 }, { PREFIX_TABLE (PREFIX_0F1A) }, { PREFIX_TABLE (PREFIX_0F1B) }, - { "nopQ", { Ev } }, - { "nopQ", { Ev } }, - { "nopQ", { Ev } }, - { "nopQ", { Ev } }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, /* 20 */ - { MOD_TABLE (MOD_0F20) }, - { MOD_TABLE (MOD_0F21) }, - { MOD_TABLE (MOD_0F22) }, - { MOD_TABLE (MOD_0F23) }, + { "movZ", { Rm, Cm }, 0 }, + { "movZ", { Rm, Dm }, 0 }, + { "movZ", { Cm, Rm }, 0 }, + { "movZ", { Dm, Rm }, 0 }, { MOD_TABLE (MOD_0F24) }, { Bad_Opcode }, { MOD_TABLE (MOD_0F26) }, { Bad_Opcode }, /* 28 */ - { "movapX", { XM, EXx } }, - { "movapX", { EXxS, XM } }, + { "movapX", { XM, EXx }, PREFIX_OPCODE }, + { "movapX", { EXxS, XM }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F2A) }, { PREFIX_TABLE (PREFIX_0F2B) }, { PREFIX_TABLE (PREFIX_0F2C) }, @@ -2558,50 +2851,50 @@ static const struct dis386 dis386_twobyte[] = { { PREFIX_TABLE (PREFIX_0F2E) }, { PREFIX_TABLE (PREFIX_0F2F) }, /* 30 */ - { "wrmsr", { XX } }, - { "rdtsc", { XX } }, - { "rdmsr", { XX } }, - { "rdpmc", { XX } }, - { "sysenter", { XX } }, - { "sysexit", { XX } }, + { "wrmsr", { XX }, 0 }, + { "rdtsc", { XX }, 0 }, + { "rdmsr", { XX }, 0 }, + { "rdpmc", { XX }, 0 }, + { "sysenter", { XX }, 0 }, + { "sysexit", { XX }, 0 }, { Bad_Opcode }, - { "getsec", { XX } }, + { "getsec", { XX }, 0 }, /* 38 */ - { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, + { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, { Bad_Opcode }, - { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, + { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 40 */ - { "cmovoS", { Gv, Ev } }, - { "cmovnoS", { Gv, Ev } }, - { "cmovbS", { Gv, Ev } }, - { "cmovaeS", { Gv, Ev } }, - { "cmoveS", { Gv, Ev } }, - { "cmovneS", { Gv, Ev } }, - { "cmovbeS", { Gv, Ev } }, - { "cmovaS", { Gv, Ev } }, + { "cmovoS", { Gv, Ev }, 0 }, + { "cmovnoS", { Gv, Ev }, 0 }, + { "cmovbS", { Gv, Ev }, 0 }, + { "cmovaeS", { Gv, Ev }, 0 }, + { "cmoveS", { Gv, Ev }, 0 }, + { "cmovneS", { Gv, Ev }, 0 }, + { "cmovbeS", { Gv, Ev }, 0 }, + { "cmovaS", { Gv, Ev }, 0 }, /* 48 */ - { "cmovsS", { Gv, Ev } }, - { "cmovnsS", { Gv, Ev } }, - { "cmovpS", { Gv, Ev } }, - { "cmovnpS", { Gv, Ev } }, - { "cmovlS", { Gv, Ev } }, - { "cmovgeS", { Gv, Ev } }, - { "cmovleS", { Gv, Ev } }, - { "cmovgS", { Gv, Ev } }, + { "cmovsS", { Gv, Ev }, 0 }, + { "cmovnsS", { Gv, Ev }, 0 }, + { "cmovpS", { Gv, Ev }, 0 }, + { "cmovnpS", { Gv, Ev }, 0 }, + { "cmovlS", { Gv, Ev }, 0 }, + { "cmovgeS", { Gv, Ev }, 0 }, + { "cmovleS", { Gv, Ev }, 0 }, + { "cmovgS", { Gv, Ev }, 0 }, /* 50 */ { MOD_TABLE (MOD_0F51) }, { PREFIX_TABLE (PREFIX_0F51) }, { PREFIX_TABLE (PREFIX_0F52) }, { PREFIX_TABLE (PREFIX_0F53) }, - { "andpX", { XM, EXx } }, - { "andnpX", { XM, EXx } }, - { "orpX", { XM, EXx } }, - { "xorpX", { XM, EXx } }, + { "andpX", { XM, EXx }, PREFIX_OPCODE }, + { "andnpX", { XM, EXx }, PREFIX_OPCODE }, + { "orpX", { XM, EXx }, PREFIX_OPCODE }, + { "xorpX", { XM, EXx }, PREFIX_OPCODE }, /* 58 */ { PREFIX_TABLE (PREFIX_0F58) }, { PREFIX_TABLE (PREFIX_0F59) }, @@ -2615,29 +2908,29 @@ static const struct dis386 dis386_twobyte[] = { { PREFIX_TABLE (PREFIX_0F60) }, { PREFIX_TABLE (PREFIX_0F61) }, { PREFIX_TABLE (PREFIX_0F62) }, - { "packsswb", { MX, EM } }, - { "pcmpgtb", { MX, EM } }, - { "pcmpgtw", { MX, EM } }, - { "pcmpgtd", { MX, EM } }, - { "packuswb", { MX, EM } }, + { "packsswb", { MX, EM }, PREFIX_OPCODE }, + { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, + { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, + { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, + { "packuswb", { MX, EM }, PREFIX_OPCODE }, /* 68 */ - { "punpckhbw", { MX, EM } }, - { "punpckhwd", { MX, EM } }, - { "punpckhdq", { MX, EM } }, - { "packssdw", { MX, EM } }, + { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, + { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, + { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, + { "packssdw", { MX, EM }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F6C) }, { PREFIX_TABLE (PREFIX_0F6D) }, - { "movK", { MX, Edq } }, + { "movK", { MX, Edq }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0F6F) }, /* 70 */ { PREFIX_TABLE (PREFIX_0F70) }, { REG_TABLE (REG_0F71) }, { REG_TABLE (REG_0F72) }, { REG_TABLE (REG_0F73) }, - { "pcmpeqb", { MX, EM } }, - { "pcmpeqw", { MX, EM } }, - { "pcmpeqd", { MX, EM } }, - { "emms", { XX } }, + { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, + { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, + { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, + { "emms", { XX }, PREFIX_OPCODE }, /* 78 */ { PREFIX_TABLE (PREFIX_0F78) }, { PREFIX_TABLE (PREFIX_0F79) }, @@ -2648,148 +2941,148 @@ static const struct dis386 dis386_twobyte[] = { { PREFIX_TABLE (PREFIX_0F7E) }, { PREFIX_TABLE (PREFIX_0F7F) }, /* 80 */ - { "joH", { Jv, BND, cond_jump_flag } }, - { "jnoH", { Jv, BND, cond_jump_flag } }, - { "jbH", { Jv, BND, cond_jump_flag } }, - { "jaeH", { Jv, BND, cond_jump_flag } }, - { "jeH", { Jv, BND, cond_jump_flag } }, - { "jneH", { Jv, BND, cond_jump_flag } }, - { "jbeH", { Jv, BND, cond_jump_flag } }, - { "jaH", { Jv, BND, cond_jump_flag } }, + { "joH", { Jv, BND, cond_jump_flag }, 0 }, + { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, + { "jbH", { Jv, BND, cond_jump_flag }, 0 }, + { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, + { "jeH", { Jv, BND, cond_jump_flag }, 0 }, + { "jneH", { Jv, BND, cond_jump_flag }, 0 }, + { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, + { "jaH", { Jv, BND, cond_jump_flag }, 0 }, /* 88 */ - { "jsH", { Jv, BND, cond_jump_flag } }, - { "jnsH", { Jv, BND, cond_jump_flag } }, - { "jpH", { Jv, BND, cond_jump_flag } }, - { "jnpH", { Jv, BND, cond_jump_flag } }, - { "jlH", { Jv, BND, cond_jump_flag } }, - { "jgeH", { Jv, BND, cond_jump_flag } }, - { "jleH", { Jv, BND, cond_jump_flag } }, - { "jgH", { Jv, BND, cond_jump_flag } }, + { "jsH", { Jv, BND, cond_jump_flag }, 0 }, + { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, + { "jpH", { Jv, BND, cond_jump_flag }, 0 }, + { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, + { "jlH", { Jv, BND, cond_jump_flag }, 0 }, + { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, + { "jleH", { Jv, BND, cond_jump_flag }, 0 }, + { "jgH", { Jv, BND, cond_jump_flag }, 0 }, /* 90 */ - { "seto", { Eb } }, - { "setno", { Eb } }, - { "setb", { Eb } }, - { "setae", { Eb } }, - { "sete", { Eb } }, - { "setne", { Eb } }, - { "setbe", { Eb } }, - { "seta", { Eb } }, + { "seto", { Eb }, 0 }, + { "setno", { Eb }, 0 }, + { "setb", { Eb }, 0 }, + { "setae", { Eb }, 0 }, + { "sete", { Eb }, 0 }, + { "setne", { Eb }, 0 }, + { "setbe", { Eb }, 0 }, + { "seta", { Eb }, 0 }, /* 98 */ - { "sets", { Eb } }, - { "setns", { Eb } }, - { "setp", { Eb } }, - { "setnp", { Eb } }, - { "setl", { Eb } }, - { "setge", { Eb } }, - { "setle", { Eb } }, - { "setg", { Eb } }, + { "sets", { Eb }, 0 }, + { "setns", { Eb }, 0 }, + { "setp", { Eb }, 0 }, + { "setnp", { Eb }, 0 }, + { "setl", { Eb }, 0 }, + { "setge", { Eb }, 0 }, + { "setle", { Eb }, 0 }, + { "setg", { Eb }, 0 }, /* a0 */ - { "pushT", { fs } }, - { "popT", { fs } }, - { "cpuid", { XX } }, - { "btS", { Ev, Gv } }, - { "shldS", { Ev, Gv, Ib } }, - { "shldS", { Ev, Gv, CL } }, + { "pushT", { fs }, 0 }, + { "popT", { fs }, 0 }, + { "cpuid", { XX }, 0 }, + { "btS", { Ev, Gv }, 0 }, + { "shldS", { Ev, Gv, Ib }, 0 }, + { "shldS", { Ev, Gv, CL }, 0 }, { REG_TABLE (REG_0FA6) }, { REG_TABLE (REG_0FA7) }, /* a8 */ - { "pushT", { gs } }, - { "popT", { gs } }, - { "rsm", { XX } }, - { "btsS", { Evh1, Gv } }, - { "shrdS", { Ev, Gv, Ib } }, - { "shrdS", { Ev, Gv, CL } }, + { "pushT", { gs }, 0 }, + { "popT", { gs }, 0 }, + { "rsm", { XX }, 0 }, + { "btsS", { Evh1, Gv }, 0 }, + { "shrdS", { Ev, Gv, Ib }, 0 }, + { "shrdS", { Ev, Gv, CL }, 0 }, { REG_TABLE (REG_0FAE) }, - { "imulS", { Gv, Ev } }, + { "imulS", { Gv, Ev }, 0 }, /* b0 */ - { "cmpxchgB", { Ebh1, Gb } }, - { "cmpxchgS", { Evh1, Gv } }, + { "cmpxchgB", { Ebh1, Gb }, 0 }, + { "cmpxchgS", { Evh1, Gv }, 0 }, { MOD_TABLE (MOD_0FB2) }, - { "btrS", { Evh1, Gv } }, + { "btrS", { Evh1, Gv }, 0 }, { MOD_TABLE (MOD_0FB4) }, { MOD_TABLE (MOD_0FB5) }, - { "movz{bR|x}", { Gv, Eb } }, - { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */ + { "movz{bR|x}", { Gv, Eb }, 0 }, + { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ /* b8 */ { PREFIX_TABLE (PREFIX_0FB8) }, - { "ud1", { XX } }, + { "ud1", { XX }, 0 }, { REG_TABLE (REG_0FBA) }, - { "btcS", { Evh1, Gv } }, + { "btcS", { Evh1, Gv }, 0 }, { PREFIX_TABLE (PREFIX_0FBC) }, { PREFIX_TABLE (PREFIX_0FBD) }, - { "movs{bR|x}", { Gv, Eb } }, - { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */ + { "movs{bR|x}", { Gv, Eb }, 0 }, + { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ /* c0 */ - { "xaddB", { Ebh1, Gb } }, - { "xaddS", { Evh1, Gv } }, + { "xaddB", { Ebh1, Gb }, 0 }, + { "xaddS", { Evh1, Gv }, 0 }, { PREFIX_TABLE (PREFIX_0FC2) }, - { PREFIX_TABLE (PREFIX_0FC3) }, - { "pinsrw", { MX, Edqw, Ib } }, - { "pextrw", { Gdq, MS, Ib } }, - { "shufpX", { XM, EXx, Ib } }, + { MOD_TABLE (MOD_0FC3) }, + { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, + { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, + { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, { REG_TABLE (REG_0FC7) }, /* c8 */ - { "bswap", { RMeAX } }, - { "bswap", { RMeCX } }, - { "bswap", { RMeDX } }, - { "bswap", { RMeBX } }, - { "bswap", { RMeSP } }, - { "bswap", { RMeBP } }, - { "bswap", { RMeSI } }, - { "bswap", { RMeDI } }, + { "bswap", { RMeAX }, 0 }, + { "bswap", { RMeCX }, 0 }, + { "bswap", { RMeDX }, 0 }, + { "bswap", { RMeBX }, 0 }, + { "bswap", { RMeSP }, 0 }, + { "bswap", { RMeBP }, 0 }, + { "bswap", { RMeSI }, 0 }, + { "bswap", { RMeDI }, 0 }, /* d0 */ { PREFIX_TABLE (PREFIX_0FD0) }, - { "psrlw", { MX, EM } }, - { "psrld", { MX, EM } }, - { "psrlq", { MX, EM } }, - { "paddq", { MX, EM } }, - { "pmullw", { MX, EM } }, + { "psrlw", { MX, EM }, PREFIX_OPCODE }, + { "psrld", { MX, EM }, PREFIX_OPCODE }, + { "psrlq", { MX, EM }, PREFIX_OPCODE }, + { "paddq", { MX, EM }, PREFIX_OPCODE }, + { "pmullw", { MX, EM }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0FD6) }, { MOD_TABLE (MOD_0FD7) }, /* d8 */ - { "psubusb", { MX, EM } }, - { "psubusw", { MX, EM } }, - { "pminub", { MX, EM } }, - { "pand", { MX, EM } }, - { "paddusb", { MX, EM } }, - { "paddusw", { MX, EM } }, - { "pmaxub", { MX, EM } }, - { "pandn", { MX, EM } }, + { "psubusb", { MX, EM }, PREFIX_OPCODE }, + { "psubusw", { MX, EM }, PREFIX_OPCODE }, + { "pminub", { MX, EM }, PREFIX_OPCODE }, + { "pand", { MX, EM }, PREFIX_OPCODE }, + { "paddusb", { MX, EM }, PREFIX_OPCODE }, + { "paddusw", { MX, EM }, PREFIX_OPCODE }, + { "pmaxub", { MX, EM }, PREFIX_OPCODE }, + { "pandn", { MX, EM }, PREFIX_OPCODE }, /* e0 */ - { "pavgb", { MX, EM } }, - { "psraw", { MX, EM } }, - { "psrad", { MX, EM } }, - { "pavgw", { MX, EM } }, - { "pmulhuw", { MX, EM } }, - { "pmulhw", { MX, EM } }, + { "pavgb", { MX, EM }, PREFIX_OPCODE }, + { "psraw", { MX, EM }, PREFIX_OPCODE }, + { "psrad", { MX, EM }, PREFIX_OPCODE }, + { "pavgw", { MX, EM }, PREFIX_OPCODE }, + { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, + { "pmulhw", { MX, EM }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0FE6) }, { PREFIX_TABLE (PREFIX_0FE7) }, /* e8 */ - { "psubsb", { MX, EM } }, - { "psubsw", { MX, EM } }, - { "pminsw", { MX, EM } }, - { "por", { MX, EM } }, - { "paddsb", { MX, EM } }, - { "paddsw", { MX, EM } }, - { "pmaxsw", { MX, EM } }, - { "pxor", { MX, EM } }, + { "psubsb", { MX, EM }, PREFIX_OPCODE }, + { "psubsw", { MX, EM }, PREFIX_OPCODE }, + { "pminsw", { MX, EM }, PREFIX_OPCODE }, + { "por", { MX, EM }, PREFIX_OPCODE }, + { "paddsb", { MX, EM }, PREFIX_OPCODE }, + { "paddsw", { MX, EM }, PREFIX_OPCODE }, + { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, + { "pxor", { MX, EM }, PREFIX_OPCODE }, /* f0 */ { PREFIX_TABLE (PREFIX_0FF0) }, - { "psllw", { MX, EM } }, - { "pslld", { MX, EM } }, - { "psllq", { MX, EM } }, - { "pmuludq", { MX, EM } }, - { "pmaddwd", { MX, EM } }, - { "psadbw", { MX, EM } }, + { "psllw", { MX, EM }, PREFIX_OPCODE }, + { "pslld", { MX, EM }, PREFIX_OPCODE }, + { "psllq", { MX, EM }, PREFIX_OPCODE }, + { "pmuludq", { MX, EM }, PREFIX_OPCODE }, + { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, + { "psadbw", { MX, EM }, PREFIX_OPCODE }, { PREFIX_TABLE (PREFIX_0FF7) }, /* f8 */ - { "psubb", { MX, EM } }, - { "psubw", { MX, EM } }, - { "psubd", { MX, EM } }, - { "psubq", { MX, EM } }, - { "paddb", { MX, EM } }, - { "paddw", { MX, EM } }, - { "paddd", { MX, EM } }, + { "psubb", { MX, EM }, PREFIX_OPCODE }, + { "psubw", { MX, EM }, PREFIX_OPCODE }, + { "psubd", { MX, EM }, PREFIX_OPCODE }, + { "psubq", { MX, EM }, PREFIX_OPCODE }, + { "paddb", { MX, EM }, PREFIX_OPCODE }, + { "paddw", { MX, EM }, PREFIX_OPCODE }, + { "paddd", { MX, EM }, PREFIX_OPCODE }, { Bad_Opcode }, }; @@ -2846,6 +3139,7 @@ static char scratchbuf[100]; static unsigned char *start_codep; static unsigned char *insn_codep; static unsigned char *codep; +static unsigned char *end_codep; static int last_lock_prefix; static int last_repz_prefix; static int last_repnz_prefix; @@ -2853,6 +3147,9 @@ static int last_data_prefix; static int last_addr_prefix; static int last_rex_prefix; static int last_seg_prefix; +static int fwait_prefix; +/* The active segment register prefix. */ +static int active_seg_prefix; #define MAX_CODE_LENGTH 15 /* We can up to 14 prefixes since the maximum instruction length is 15bytes. */ @@ -3073,40 +3370,40 @@ static const char *names_rounding[] = static const struct dis386 reg_table[][8] = { /* REG_80 */ { - { "addA", { Ebh1, Ib } }, - { "orA", { Ebh1, Ib } }, - { "adcA", { Ebh1, Ib } }, - { "sbbA", { Ebh1, Ib } }, - { "andA", { Ebh1, Ib } }, - { "subA", { Ebh1, Ib } }, - { "xorA", { Ebh1, Ib } }, - { "cmpA", { Eb, Ib } }, + { "addA", { Ebh1, Ib }, 0 }, + { "orA", { Ebh1, Ib }, 0 }, + { "adcA", { Ebh1, Ib }, 0 }, + { "sbbA", { Ebh1, Ib }, 0 }, + { "andA", { Ebh1, Ib }, 0 }, + { "subA", { Ebh1, Ib }, 0 }, + { "xorA", { Ebh1, Ib }, 0 }, + { "cmpA", { Eb, Ib }, 0 }, }, /* REG_81 */ { - { "addQ", { Evh1, Iv } }, - { "orQ", { Evh1, Iv } }, - { "adcQ", { Evh1, Iv } }, - { "sbbQ", { Evh1, Iv } }, - { "andQ", { Evh1, Iv } }, - { "subQ", { Evh1, Iv } }, - { "xorQ", { Evh1, Iv } }, - { "cmpQ", { Ev, Iv } }, + { "addQ", { Evh1, Iv }, 0 }, + { "orQ", { Evh1, Iv }, 0 }, + { "adcQ", { Evh1, Iv }, 0 }, + { "sbbQ", { Evh1, Iv }, 0 }, + { "andQ", { Evh1, Iv }, 0 }, + { "subQ", { Evh1, Iv }, 0 }, + { "xorQ", { Evh1, Iv }, 0 }, + { "cmpQ", { Ev, Iv }, 0 }, }, /* REG_82 */ { - { "addQ", { Evh1, sIb } }, - { "orQ", { Evh1, sIb } }, - { "adcQ", { Evh1, sIb } }, - { "sbbQ", { Evh1, sIb } }, - { "andQ", { Evh1, sIb } }, - { "subQ", { Evh1, sIb } }, - { "xorQ", { Evh1, sIb } }, - { "cmpQ", { Ev, sIb } }, + { "addQ", { Evh1, sIb }, 0 }, + { "orQ", { Evh1, sIb }, 0 }, + { "adcQ", { Evh1, sIb }, 0 }, + { "sbbQ", { Evh1, sIb }, 0 }, + { "andQ", { Evh1, sIb }, 0 }, + { "subQ", { Evh1, sIb }, 0 }, + { "xorQ", { Evh1, sIb }, 0 }, + { "cmpQ", { Ev, sIb }, 0 }, }, /* REG_8F */ { - { "popU", { stackEv } }, + { "popU", { stackEv }, 0 }, { XOP_8F_TABLE (XOP_09) }, { Bad_Opcode }, { Bad_Opcode }, @@ -3115,29 +3412,29 @@ static const struct dis386 reg_table[][8] = { }, /* REG_C0 */ { - { "rolA", { Eb, Ib } }, - { "rorA", { Eb, Ib } }, - { "rclA", { Eb, Ib } }, - { "rcrA", { Eb, Ib } }, - { "shlA", { Eb, Ib } }, - { "shrA", { Eb, Ib } }, + { "rolA", { Eb, Ib }, 0 }, + { "rorA", { Eb, Ib }, 0 }, + { "rclA", { Eb, Ib }, 0 }, + { "rcrA", { Eb, Ib }, 0 }, + { "shlA", { Eb, Ib }, 0 }, + { "shrA", { Eb, Ib }, 0 }, { Bad_Opcode }, - { "sarA", { Eb, Ib } }, + { "sarA", { Eb, Ib }, 0 }, }, /* REG_C1 */ { - { "rolQ", { Ev, Ib } }, - { "rorQ", { Ev, Ib } }, - { "rclQ", { Ev, Ib } }, - { "rcrQ", { Ev, Ib } }, - { "shlQ", { Ev, Ib } }, - { "shrQ", { Ev, Ib } }, + { "rolQ", { Ev, Ib }, 0 }, + { "rorQ", { Ev, Ib }, 0 }, + { "rclQ", { Ev, Ib }, 0 }, + { "rcrQ", { Ev, Ib }, 0 }, + { "shlQ", { Ev, Ib }, 0 }, + { "shrQ", { Ev, Ib }, 0 }, { Bad_Opcode }, - { "sarQ", { Ev, Ib } }, + { "sarQ", { Ev, Ib }, 0 }, }, /* REG_C6 */ { - { "movA", { Ebh3, Ib } }, + { "movA", { Ebh3, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -3148,7 +3445,7 @@ static const struct dis386 reg_table[][8] = { }, /* REG_C7 */ { - { "movQ", { Evh3, Iv } }, + { "movQ", { Evh3, Iv }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -3159,94 +3456,94 @@ static const struct dis386 reg_table[][8] = { }, /* REG_D0 */ { - { "rolA", { Eb, I1 } }, - { "rorA", { Eb, I1 } }, - { "rclA", { Eb, I1 } }, - { "rcrA", { Eb, I1 } }, - { "shlA", { Eb, I1 } }, - { "shrA", { Eb, I1 } }, + { "rolA", { Eb, I1 }, 0 }, + { "rorA", { Eb, I1 }, 0 }, + { "rclA", { Eb, I1 }, 0 }, + { "rcrA", { Eb, I1 }, 0 }, + { "shlA", { Eb, I1 }, 0 }, + { "shrA", { Eb, I1 }, 0 }, { Bad_Opcode }, - { "sarA", { Eb, I1 } }, + { "sarA", { Eb, I1 }, 0 }, }, /* REG_D1 */ { - { "rolQ", { Ev, I1 } }, - { "rorQ", { Ev, I1 } }, - { "rclQ", { Ev, I1 } }, - { "rcrQ", { Ev, I1 } }, - { "shlQ", { Ev, I1 } }, - { "shrQ", { Ev, I1 } }, + { "rolQ", { Ev, I1 }, 0 }, + { "rorQ", { Ev, I1 }, 0 }, + { "rclQ", { Ev, I1 }, 0 }, + { "rcrQ", { Ev, I1 }, 0 }, + { "shlQ", { Ev, I1 }, 0 }, + { "shrQ", { Ev, I1 }, 0 }, { Bad_Opcode }, - { "sarQ", { Ev, I1 } }, + { "sarQ", { Ev, I1 }, 0 }, }, /* REG_D2 */ { - { "rolA", { Eb, CL } }, - { "rorA", { Eb, CL } }, - { "rclA", { Eb, CL } }, - { "rcrA", { Eb, CL } }, - { "shlA", { Eb, CL } }, - { "shrA", { Eb, CL } }, + { "rolA", { Eb, CL }, 0 }, + { "rorA", { Eb, CL }, 0 }, + { "rclA", { Eb, CL }, 0 }, + { "rcrA", { Eb, CL }, 0 }, + { "shlA", { Eb, CL }, 0 }, + { "shrA", { Eb, CL }, 0 }, { Bad_Opcode }, - { "sarA", { Eb, CL } }, + { "sarA", { Eb, CL }, 0 }, }, /* REG_D3 */ { - { "rolQ", { Ev, CL } }, - { "rorQ", { Ev, CL } }, - { "rclQ", { Ev, CL } }, - { "rcrQ", { Ev, CL } }, - { "shlQ", { Ev, CL } }, - { "shrQ", { Ev, CL } }, + { "rolQ", { Ev, CL }, 0 }, + { "rorQ", { Ev, CL }, 0 }, + { "rclQ", { Ev, CL }, 0 }, + { "rcrQ", { Ev, CL }, 0 }, + { "shlQ", { Ev, CL }, 0 }, + { "shrQ", { Ev, CL }, 0 }, { Bad_Opcode }, - { "sarQ", { Ev, CL } }, + { "sarQ", { Ev, CL }, 0 }, }, /* REG_F6 */ { - { "testA", { Eb, Ib } }, + { "testA", { Eb, Ib }, 0 }, { Bad_Opcode }, - { "notA", { Ebh1 } }, - { "negA", { Ebh1 } }, - { "mulA", { Eb } }, /* Don't print the implicit %al register, */ - { "imulA", { Eb } }, /* to distinguish these opcodes from other */ - { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */ - { "idivA", { Eb } }, /* and idiv for consistency. */ + { "notA", { Ebh1 }, 0 }, + { "negA", { Ebh1 }, 0 }, + { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ + { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ + { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ + { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ }, /* REG_F7 */ { - { "testQ", { Ev, Iv } }, + { "testQ", { Ev, Iv }, 0 }, { Bad_Opcode }, - { "notQ", { Evh1 } }, - { "negQ", { Evh1 } }, - { "mulQ", { Ev } }, /* Don't print the implicit register. */ - { "imulQ", { Ev } }, - { "divQ", { Ev } }, - { "idivQ", { Ev } }, + { "notQ", { Evh1 }, 0 }, + { "negQ", { Evh1 }, 0 }, + { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ + { "imulQ", { Ev }, 0 }, + { "divQ", { Ev }, 0 }, + { "idivQ", { Ev }, 0 }, }, /* REG_FE */ { - { "incA", { Ebh1 } }, - { "decA", { Ebh1 } }, + { "incA", { Ebh1 }, 0 }, + { "decA", { Ebh1 }, 0 }, }, /* REG_FF */ { - { "incQ", { Evh1 } }, - { "decQ", { Evh1 } }, - { "call{T|}", { indirEv, BND } }, + { "incQ", { Evh1 }, 0 }, + { "decQ", { Evh1 }, 0 }, + { "call{T|}", { indirEv, BND }, 0 }, { MOD_TABLE (MOD_FF_REG_3) }, - { "jmp{T|}", { indirEv, BND } }, + { "jmp{T|}", { indirEv, BND }, 0 }, { MOD_TABLE (MOD_FF_REG_5) }, - { "pushU", { stackEv } }, + { "pushU", { stackEv }, 0 }, { Bad_Opcode }, }, /* REG_0F00 */ { - { "sldtD", { Sv } }, - { "strD", { Sv } }, - { "lldt", { Ew } }, - { "ltr", { Ew } }, - { "verr", { Ew } }, - { "verw", { Ew } }, + { "sldtD", { Sv }, 0 }, + { "strD", { Sv }, 0 }, + { "lldt", { Ew }, 0 }, + { "ltr", { Ew }, 0 }, + { "verr", { Ew }, 0 }, + { "verw", { Ew }, 0 }, { Bad_Opcode }, { Bad_Opcode }, }, @@ -3256,21 +3553,21 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F01_REG_1) }, { MOD_TABLE (MOD_0F01_REG_2) }, { MOD_TABLE (MOD_0F01_REG_3) }, - { "smswD", { Sv } }, + { "smswD", { Sv }, 0 }, { Bad_Opcode }, - { "lmsw", { Ew } }, + { "lmsw", { Ew }, 0 }, { MOD_TABLE (MOD_0F01_REG_7) }, }, /* REG_0F0D */ { - { "prefetch", { Mb } }, - { "prefetchw", { Mb } }, - { "prefetchwt1", { Mb } }, - { "prefetch", { Mb } }, - { "prefetch", { Mb } }, - { "prefetch", { Mb } }, - { "prefetch", { Mb } }, - { "prefetch", { Mb } }, + { "prefetch", { Mb }, 0 }, + { "prefetchw", { Mb }, 0 }, + { "prefetchwt1", { Mb }, 0 }, + { "prefetch", { Mb }, 0 }, + { "prefetch", { Mb }, 0 }, + { "prefetch", { Mb }, 0 }, + { "prefetch", { Mb }, 0 }, + { "prefetch", { Mb }, 0 }, }, /* REG_0F18 */ { @@ -3316,18 +3613,18 @@ static const struct dis386 reg_table[][8] = { }, /* REG_0FA6 */ { - { "montmul", { { OP_0f07, 0 } } }, - { "xsha1", { { OP_0f07, 0 } } }, - { "xsha256", { { OP_0f07, 0 } } }, + { "montmul", { { OP_0f07, 0 } }, 0 }, + { "xsha1", { { OP_0f07, 0 } }, 0 }, + { "xsha256", { { OP_0f07, 0 } }, 0 }, }, /* REG_0FA7 */ { - { "xstore-rng", { { OP_0f07, 0 } } }, - { "xcrypt-ecb", { { OP_0f07, 0 } } }, - { "xcrypt-cbc", { { OP_0f07, 0 } } }, - { "xcrypt-ctr", { { OP_0f07, 0 } } }, - { "xcrypt-cfb", { { OP_0f07, 0 } } }, - { "xcrypt-ofb", { { OP_0f07, 0 } } }, + { "xstore-rng", { { OP_0f07, 0 } }, 0 }, + { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, + { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, + { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, + { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, + { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, }, /* REG_0FAE */ { @@ -3346,15 +3643,15 @@ static const struct dis386 reg_table[][8] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "btQ", { Ev, Ib } }, - { "btsQ", { Evh1, Ib } }, - { "btrQ", { Evh1, Ib } }, - { "btcQ", { Evh1, Ib } }, + { "btQ", { Ev, Ib }, 0 }, + { "btsQ", { Evh1, Ib }, 0 }, + { "btrQ", { Evh1, Ib }, 0 }, + { "btcQ", { Evh1, Ib }, 0 }, }, /* REG_0FC7 */ { { Bad_Opcode }, - { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } }, + { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, { Bad_Opcode }, { MOD_TABLE (MOD_0FC7_REG_3) }, { MOD_TABLE (MOD_0FC7_REG_4) }, @@ -3409,34 +3706,34 @@ static const struct dis386 reg_table[][8] = { }, /* REG_XOP_LWPCB */ { - { "llwpcb", { { OP_LWPCB_E, 0 } } }, - { "slwpcb", { { OP_LWPCB_E, 0 } } }, + { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, + { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, }, /* REG_XOP_LWP */ { - { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } }, - { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } }, + { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, + { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, }, /* REG_XOP_TBM_01 */ { { Bad_Opcode }, - { "blcfill", { { OP_LWP_E, 0 }, Ev } }, - { "blsfill", { { OP_LWP_E, 0 }, Ev } }, - { "blcs", { { OP_LWP_E, 0 }, Ev } }, - { "tzmsk", { { OP_LWP_E, 0 }, Ev } }, - { "blcic", { { OP_LWP_E, 0 }, Ev } }, - { "blsic", { { OP_LWP_E, 0 }, Ev } }, - { "t1mskc", { { OP_LWP_E, 0 }, Ev } }, + { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, }, /* REG_XOP_TBM_02 */ { { Bad_Opcode }, - { "blcmsk", { { OP_LWP_E, 0 }, Ev } }, + { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "blci", { { OP_LWP_E, 0 }, Ev } }, + { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, }, #define NEED_REG_TABLE #include "i386-dis-evex.h" @@ -3446,64 +3743,65 @@ static const struct dis386 reg_table[][8] = { static const struct dis386 prefix_table[][4] = { /* PREFIX_90 */ { - { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, - { "pause", { XX } }, - { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } }, + { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, + { "pause", { XX }, 0 }, + { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, + { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, /* PREFIX_0F10 */ { - { "movups", { XM, EXx } }, - { "movss", { XM, EXd } }, - { "movupd", { XM, EXx } }, - { "movsd", { XM, EXq } }, + { "movups", { XM, EXx }, PREFIX_OPCODE }, + { "movss", { XM, EXd }, PREFIX_OPCODE }, + { "movupd", { XM, EXx }, PREFIX_OPCODE }, + { "movsd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F11 */ { - { "movups", { EXxS, XM } }, - { "movss", { EXdS, XM } }, - { "movupd", { EXxS, XM } }, - { "movsd", { EXqS, XM } }, + { "movups", { EXxS, XM }, PREFIX_OPCODE }, + { "movss", { EXdS, XM }, PREFIX_OPCODE }, + { "movupd", { EXxS, XM }, PREFIX_OPCODE }, + { "movsd", { EXqS, XM }, PREFIX_OPCODE }, }, /* PREFIX_0F12 */ { { MOD_TABLE (MOD_0F12_PREFIX_0) }, - { "movsldup", { XM, EXx } }, - { "movlpd", { XM, EXq } }, - { "movddup", { XM, EXq } }, + { "movsldup", { XM, EXx }, PREFIX_OPCODE }, + { "movlpd", { XM, EXq }, PREFIX_OPCODE }, + { "movddup", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F16 */ { { MOD_TABLE (MOD_0F16_PREFIX_0) }, - { "movshdup", { XM, EXx } }, - { "movhpd", { XM, EXq } }, + { "movshdup", { XM, EXx }, PREFIX_OPCODE }, + { "movhpd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F1A */ { { MOD_TABLE (MOD_0F1A_PREFIX_0) }, - { "bndcl", { Gbnd, Ev_bnd } }, - { "bndmov", { Gbnd, Ebnd } }, - { "bndcu", { Gbnd, Ev_bnd } }, + { "bndcl", { Gbnd, Ev_bnd }, 0 }, + { "bndmov", { Gbnd, Ebnd }, 0 }, + { "bndcu", { Gbnd, Ev_bnd }, 0 }, }, /* PREFIX_0F1B */ { { MOD_TABLE (MOD_0F1B_PREFIX_0) }, { MOD_TABLE (MOD_0F1B_PREFIX_1) }, - { "bndmov", { Ebnd, Gbnd } }, - { "bndcn", { Gbnd, Ev_bnd } }, + { "bndmov", { Ebnd, Gbnd }, 0 }, + { "bndcn", { Gbnd, Ev_bnd }, 0 }, }, /* PREFIX_0F2A */ { - { "cvtpi2ps", { XM, EMCq } }, - { "cvtsi2ss%LQ", { XM, Ev } }, - { "cvtpi2pd", { XM, EMCq } }, - { "cvtsi2sd%LQ", { XM, Ev } }, + { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, + { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, + { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, + { "cvtsi2sd%LQ", { XM, Ev }, 0 }, }, /* PREFIX_0F2B */ @@ -3516,325 +3814,353 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2C */ { - { "cvttps2pi", { MXC, EXq } }, - { "cvttss2siY", { Gv, EXd } }, - { "cvttpd2pi", { MXC, EXx } }, - { "cvttsd2siY", { Gv, EXq } }, + { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, + { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, + { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, + { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2D */ { - { "cvtps2pi", { MXC, EXq } }, - { "cvtss2siY", { Gv, EXd } }, - { "cvtpd2pi", { MXC, EXx } }, - { "cvtsd2siY", { Gv, EXq } }, + { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, + { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, + { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, + { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2E */ { - { "ucomiss",{ XM, EXd } }, + { "ucomiss",{ XM, EXd }, 0 }, { Bad_Opcode }, - { "ucomisd",{ XM, EXq } }, + { "ucomisd",{ XM, EXq }, 0 }, }, /* PREFIX_0F2F */ { - { "comiss", { XM, EXd } }, + { "comiss", { XM, EXd }, 0 }, { Bad_Opcode }, - { "comisd", { XM, EXq } }, + { "comisd", { XM, EXq }, 0 }, }, /* PREFIX_0F51 */ { - { "sqrtps", { XM, EXx } }, - { "sqrtss", { XM, EXd } }, - { "sqrtpd", { XM, EXx } }, - { "sqrtsd", { XM, EXq } }, + { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, + { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, + { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, + { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F52 */ { - { "rsqrtps",{ XM, EXx } }, - { "rsqrtss",{ XM, EXd } }, + { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, + { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, }, /* PREFIX_0F53 */ { - { "rcpps", { XM, EXx } }, - { "rcpss", { XM, EXd } }, + { "rcpps", { XM, EXx }, PREFIX_OPCODE }, + { "rcpss", { XM, EXd }, PREFIX_OPCODE }, }, /* PREFIX_0F58 */ { - { "addps", { XM, EXx } }, - { "addss", { XM, EXd } }, - { "addpd", { XM, EXx } }, - { "addsd", { XM, EXq } }, + { "addps", { XM, EXx }, PREFIX_OPCODE }, + { "addss", { XM, EXd }, PREFIX_OPCODE }, + { "addpd", { XM, EXx }, PREFIX_OPCODE }, + { "addsd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F59 */ { - { "mulps", { XM, EXx } }, - { "mulss", { XM, EXd } }, - { "mulpd", { XM, EXx } }, - { "mulsd", { XM, EXq } }, + { "mulps", { XM, EXx }, PREFIX_OPCODE }, + { "mulss", { XM, EXd }, PREFIX_OPCODE }, + { "mulpd", { XM, EXx }, PREFIX_OPCODE }, + { "mulsd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F5A */ { - { "cvtps2pd", { XM, EXq } }, - { "cvtss2sd", { XM, EXd } }, - { "cvtpd2ps", { XM, EXx } }, - { "cvtsd2ss", { XM, EXq } }, + { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, + { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, + { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, + { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F5B */ { - { "cvtdq2ps", { XM, EXx } }, - { "cvttps2dq", { XM, EXx } }, - { "cvtps2dq", { XM, EXx } }, + { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, + { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, + { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F5C */ { - { "subps", { XM, EXx } }, - { "subss", { XM, EXd } }, - { "subpd", { XM, EXx } }, - { "subsd", { XM, EXq } }, + { "subps", { XM, EXx }, PREFIX_OPCODE }, + { "subss", { XM, EXd }, PREFIX_OPCODE }, + { "subpd", { XM, EXx }, PREFIX_OPCODE }, + { "subsd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F5D */ { - { "minps", { XM, EXx } }, - { "minss", { XM, EXd } }, - { "minpd", { XM, EXx } }, - { "minsd", { XM, EXq } }, + { "minps", { XM, EXx }, PREFIX_OPCODE }, + { "minss", { XM, EXd }, PREFIX_OPCODE }, + { "minpd", { XM, EXx }, PREFIX_OPCODE }, + { "minsd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F5E */ { - { "divps", { XM, EXx } }, - { "divss", { XM, EXd } }, - { "divpd", { XM, EXx } }, - { "divsd", { XM, EXq } }, + { "divps", { XM, EXx }, PREFIX_OPCODE }, + { "divss", { XM, EXd }, PREFIX_OPCODE }, + { "divpd", { XM, EXx }, PREFIX_OPCODE }, + { "divsd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F5F */ { - { "maxps", { XM, EXx } }, - { "maxss", { XM, EXd } }, - { "maxpd", { XM, EXx } }, - { "maxsd", { XM, EXq } }, + { "maxps", { XM, EXx }, PREFIX_OPCODE }, + { "maxss", { XM, EXd }, PREFIX_OPCODE }, + { "maxpd", { XM, EXx }, PREFIX_OPCODE }, + { "maxsd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F60 */ { - { "punpcklbw",{ MX, EMd } }, + { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, { Bad_Opcode }, - { "punpcklbw",{ MX, EMx } }, + { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, }, /* PREFIX_0F61 */ { - { "punpcklwd",{ MX, EMd } }, + { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, { Bad_Opcode }, - { "punpcklwd",{ MX, EMx } }, + { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, }, /* PREFIX_0F62 */ { - { "punpckldq",{ MX, EMd } }, + { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, { Bad_Opcode }, - { "punpckldq",{ MX, EMx } }, + { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, }, /* PREFIX_0F6C */ { { Bad_Opcode }, { Bad_Opcode }, - { "punpcklqdq", { XM, EXx } }, + { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F6D */ { { Bad_Opcode }, { Bad_Opcode }, - { "punpckhqdq", { XM, EXx } }, + { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F6F */ { - { "movq", { MX, EM } }, - { "movdqu", { XM, EXx } }, - { "movdqa", { XM, EXx } }, + { "movq", { MX, EM }, PREFIX_OPCODE }, + { "movdqu", { XM, EXx }, PREFIX_OPCODE }, + { "movdqa", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F70 */ { - { "pshufw", { MX, EM, Ib } }, - { "pshufhw",{ XM, EXx, Ib } }, - { "pshufd", { XM, EXx, Ib } }, - { "pshuflw",{ XM, EXx, Ib } }, + { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, + { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, + { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, + { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F73_REG_3 */ { { Bad_Opcode }, { Bad_Opcode }, - { "psrldq", { XS, Ib } }, + { "psrldq", { XS, Ib }, 0 }, }, /* PREFIX_0F73_REG_7 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pslldq", { XS, Ib } }, + { "pslldq", { XS, Ib }, 0 }, }, /* PREFIX_0F78 */ { - {"vmread", { Em, Gm } }, + {"vmread", { Em, Gm }, 0 }, { Bad_Opcode }, - {"extrq", { XS, Ib, Ib } }, - {"insertq", { XM, XS, Ib, Ib } }, + {"extrq", { XS, Ib, Ib }, 0 }, + {"insertq", { XM, XS, Ib, Ib }, 0 }, }, /* PREFIX_0F79 */ { - {"vmwrite", { Gm, Em } }, + {"vmwrite", { Gm, Em }, 0 }, { Bad_Opcode }, - {"extrq", { XM, XS } }, - {"insertq", { XM, XS } }, + {"extrq", { XM, XS }, 0 }, + {"insertq", { XM, XS }, 0 }, }, /* PREFIX_0F7C */ { { Bad_Opcode }, { Bad_Opcode }, - { "haddpd", { XM, EXx } }, - { "haddps", { XM, EXx } }, + { "haddpd", { XM, EXx }, PREFIX_OPCODE }, + { "haddps", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F7D */ { { Bad_Opcode }, { Bad_Opcode }, - { "hsubpd", { XM, EXx } }, - { "hsubps", { XM, EXx } }, + { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, + { "hsubps", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F7E */ { - { "movK", { Edq, MX } }, - { "movq", { XM, EXq } }, - { "movK", { Edq, XM } }, + { "movK", { Edq, MX }, PREFIX_OPCODE }, + { "movq", { XM, EXq }, PREFIX_OPCODE }, + { "movK", { Edq, XM }, PREFIX_OPCODE }, }, /* PREFIX_0F7F */ { - { "movq", { EMS, MX } }, - { "movdqu", { EXxS, XM } }, - { "movdqa", { EXxS, XM } }, + { "movq", { EMS, MX }, PREFIX_OPCODE }, + { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, + { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, }, /* PREFIX_0FAE_REG_0 */ { { Bad_Opcode }, - { "rdfsbase", { Ev } }, + { "rdfsbase", { Ev }, 0 }, }, /* PREFIX_0FAE_REG_1 */ { { Bad_Opcode }, - { "rdgsbase", { Ev } }, + { "rdgsbase", { Ev }, 0 }, }, /* PREFIX_0FAE_REG_2 */ { { Bad_Opcode }, - { "wrfsbase", { Ev } }, + { "wrfsbase", { Ev }, 0 }, }, /* PREFIX_0FAE_REG_3 */ { { Bad_Opcode }, - { "wrgsbase", { Ev } }, + { "wrgsbase", { Ev }, 0 }, + }, + + /* PREFIX_0FAE_REG_6 */ + { + { "xsaveopt", { FXSAVE }, 0 }, + { Bad_Opcode }, + { "clwb", { Mb }, 0 }, }, /* PREFIX_0FAE_REG_7 */ { - { "clflush", { Mb } }, + { "clflush", { Mb }, 0 }, { Bad_Opcode }, - { "clflushopt", { Mb } }, + { "clflushopt", { Mb }, 0 }, + }, + + /* PREFIX_RM_0_0FAE_REG_7 */ + { + { "sfence", { Skip_MODRM }, 0 }, + { Bad_Opcode }, + { "pcommit", { Skip_MODRM }, 0 }, }, /* PREFIX_0FB8 */ { { Bad_Opcode }, - { "popcntS", { Gv, Ev } }, + { "popcntS", { Gv, Ev }, 0 }, }, /* PREFIX_0FBC */ { - { "bsfS", { Gv, Ev } }, - { "tzcntS", { Gv, Ev } }, - { "bsfS", { Gv, Ev } }, + { "bsfS", { Gv, Ev }, 0 }, + { "tzcntS", { Gv, Ev }, 0 }, + { "bsfS", { Gv, Ev }, 0 }, }, /* PREFIX_0FBD */ { - { "bsrS", { Gv, Ev } }, - { "lzcntS", { Gv, Ev } }, - { "bsrS", { Gv, Ev } }, + { "bsrS", { Gv, Ev }, 0 }, + { "lzcntS", { Gv, Ev }, 0 }, + { "bsrS", { Gv, Ev }, 0 }, }, /* PREFIX_0FC2 */ { - { "cmpps", { XM, EXx, CMP } }, - { "cmpss", { XM, EXd, CMP } }, - { "cmppd", { XM, EXx, CMP } }, - { "cmpsd", { XM, EXq, CMP } }, + { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, + { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, + { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, + { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, + }, + + /* PREFIX_MOD_0_0FC3 */ + { + { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, + }, + + /* PREFIX_MOD_0_0FC7_REG_6 */ + { + { "vmptrld",{ Mq }, 0 }, + { "vmxon", { Mq }, 0 }, + { "vmclear",{ Mq }, 0 }, }, - /* PREFIX_0FC3 */ + /* PREFIX_MOD_3_0FC7_REG_6 */ { - { "movntiS", { Ma, Gv } }, + { "rdrand", { Ev }, 0 }, + { Bad_Opcode }, + { "rdrand", { Ev }, 0 } }, - /* PREFIX_0FC7_REG_6 */ + /* PREFIX_MOD_3_0FC7_REG_7 */ { - { "vmptrld",{ Mq } }, - { "vmxon", { Mq } }, - { "vmclear",{ Mq } }, + { "rdseed", { Ev }, 0 }, + { Bad_Opcode }, + { "rdseed", { Ev }, 0 }, }, /* PREFIX_0FD0 */ { { Bad_Opcode }, { Bad_Opcode }, - { "addsubpd", { XM, EXx } }, - { "addsubps", { XM, EXx } }, + { "addsubpd", { XM, EXx }, 0 }, + { "addsubps", { XM, EXx }, 0 }, }, /* PREFIX_0FD6 */ { { Bad_Opcode }, - { "movq2dq",{ XM, MS } }, - { "movq", { EXqS, XM } }, - { "movdq2q",{ MX, XS } }, + { "movq2dq",{ XM, MS }, 0 }, + { "movq", { EXqS, XM }, 0 }, + { "movdq2q",{ MX, XS }, 0 }, }, /* PREFIX_0FE6 */ { { Bad_Opcode }, - { "cvtdq2pd", { XM, EXq } }, - { "cvttpd2dq", { XM, EXx } }, - { "cvtpd2dq", { XM, EXx } }, + { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, + { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, + { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0FE7 */ { - { "movntq", { Mq, MX } }, + { "movntq", { Mq, MX }, PREFIX_OPCODE }, { Bad_Opcode }, { MOD_TABLE (MOD_0FE7_PREFIX_2) }, }, @@ -3849,93 +4175,93 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0FF7 */ { - { "maskmovq", { MX, MS } }, + { "maskmovq", { MX, MS }, PREFIX_OPCODE }, { Bad_Opcode }, - { "maskmovdqu", { XM, XS } }, + { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, }, /* PREFIX_0F3810 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pblendvb", { XM, EXx, XMM0 } }, + { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, }, /* PREFIX_0F3814 */ { { Bad_Opcode }, { Bad_Opcode }, - { "blendvps", { XM, EXx, XMM0 } }, + { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, }, /* PREFIX_0F3815 */ { { Bad_Opcode }, { Bad_Opcode }, - { "blendvpd", { XM, EXx, XMM0 } }, + { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, }, /* PREFIX_0F3817 */ { { Bad_Opcode }, { Bad_Opcode }, - { "ptest", { XM, EXx } }, + { "ptest", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F3820 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovsxbw", { XM, EXq } }, + { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F3821 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovsxbd", { XM, EXd } }, + { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, }, /* PREFIX_0F3822 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovsxbq", { XM, EXw } }, + { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, }, /* PREFIX_0F3823 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovsxwd", { XM, EXq } }, + { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F3824 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovsxwq", { XM, EXd } }, + { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, }, /* PREFIX_0F3825 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovsxdq", { XM, EXq } }, + { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F3828 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmuldq", { XM, EXx } }, + { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F3829 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpeqq", { XM, EXx } }, + { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F382A */ @@ -3949,235 +4275,235 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "packusdw", { XM, EXx } }, + { "packusdw", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F3830 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovzxbw", { XM, EXq } }, + { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F3831 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovzxbd", { XM, EXd } }, + { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, }, /* PREFIX_0F3832 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovzxbq", { XM, EXw } }, + { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, }, /* PREFIX_0F3833 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovzxwd", { XM, EXq } }, + { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F3834 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovzxwq", { XM, EXd } }, + { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, }, /* PREFIX_0F3835 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmovzxdq", { XM, EXq } }, + { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F3837 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpgtq", { XM, EXx } }, + { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F3838 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pminsb", { XM, EXx } }, + { "pminsb", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F3839 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pminsd", { XM, EXx } }, + { "pminsd", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F383A */ { { Bad_Opcode }, { Bad_Opcode }, - { "pminuw", { XM, EXx } }, + { "pminuw", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F383B */ { { Bad_Opcode }, { Bad_Opcode }, - { "pminud", { XM, EXx } }, + { "pminud", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F383C */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmaxsb", { XM, EXx } }, + { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F383D */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmaxsd", { XM, EXx } }, + { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F383E */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmaxuw", { XM, EXx } }, + { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F383F */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmaxud", { XM, EXx } }, + { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F3840 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pmulld", { XM, EXx } }, + { "pmulld", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F3841 */ { { Bad_Opcode }, { Bad_Opcode }, - { "phminposuw", { XM, EXx } }, + { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F3880 */ { { Bad_Opcode }, { Bad_Opcode }, - { "invept", { Gm, Mo } }, + { "invept", { Gm, Mo }, PREFIX_OPCODE }, }, /* PREFIX_0F3881 */ { { Bad_Opcode }, { Bad_Opcode }, - { "invvpid", { Gm, Mo } }, + { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, }, /* PREFIX_0F3882 */ { { Bad_Opcode }, { Bad_Opcode }, - { "invpcid", { Gm, M } }, + { "invpcid", { Gm, M }, PREFIX_OPCODE }, }, /* PREFIX_0F38C8 */ { - { "sha1nexte", { XM, EXxmm } }, + { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, }, /* PREFIX_0F38C9 */ { - { "sha1msg1", { XM, EXxmm } }, + { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, }, /* PREFIX_0F38CA */ { - { "sha1msg2", { XM, EXxmm } }, + { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, }, /* PREFIX_0F38CB */ { - { "sha256rnds2", { XM, EXxmm, XMM0 } }, + { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, }, /* PREFIX_0F38CC */ { - { "sha256msg1", { XM, EXxmm } }, + { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, }, /* PREFIX_0F38CD */ { - { "sha256msg2", { XM, EXxmm } }, + { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, }, /* PREFIX_0F38DB */ { { Bad_Opcode }, { Bad_Opcode }, - { "aesimc", { XM, EXx } }, + { "aesimc", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F38DC */ { { Bad_Opcode }, { Bad_Opcode }, - { "aesenc", { XM, EXx } }, + { "aesenc", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F38DD */ { { Bad_Opcode }, { Bad_Opcode }, - { "aesenclast", { XM, EXx } }, + { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F38DE */ { { Bad_Opcode }, { Bad_Opcode }, - { "aesdec", { XM, EXx } }, + { "aesdec", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F38DF */ { { Bad_Opcode }, { Bad_Opcode }, - { "aesdeclast", { XM, EXx } }, + { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, }, /* PREFIX_0F38F0 */ { - { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, + { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, { Bad_Opcode }, - { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } }, - { "crc32", { Gdq, { CRC32_Fixup, b_mode } } }, + { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, + { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, }, /* PREFIX_0F38F1 */ { - { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, + { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, { Bad_Opcode }, - { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } }, - { "crc32", { Gdq, { CRC32_Fixup, v_mode } } }, + { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, + { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, }, /* PREFIX_0F38F6 */ { { Bad_Opcode }, - { "adoxS", { Gdq, Edq} }, - { "adcxS", { Gdq, Edq} }, + { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, + { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, { Bad_Opcode }, }, @@ -4185,166 +4511,166 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "roundps", { XM, EXx, Ib } }, + { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A09 */ { { Bad_Opcode }, { Bad_Opcode }, - { "roundpd", { XM, EXx, Ib } }, + { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A0A */ { { Bad_Opcode }, { Bad_Opcode }, - { "roundss", { XM, EXd, Ib } }, + { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A0B */ { { Bad_Opcode }, { Bad_Opcode }, - { "roundsd", { XM, EXq, Ib } }, + { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A0C */ { { Bad_Opcode }, { Bad_Opcode }, - { "blendps", { XM, EXx, Ib } }, + { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A0D */ { { Bad_Opcode }, { Bad_Opcode }, - { "blendpd", { XM, EXx, Ib } }, + { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A0E */ { { Bad_Opcode }, { Bad_Opcode }, - { "pblendw", { XM, EXx, Ib } }, + { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A14 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pextrb", { Edqb, XM, Ib } }, + { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A15 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pextrw", { Edqw, XM, Ib } }, + { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A16 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pextrK", { Edq, XM, Ib } }, + { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A17 */ { { Bad_Opcode }, { Bad_Opcode }, - { "extractps", { Edqd, XM, Ib } }, + { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A20 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pinsrb", { XM, Edqb, Ib } }, + { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A21 */ { { Bad_Opcode }, { Bad_Opcode }, - { "insertps", { XM, EXd, Ib } }, + { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A22 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pinsrK", { XM, Edq, Ib } }, + { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A40 */ { { Bad_Opcode }, { Bad_Opcode }, - { "dpps", { XM, EXx, Ib } }, + { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A41 */ { { Bad_Opcode }, { Bad_Opcode }, - { "dppd", { XM, EXx, Ib } }, + { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A42 */ { { Bad_Opcode }, { Bad_Opcode }, - { "mpsadbw", { XM, EXx, Ib } }, + { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A44 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pclmulqdq", { XM, EXx, PCLMUL } }, + { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, }, /* PREFIX_0F3A60 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpestrm", { XM, EXx, Ib } }, + { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A61 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpestri", { XM, EXx, Ib } }, + { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A62 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpistrm", { XM, EXx, Ib } }, + { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A63 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpistri", { XM, EXx, Ib } }, + { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3ACC */ { - { "sha1rnds4", { XM, EXxmm, Ib } }, + { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3ADF */ { { Bad_Opcode }, { Bad_Opcode }, - { "aeskeygenassist", { XM, EXx, Ib } }, + { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, }, /* PREFIX_VEX_0F10 */ @@ -4419,36 +4745,55 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F41 */ { { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, }, /* PREFIX_VEX_0F42 */ { { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, }, /* PREFIX_VEX_0F44 */ { { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, }, /* PREFIX_VEX_0F45 */ { { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, }, /* PREFIX_VEX_0F46 */ { { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, }, /* PREFIX_VEX_0F47 */ { { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, }, - /* PREFIX_VEX_0F4B */ + /* PREFIX_VEX_0F4A */ { + { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, + }, + + /* PREFIX_VEX_0F4B */ + { + { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, { Bad_Opcode }, { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, }, @@ -4493,7 +4838,7 @@ static const struct dis386 prefix_table[][4] = { { { VEX_W_TABLE (VEX_W_0F5A_P_0) }, { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, - { "vcvtpd2ps%XY", { XMM, EXx } }, + { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, }, @@ -4785,26 +5130,45 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F90 */ { { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, }, /* PREFIX_VEX_0F91 */ { { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, }, /* PREFIX_VEX_0F92 */ { { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, }, /* PREFIX_VEX_0F93 */ { { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, + { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, }, /* PREFIX_VEX_0F98 */ { { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, + }, + + /* PREFIX_VEX_0F99 */ + { + { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, }, /* PREFIX_VEX_0FC2 */ @@ -5277,7 +5641,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vcvtph2ps", { XM, EXxmmq } }, + { "vcvtph2ps", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3816 */ @@ -5564,7 +5928,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vpsrlv%LW", { XM, Vex, EXx } }, + { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3846 */ @@ -5578,7 +5942,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vpsllv%LW", { XM, Vex, EXx } }, + { "vpsllv%LW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3858 */ @@ -5634,105 +5998,105 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } }, + { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, }, /* PREFIX_VEX_0F3891 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, + { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, }, /* PREFIX_VEX_0F3892 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } }, + { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, }, /* PREFIX_VEX_0F3893 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } }, + { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, }, /* PREFIX_VEX_0F3896 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub132p%XW", { XM, Vex, EXx } }, + { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3897 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubadd132p%XW", { XM, Vex, EXx } }, + { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3898 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmadd132p%XW", { XM, Vex, EXx } }, + { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3899 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F389A */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsub132p%XW", { XM, Vex, EXx } }, + { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F389B */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F389C */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmadd132p%XW", { XM, Vex, EXx } }, + { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F389D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F389E */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsub132p%XW", { XM, Vex, EXx } }, + { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F389F */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38A6 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub213p%XW", { XM, Vex, EXx } }, + { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, { Bad_Opcode }, }, @@ -5740,133 +6104,133 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubadd213p%XW", { XM, Vex, EXx } }, + { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38A8 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmadd213p%XW", { XM, Vex, EXx } }, + { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38A9 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38AA */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsub213p%XW", { XM, Vex, EXx } }, + { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38AB */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38AC */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmadd213p%XW", { XM, Vex, EXx } }, + { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38AD */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38AE */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsub213p%XW", { XM, Vex, EXx } }, + { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38AF */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38B6 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub231p%XW", { XM, Vex, EXx } }, + { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38B7 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubadd231p%XW", { XM, Vex, EXx } }, + { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38B8 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmadd231p%XW", { XM, Vex, EXx } }, + { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38B9 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38BA */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsub231p%XW", { XM, Vex, EXx } }, + { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38BB */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38BC */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmadd231p%XW", { XM, Vex, EXx } }, + { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38BD */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38BE */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsub231p%XW", { XM, Vex, EXx } }, + { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38BF */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } }, + { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, /* PREFIX_VEX_0F38DB */ @@ -6092,7 +6456,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vcvtps2ph", { EXxmmq, XM, Ib } }, + { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, }, /* PREFIX_VEX_0F3A20 */ @@ -6123,6 +6487,13 @@ static const struct dis386 prefix_table[][4] = { { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, }, + /* PREFIX_VEX_0F3A31 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, + }, + /* PREFIX_VEX_0F3A32 */ { { Bad_Opcode }, @@ -6130,6 +6501,13 @@ static const struct dis386 prefix_table[][4] = { { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, }, + /* PREFIX_VEX_0F3A33 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, + }, + /* PREFIX_VEX_0F3A38 */ { { Bad_Opcode }, @@ -6218,28 +6596,28 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A5D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A5E */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A5F */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A60 */ @@ -6275,14 +6653,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A69 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A6A */ @@ -6303,14 +6681,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A6D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A6E */ @@ -6331,14 +6709,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A79 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A7A */ @@ -6359,7 +6737,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, }, @@ -6367,7 +6745,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, }, /* PREFIX_VEX_0F3A7E */ @@ -6407,67 +6785,67 @@ static const struct dis386 prefix_table[][4] = { static const struct dis386 x86_64_table[][2] = { /* X86_64_06 */ { - { "pushP", { es } }, + { "pushP", { es }, 0 }, }, /* X86_64_07 */ { - { "popP", { es } }, + { "popP", { es }, 0 }, }, /* X86_64_0D */ { - { "pushP", { cs } }, + { "pushP", { cs }, 0 }, }, /* X86_64_16 */ { - { "pushP", { ss } }, + { "pushP", { ss }, 0 }, }, /* X86_64_17 */ { - { "popP", { ss } }, + { "popP", { ss }, 0 }, }, /* X86_64_1E */ { - { "pushP", { ds } }, + { "pushP", { ds }, 0 }, }, /* X86_64_1F */ { - { "popP", { ds } }, + { "popP", { ds }, 0 }, }, /* X86_64_27 */ { - { "daa", { XX } }, + { "daa", { XX }, 0 }, }, /* X86_64_2F */ { - { "das", { XX } }, + { "das", { XX }, 0 }, }, /* X86_64_37 */ { - { "aaa", { XX } }, + { "aaa", { XX }, 0 }, }, /* X86_64_3F */ { - { "aas", { XX } }, + { "aas", { XX }, 0 }, }, /* X86_64_60 */ { - { "pushaP", { XX } }, + { "pushaP", { XX }, 0 }, }, /* X86_64_61 */ { - { "popaP", { XX } }, + { "popaP", { XX }, 0 }, }, /* X86_64_62 */ @@ -6478,25 +6856,25 @@ static const struct dis386 x86_64_table[][2] = { /* X86_64_63 */ { - { "arpl", { Ew, Gw } }, - { "movs{lq|xd}", { Gv, Ed } }, + { "arpl", { Ew, Gw }, 0 }, + { "movs{lq|xd}", { Gv, Ed }, 0 }, }, /* X86_64_6D */ { - { "ins{R|}", { Yzr, indirDX } }, - { "ins{G|}", { Yzr, indirDX } }, + { "ins{R|}", { Yzr, indirDX }, 0 }, + { "ins{G|}", { Yzr, indirDX }, 0 }, }, /* X86_64_6F */ { - { "outs{R|}", { indirDXr, Xz } }, - { "outs{G|}", { indirDXr, Xz } }, + { "outs{R|}", { indirDXr, Xz }, 0 }, + { "outs{G|}", { indirDXr, Xz }, 0 }, }, /* X86_64_9A */ { - { "Jcall{T|}", { Ap } }, + { "Jcall{T|}", { Ap }, 0 }, }, /* X86_64_C4 */ @@ -6513,46 +6891,58 @@ static const struct dis386 x86_64_table[][2] = { /* X86_64_CE */ { - { "into", { XX } }, + { "into", { XX }, 0 }, }, /* X86_64_D4 */ { - { "aam", { Ib } }, + { "aam", { Ib }, 0 }, }, /* X86_64_D5 */ { - { "aad", { Ib } }, + { "aad", { Ib }, 0 }, + }, + + /* X86_64_E8 */ + { + { "callP", { Jv, BND }, 0 }, + { "call@", { Jv, BND }, 0 } + }, + + /* X86_64_E9 */ + { + { "jmpP", { Jv, BND }, 0 }, + { "jmp@", { Jv, BND }, 0 } }, /* X86_64_EA */ { - { "Jjmp{T|}", { Ap } }, + { "Jjmp{T|}", { Ap }, 0 }, }, /* X86_64_0F01_REG_0 */ { - { "sgdt{Q|IQ}", { M } }, - { "sgdt", { M } }, + { "sgdt{Q|IQ}", { M }, 0 }, + { "sgdt", { M }, 0 }, }, /* X86_64_0F01_REG_1 */ { - { "sidt{Q|IQ}", { M } }, - { "sidt", { M } }, + { "sidt{Q|IQ}", { M }, 0 }, + { "sidt", { M }, 0 }, }, /* X86_64_0F01_REG_2 */ { - { "lgdt{Q|Q}", { M } }, - { "lgdt", { M } }, + { "lgdt{Q|Q}", { M }, 0 }, + { "lgdt", { M }, 0 }, }, /* X86_64_0F01_REG_3 */ { - { "lidt{Q|Q}", { M } }, - { "lidt", { M } }, + { "lidt{Q|Q}", { M }, 0 }, + { "lidt", { M }, 0 }, }, }; @@ -6561,19 +6951,19 @@ static const struct dis386 three_byte_table[][256] = { /* THREE_BYTE_0F38 */ { /* 00 */ - { "pshufb", { MX, EM } }, - { "phaddw", { MX, EM } }, - { "phaddd", { MX, EM } }, - { "phaddsw", { MX, EM } }, - { "pmaddubsw", { MX, EM } }, - { "phsubw", { MX, EM } }, - { "phsubd", { MX, EM } }, - { "phsubsw", { MX, EM } }, + { "pshufb", { MX, EM }, PREFIX_OPCODE }, + { "phaddw", { MX, EM }, PREFIX_OPCODE }, + { "phaddd", { MX, EM }, PREFIX_OPCODE }, + { "phaddsw", { MX, EM }, PREFIX_OPCODE }, + { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, + { "phsubw", { MX, EM }, PREFIX_OPCODE }, + { "phsubd", { MX, EM }, PREFIX_OPCODE }, + { "phsubsw", { MX, EM }, PREFIX_OPCODE }, /* 08 */ - { "psignb", { MX, EM } }, - { "psignw", { MX, EM } }, - { "psignd", { MX, EM } }, - { "pmulhrsw", { MX, EM } }, + { "psignb", { MX, EM }, PREFIX_OPCODE }, + { "psignw", { MX, EM }, PREFIX_OPCODE }, + { "psignd", { MX, EM }, PREFIX_OPCODE }, + { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -6592,9 +6982,9 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "pabsb", { MX, EM } }, - { "pabsw", { MX, EM } }, - { "pabsd", { MX, EM } }, + { "pabsb", { MX, EM }, PREFIX_OPCODE }, + { "pabsw", { MX, EM }, PREFIX_OPCODE }, + { "pabsd", { MX, EM }, PREFIX_OPCODE }, { Bad_Opcode }, /* 20 */ { PREFIX_TABLE (PREFIX_0F3820) }, @@ -6868,7 +7258,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F3A0C) }, { PREFIX_TABLE (PREFIX_0F3A0D) }, { PREFIX_TABLE (PREFIX_0F3A0E) }, - { "palignr", { MX, EM, Ib } }, + { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, /* 10 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7180,7 +7570,7 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 20 */ - { "ptest", { XX } }, + { "ptest", { XX }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7217,45 +7607,45 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, /* 40 */ { Bad_Opcode }, - { "phaddbw", { XM, EXq } }, - { "phaddbd", { XM, EXq } }, - { "phaddbq", { XM, EXq } }, + { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, + { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, + { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, - { "phaddwd", { XM, EXq } }, - { "phaddwq", { XM, EXq } }, + { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, + { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, /* 48 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "phadddq", { XM, EXq } }, + { "phadddq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 50 */ { Bad_Opcode }, - { "phaddubw", { XM, EXq } }, - { "phaddubd", { XM, EXq } }, - { "phaddubq", { XM, EXq } }, + { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, + { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, + { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, - { "phadduwd", { XM, EXq } }, - { "phadduwq", { XM, EXq } }, + { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, + { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, /* 58 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "phaddudq", { XM, EXq } }, + { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 60 */ { Bad_Opcode }, - { "phsubbw", { XM, EXq } }, - { "phsubbd", { XM, EXq } }, - { "phsubbq", { XM, EXq } }, + { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, + { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, + { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7587,9 +7977,9 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, - { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, - { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, /* 88 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7597,17 +7987,17 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, - { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, - { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, - { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, /* 98 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7615,16 +8005,16 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, - { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, /* a0 */ { Bad_Opcode }, { Bad_Opcode }, - { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, - { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, /* a8 */ { Bad_Opcode }, @@ -7642,7 +8032,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } }, + { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, /* b8 */ { Bad_Opcode }, @@ -7654,10 +8044,10 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* c0 */ - { "vprotb", { XM, Vex_2src_1, Ib } }, - { "vprotw", { XM, Vex_2src_1, Ib } }, - { "vprotd", { XM, Vex_2src_1, Ib } }, - { "vprotq", { XM, Vex_2src_1, Ib } }, + { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7875,8 +8265,8 @@ static const struct dis386 xop_table[][256] = { /* 80 */ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, - { "vfrczss", { XM, EXd } }, - { "vfrczsd", { XM, EXq } }, + { "vfrczss", { XM, EXd }, 0 }, + { "vfrczsd", { XM, EXq }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7891,19 +8281,19 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 90 */ - { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, /* 98 */ - { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } }, - { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } }, + { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7946,45 +8336,45 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, /* c0 */ { Bad_Opcode }, - { "vphaddbw", { XM, EXxmm } }, - { "vphaddbd", { XM, EXxmm } }, - { "vphaddbq", { XM, EXxmm } }, + { "vphaddbw", { XM, EXxmm }, 0 }, + { "vphaddbd", { XM, EXxmm }, 0 }, + { "vphaddbq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vphaddwd", { XM, EXxmm } }, - { "vphaddwq", { XM, EXxmm } }, + { "vphaddwd", { XM, EXxmm }, 0 }, + { "vphaddwq", { XM, EXxmm }, 0 }, /* c8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vphadddq", { XM, EXxmm } }, + { "vphadddq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* d0 */ { Bad_Opcode }, - { "vphaddubw", { XM, EXxmm } }, - { "vphaddubd", { XM, EXxmm } }, - { "vphaddubq", { XM, EXxmm } }, + { "vphaddubw", { XM, EXxmm }, 0 }, + { "vphaddubd", { XM, EXxmm }, 0 }, + { "vphaddubq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vphadduwd", { XM, EXxmm } }, - { "vphadduwq", { XM, EXxmm } }, + { "vphadduwd", { XM, EXxmm }, 0 }, + { "vphadduwq", { XM, EXxmm }, 0 }, /* d8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vphaddudq", { XM, EXxmm } }, + { "vphaddudq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* e0 */ { Bad_Opcode }, - { "vphsubbw", { XM, EXxmm } }, - { "vphsubwd", { XM, EXxmm } }, - { "vphsubdq", { XM, EXxmm } }, + { "vphsubbw", { XM, EXxmm }, 0 }, + { "vphsubwd", { XM, EXxmm }, 0 }, + { "vphsubdq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8038,7 +8428,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { "bextr", { Gv, Ev, Iq } }, + { "bextr", { Gv, Ev, Iq }, 0 }, { Bad_Opcode }, { REG_TABLE (REG_XOP_LWP) }, { Bad_Opcode }, @@ -8397,7 +8787,7 @@ static const struct dis386 vex_table[][256] = { /* 48 */ { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F4A) }, { PREFIX_TABLE (PREFIX_VEX_0F4B) }, { Bad_Opcode }, { Bad_Opcode }, @@ -8408,10 +8798,10 @@ static const struct dis386 vex_table[][256] = { { PREFIX_TABLE (PREFIX_VEX_0F51) }, { PREFIX_TABLE (PREFIX_VEX_0F52) }, { PREFIX_TABLE (PREFIX_VEX_0F53) }, - { "vandpX", { XM, Vex, EXx } }, - { "vandnpX", { XM, Vex, EXx } }, - { "vorpX", { XM, Vex, EXx } }, - { "vxorpX", { XM, Vex, EXx } }, + { "vandpX", { XM, Vex, EXx }, 0 }, + { "vandnpX", { XM, Vex, EXx }, 0 }, + { "vorpX", { XM, Vex, EXx }, 0 }, + { "vxorpX", { XM, Vex, EXx }, 0 }, /* 58 */ { PREFIX_TABLE (PREFIX_VEX_0F58) }, { PREFIX_TABLE (PREFIX_VEX_0F59) }, @@ -8486,7 +8876,7 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, /* 98 */ { PREFIX_TABLE (PREFIX_VEX_0F98) }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F99) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8536,7 +8926,7 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_VEX_0FC4) }, { PREFIX_TABLE (PREFIX_VEX_0FC5) }, - { "vshufpX", { XM, Vex, EXx, Ib } }, + { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, { Bad_Opcode }, /* c8 */ { Bad_Opcode }, @@ -8951,9 +9341,9 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, /* 30 */ { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9256,38 +9646,38 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F2A_P_1 */ { - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, }, /* VEX_LEN_0F2A_P_3 */ { - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, }, /* VEX_LEN_0F2C_P_1 */ { - { "vcvttss2siY", { Gv, EXdScalar } }, - { "vcvttss2siY", { Gv, EXdScalar } }, + { "vcvttss2siY", { Gv, EXdScalar }, 0 }, + { "vcvttss2siY", { Gv, EXdScalar }, 0 }, }, /* VEX_LEN_0F2C_P_3 */ { - { "vcvttsd2siY", { Gv, EXqScalar } }, - { "vcvttsd2siY", { Gv, EXqScalar } }, + { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, + { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, }, /* VEX_LEN_0F2D_P_1 */ { - { "vcvtss2siY", { Gv, EXdScalar } }, - { "vcvtss2siY", { Gv, EXdScalar } }, + { "vcvtss2siY", { Gv, EXdScalar }, 0 }, + { "vcvtss2siY", { Gv, EXdScalar }, 0 }, }, /* VEX_LEN_0F2D_P_3 */ { - { "vcvtsd2siY", { Gv, EXqScalar } }, - { "vcvtsd2siY", { Gv, EXqScalar } }, + { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, + { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, }, /* VEX_LEN_0F2E_P_0 */ @@ -9319,30 +9709,74 @@ static const struct dis386 vex_len_table[][2] = { { Bad_Opcode }, { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, }, + /* VEX_LEN_0F41_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, + }, /* VEX_LEN_0F42_P_0 */ { { Bad_Opcode }, { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, }, + /* VEX_LEN_0F42_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, + }, /* VEX_LEN_0F44_P_0 */ { { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, }, + /* VEX_LEN_0F44_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, + }, /* VEX_LEN_0F45_P_0 */ { { Bad_Opcode }, { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, }, + /* VEX_LEN_0F45_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, + }, /* VEX_LEN_0F46_P_0 */ { { Bad_Opcode }, { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, }, + /* VEX_LEN_0F46_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, + }, /* VEX_LEN_0F47_P_0 */ { { Bad_Opcode }, { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, }, + /* VEX_LEN_0F47_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, + }, + /* VEX_LEN_0F4A_P_0 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, + }, + /* VEX_LEN_0F4A_P_2 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, + }, + /* VEX_LEN_0F4B_P_0 */ + { + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, + }, /* VEX_LEN_0F4B_P_2 */ { { Bad_Opcode }, @@ -9459,8 +9893,8 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F6E_P_2 */ { - { "vmovK", { XMScalar, Edq } }, - { "vmovK", { XMScalar, Edq } }, + { "vmovK", { XMScalar, Edq }, 0 }, + { "vmovK", { XMScalar, Edq }, 0 }, }, /* VEX_LEN_0F7E_P_1 */ @@ -9471,8 +9905,8 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F7E_P_2 */ { - { "vmovK", { Edq, XMScalar } }, - { "vmovK", { Edq, XMScalar } }, + { "vmovK", { Edq, XMScalar }, 0 }, + { "vmovK", { Edq, XMScalar }, 0 }, }, /* VEX_LEN_0F90_P_0 */ @@ -9480,26 +9914,71 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, }, + /* VEX_LEN_0F90_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, + }, + /* VEX_LEN_0F91_P_0 */ { { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, }, + /* VEX_LEN_0F91_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, + }, + /* VEX_LEN_0F92_P_0 */ { { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, }, + /* VEX_LEN_0F92_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, + }, + + /* VEX_LEN_0F92_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, + }, + /* VEX_LEN_0F93_P_0 */ { { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, }, + /* VEX_LEN_0F93_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, + }, + + /* VEX_LEN_0F93_P_3 */ + { + { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, + }, + /* VEX_LEN_0F98_P_0 */ { { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, }, + /* VEX_LEN_0F98_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, + }, + + /* VEX_LEN_0F99_P_0 */ + { + { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, + }, + + /* VEX_LEN_0F99_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, + }, + /* VEX_LEN_0FAE_R_2_M_0 */ { { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, @@ -9605,62 +10084,62 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F38F2_P_0 */ { - { "andnS", { Gdq, VexGdq, Edq } }, + { "andnS", { Gdq, VexGdq, Edq }, 0 }, }, /* VEX_LEN_0F38F3_R_1_P_0 */ { - { "blsrS", { VexGdq, Edq } }, + { "blsrS", { VexGdq, Edq }, 0 }, }, /* VEX_LEN_0F38F3_R_2_P_0 */ { - { "blsmskS", { VexGdq, Edq } }, + { "blsmskS", { VexGdq, Edq }, 0 }, }, /* VEX_LEN_0F38F3_R_3_P_0 */ { - { "blsiS", { VexGdq, Edq } }, + { "blsiS", { VexGdq, Edq }, 0 }, }, /* VEX_LEN_0F38F5_P_0 */ { - { "bzhiS", { Gdq, Edq, VexGdq } }, + { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, }, /* VEX_LEN_0F38F5_P_1 */ { - { "pextS", { Gdq, VexGdq, Edq } }, + { "pextS", { Gdq, VexGdq, Edq }, 0 }, }, /* VEX_LEN_0F38F5_P_3 */ { - { "pdepS", { Gdq, VexGdq, Edq } }, + { "pdepS", { Gdq, VexGdq, Edq }, 0 }, }, /* VEX_LEN_0F38F6_P_3 */ { - { "mulxS", { Gdq, VexGdq, Edq } }, + { "mulxS", { Gdq, VexGdq, Edq }, 0 }, }, /* VEX_LEN_0F38F7_P_0 */ { - { "bextrS", { Gdq, Edq, VexGdq } }, + { "bextrS", { Gdq, Edq, VexGdq }, 0 }, }, /* VEX_LEN_0F38F7_P_1 */ { - { "sarxS", { Gdq, Edq, VexGdq } }, + { "sarxS", { Gdq, Edq, VexGdq }, 0 }, }, /* VEX_LEN_0F38F7_P_2 */ { - { "shlxS", { Gdq, Edq, VexGdq } }, + { "shlxS", { Gdq, Edq, VexGdq }, 0 }, }, /* VEX_LEN_0F38F7_P_3 */ { - { "shrxS", { Gdq, Edq, VexGdq } }, + { "shrxS", { Gdq, Edq, VexGdq }, 0 }, }, /* VEX_LEN_0F3A00_P_2 */ @@ -9705,12 +10184,12 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A16_P_2 */ { - { "vpextrK", { Edq, XM, Ib } }, + { "vpextrK", { Edq, XM, Ib }, 0 }, }, /* VEX_LEN_0F3A17_P_2 */ { - { "vextractps", { Edqd, XM, Ib } }, + { "vextractps", { Edqd, XM, Ib }, 0 }, }, /* VEX_LEN_0F3A18_P_2 */ @@ -9737,7 +10216,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A22_P_2 */ { - { "vpinsrK", { XM, Vex128, Edq, Ib } }, + { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, }, /* VEX_LEN_0F3A30_P_2 */ @@ -9745,11 +10224,21 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, }, + /* VEX_LEN_0F3A31_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, + }, + /* VEX_LEN_0F3A32_P_2 */ { { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, }, + /* VEX_LEN_0F3A33_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, + }, + /* VEX_LEN_0F3A38_P_2 */ { { Bad_Opcode }, @@ -9800,42 +10289,42 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A6A_P_2 */ { - { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, }, /* VEX_LEN_0F3A6B_P_2 */ { - { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, }, /* VEX_LEN_0F3A6E_P_2 */ { - { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, }, /* VEX_LEN_0F3A6F_P_2 */ { - { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, }, /* VEX_LEN_0F3A7A_P_2 */ { - { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, }, /* VEX_LEN_0F3A7B_P_2 */ { - { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, }, /* VEX_LEN_0F3A7E_P_2 */ { - { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } }, + { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, }, /* VEX_LEN_0F3A7F_P_2 */ { - { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } }, + { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, }, /* VEX_LEN_0F3ADF_P_2 */ @@ -9845,1200 +10334,1307 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3AF0_P_3 */ { - { "rorxS", { Gdq, Edq, Ib } }, + { "rorxS", { Gdq, Edq, Ib }, 0 }, }, /* VEX_LEN_0FXOP_08_CC */ { - { "vpcomb", { XM, Vex128, EXx, Ib } }, + { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0FXOP_08_CD */ { - { "vpcomw", { XM, Vex128, EXx, Ib } }, + { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0FXOP_08_CE */ { - { "vpcomd", { XM, Vex128, EXx, Ib } }, + { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0FXOP_08_CF */ { - { "vpcomq", { XM, Vex128, EXx, Ib } }, + { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0FXOP_08_EC */ { - { "vpcomub", { XM, Vex128, EXx, Ib } }, + { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0FXOP_08_ED */ { - { "vpcomuw", { XM, Vex128, EXx, Ib } }, + { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0FXOP_08_EE */ { - { "vpcomud", { XM, Vex128, EXx, Ib } }, + { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0FXOP_08_EF */ { - { "vpcomuq", { XM, Vex128, EXx, Ib } }, + { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0FXOP_09_80 */ { - { "vfrczps", { XM, EXxmm } }, - { "vfrczps", { XM, EXymmq } }, + { "vfrczps", { XM, EXxmm }, 0 }, + { "vfrczps", { XM, EXymmq }, 0 }, }, /* VEX_LEN_0FXOP_09_81 */ { - { "vfrczpd", { XM, EXxmm } }, - { "vfrczpd", { XM, EXymmq } }, + { "vfrczpd", { XM, EXxmm }, 0 }, + { "vfrczpd", { XM, EXymmq }, 0 }, }, }; static const struct dis386 vex_w_table[][2] = { { /* VEX_W_0F10_P_0 */ - { "vmovups", { XM, EXx } }, + { "vmovups", { XM, EXx }, 0 }, }, { /* VEX_W_0F10_P_1 */ - { "vmovss", { XMVexScalar, VexScalar, EXdScalar } }, + { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F10_P_2 */ - { "vmovupd", { XM, EXx } }, + { "vmovupd", { XM, EXx }, 0 }, }, { /* VEX_W_0F10_P_3 */ - { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } }, + { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F11_P_0 */ - { "vmovups", { EXxS, XM } }, + { "vmovups", { EXxS, XM }, 0 }, }, { /* VEX_W_0F11_P_1 */ - { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } }, + { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, }, { /* VEX_W_0F11_P_2 */ - { "vmovupd", { EXxS, XM } }, + { "vmovupd", { EXxS, XM }, 0 }, }, { /* VEX_W_0F11_P_3 */ - { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } }, + { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, }, { /* VEX_W_0F12_P_0_M_0 */ - { "vmovlps", { XM, Vex128, EXq } }, + { "vmovlps", { XM, Vex128, EXq }, 0 }, }, { /* VEX_W_0F12_P_0_M_1 */ - { "vmovhlps", { XM, Vex128, EXq } }, + { "vmovhlps", { XM, Vex128, EXq }, 0 }, }, { /* VEX_W_0F12_P_1 */ - { "vmovsldup", { XM, EXx } }, + { "vmovsldup", { XM, EXx }, 0 }, }, { /* VEX_W_0F12_P_2 */ - { "vmovlpd", { XM, Vex128, EXq } }, + { "vmovlpd", { XM, Vex128, EXq }, 0 }, }, { /* VEX_W_0F12_P_3 */ - { "vmovddup", { XM, EXymmq } }, + { "vmovddup", { XM, EXymmq }, 0 }, }, { /* VEX_W_0F13_M_0 */ - { "vmovlpX", { EXq, XM } }, + { "vmovlpX", { EXq, XM }, 0 }, }, { /* VEX_W_0F14 */ - { "vunpcklpX", { XM, Vex, EXx } }, + { "vunpcklpX", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F15 */ - { "vunpckhpX", { XM, Vex, EXx } }, + { "vunpckhpX", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F16_P_0_M_0 */ - { "vmovhps", { XM, Vex128, EXq } }, + { "vmovhps", { XM, Vex128, EXq }, 0 }, }, { /* VEX_W_0F16_P_0_M_1 */ - { "vmovlhps", { XM, Vex128, EXq } }, + { "vmovlhps", { XM, Vex128, EXq }, 0 }, }, { /* VEX_W_0F16_P_1 */ - { "vmovshdup", { XM, EXx } }, + { "vmovshdup", { XM, EXx }, 0 }, }, { /* VEX_W_0F16_P_2 */ - { "vmovhpd", { XM, Vex128, EXq } }, + { "vmovhpd", { XM, Vex128, EXq }, 0 }, }, { /* VEX_W_0F17_M_0 */ - { "vmovhpX", { EXq, XM } }, + { "vmovhpX", { EXq, XM }, 0 }, }, { /* VEX_W_0F28 */ - { "vmovapX", { XM, EXx } }, + { "vmovapX", { XM, EXx }, 0 }, }, { /* VEX_W_0F29 */ - { "vmovapX", { EXxS, XM } }, + { "vmovapX", { EXxS, XM }, 0 }, }, { /* VEX_W_0F2B_M_0 */ - { "vmovntpX", { Mx, XM } }, + { "vmovntpX", { Mx, XM }, 0 }, }, { /* VEX_W_0F2E_P_0 */ - { "vucomiss", { XMScalar, EXdScalar } }, + { "vucomiss", { XMScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F2E_P_2 */ - { "vucomisd", { XMScalar, EXqScalar } }, + { "vucomisd", { XMScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F2F_P_0 */ - { "vcomiss", { XMScalar, EXdScalar } }, + { "vcomiss", { XMScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F2F_P_2 */ - { "vcomisd", { XMScalar, EXqScalar } }, + { "vcomisd", { XMScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F41_P_0_LEN_1 */ - { "kandw", { MaskG, MaskVex, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, + }, + { + /* VEX_W_0F41_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } }, { /* VEX_W_0F42_P_0_LEN_1 */ - { "kandnw", { MaskG, MaskVex, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, + }, + { + /* VEX_W_0F42_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, }, { /* VEX_W_0F44_P_0_LEN_0 */ - { "knotw", { MaskG, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, + }, + { + /* VEX_W_0F44_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, }, { /* VEX_W_0F45_P_0_LEN_1 */ - { "korw", { MaskG, MaskVex, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, + }, + { + /* VEX_W_0F45_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, }, { /* VEX_W_0F46_P_0_LEN_1 */ - { "kxnorw", { MaskG, MaskVex, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, + }, + { + /* VEX_W_0F46_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, }, { /* VEX_W_0F47_P_0_LEN_1 */ - { "kxorw", { MaskG, MaskVex, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, + }, + { + /* VEX_W_0F47_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, + }, + { + /* VEX_W_0F4A_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, + }, + { + /* VEX_W_0F4A_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, + }, + { + /* VEX_W_0F4B_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, }, { /* VEX_W_0F4B_P_2_LEN_1 */ - { "kunpckbw", { MaskG, MaskVex, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, }, { /* VEX_W_0F50_M_0 */ - { "vmovmskpX", { Gdq, XS } }, + { "vmovmskpX", { Gdq, XS }, 0 }, }, { /* VEX_W_0F51_P_0 */ - { "vsqrtps", { XM, EXx } }, + { "vsqrtps", { XM, EXx }, 0 }, }, { /* VEX_W_0F51_P_1 */ - { "vsqrtss", { XMScalar, VexScalar, EXdScalar } }, + { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F51_P_2 */ - { "vsqrtpd", { XM, EXx } }, + { "vsqrtpd", { XM, EXx }, 0 }, }, { /* VEX_W_0F51_P_3 */ - { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } }, + { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F52_P_0 */ - { "vrsqrtps", { XM, EXx } }, + { "vrsqrtps", { XM, EXx }, 0 }, }, { /* VEX_W_0F52_P_1 */ - { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } }, + { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F53_P_0 */ - { "vrcpps", { XM, EXx } }, + { "vrcpps", { XM, EXx }, 0 }, }, { /* VEX_W_0F53_P_1 */ - { "vrcpss", { XMScalar, VexScalar, EXdScalar } }, + { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F58_P_0 */ - { "vaddps", { XM, Vex, EXx } }, + { "vaddps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F58_P_1 */ - { "vaddss", { XMScalar, VexScalar, EXdScalar } }, + { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F58_P_2 */ - { "vaddpd", { XM, Vex, EXx } }, + { "vaddpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F58_P_3 */ - { "vaddsd", { XMScalar, VexScalar, EXqScalar } }, + { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F59_P_0 */ - { "vmulps", { XM, Vex, EXx } }, + { "vmulps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F59_P_1 */ - { "vmulss", { XMScalar, VexScalar, EXdScalar } }, + { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F59_P_2 */ - { "vmulpd", { XM, Vex, EXx } }, + { "vmulpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F59_P_3 */ - { "vmulsd", { XMScalar, VexScalar, EXqScalar } }, + { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F5A_P_0 */ - { "vcvtps2pd", { XM, EXxmmq } }, + { "vcvtps2pd", { XM, EXxmmq }, 0 }, }, { /* VEX_W_0F5A_P_1 */ - { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } }, + { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F5A_P_3 */ - { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } }, + { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F5B_P_0 */ - { "vcvtdq2ps", { XM, EXx } }, + { "vcvtdq2ps", { XM, EXx }, 0 }, }, { /* VEX_W_0F5B_P_1 */ - { "vcvttps2dq", { XM, EXx } }, + { "vcvttps2dq", { XM, EXx }, 0 }, }, { /* VEX_W_0F5B_P_2 */ - { "vcvtps2dq", { XM, EXx } }, + { "vcvtps2dq", { XM, EXx }, 0 }, }, { /* VEX_W_0F5C_P_0 */ - { "vsubps", { XM, Vex, EXx } }, + { "vsubps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F5C_P_1 */ - { "vsubss", { XMScalar, VexScalar, EXdScalar } }, + { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F5C_P_2 */ - { "vsubpd", { XM, Vex, EXx } }, + { "vsubpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F5C_P_3 */ - { "vsubsd", { XMScalar, VexScalar, EXqScalar } }, + { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F5D_P_0 */ - { "vminps", { XM, Vex, EXx } }, + { "vminps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F5D_P_1 */ - { "vminss", { XMScalar, VexScalar, EXdScalar } }, + { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F5D_P_2 */ - { "vminpd", { XM, Vex, EXx } }, + { "vminpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F5D_P_3 */ - { "vminsd", { XMScalar, VexScalar, EXqScalar } }, + { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F5E_P_0 */ - { "vdivps", { XM, Vex, EXx } }, + { "vdivps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F5E_P_1 */ - { "vdivss", { XMScalar, VexScalar, EXdScalar } }, + { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F5E_P_2 */ - { "vdivpd", { XM, Vex, EXx } }, + { "vdivpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F5E_P_3 */ - { "vdivsd", { XMScalar, VexScalar, EXqScalar } }, + { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F5F_P_0 */ - { "vmaxps", { XM, Vex, EXx } }, + { "vmaxps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F5F_P_1 */ - { "vmaxss", { XMScalar, VexScalar, EXdScalar } }, + { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, { /* VEX_W_0F5F_P_2 */ - { "vmaxpd", { XM, Vex, EXx } }, + { "vmaxpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F5F_P_3 */ - { "vmaxsd", { XMScalar, VexScalar, EXqScalar } }, + { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F60_P_2 */ - { "vpunpcklbw", { XM, Vex, EXx } }, + { "vpunpcklbw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F61_P_2 */ - { "vpunpcklwd", { XM, Vex, EXx } }, + { "vpunpcklwd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F62_P_2 */ - { "vpunpckldq", { XM, Vex, EXx } }, + { "vpunpckldq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F63_P_2 */ - { "vpacksswb", { XM, Vex, EXx } }, + { "vpacksswb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F64_P_2 */ - { "vpcmpgtb", { XM, Vex, EXx } }, + { "vpcmpgtb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F65_P_2 */ - { "vpcmpgtw", { XM, Vex, EXx } }, + { "vpcmpgtw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F66_P_2 */ - { "vpcmpgtd", { XM, Vex, EXx } }, + { "vpcmpgtd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F67_P_2 */ - { "vpackuswb", { XM, Vex, EXx } }, + { "vpackuswb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F68_P_2 */ - { "vpunpckhbw", { XM, Vex, EXx } }, + { "vpunpckhbw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F69_P_2 */ - { "vpunpckhwd", { XM, Vex, EXx } }, + { "vpunpckhwd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F6A_P_2 */ - { "vpunpckhdq", { XM, Vex, EXx } }, + { "vpunpckhdq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F6B_P_2 */ - { "vpackssdw", { XM, Vex, EXx } }, + { "vpackssdw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F6C_P_2 */ - { "vpunpcklqdq", { XM, Vex, EXx } }, + { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F6D_P_2 */ - { "vpunpckhqdq", { XM, Vex, EXx } }, + { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F6F_P_1 */ - { "vmovdqu", { XM, EXx } }, + { "vmovdqu", { XM, EXx }, 0 }, }, { /* VEX_W_0F6F_P_2 */ - { "vmovdqa", { XM, EXx } }, + { "vmovdqa", { XM, EXx }, 0 }, }, { /* VEX_W_0F70_P_1 */ - { "vpshufhw", { XM, EXx, Ib } }, + { "vpshufhw", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F70_P_2 */ - { "vpshufd", { XM, EXx, Ib } }, + { "vpshufd", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F70_P_3 */ - { "vpshuflw", { XM, EXx, Ib } }, + { "vpshuflw", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F71_R_2_P_2 */ - { "vpsrlw", { Vex, XS, Ib } }, + { "vpsrlw", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F71_R_4_P_2 */ - { "vpsraw", { Vex, XS, Ib } }, + { "vpsraw", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F71_R_6_P_2 */ - { "vpsllw", { Vex, XS, Ib } }, + { "vpsllw", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F72_R_2_P_2 */ - { "vpsrld", { Vex, XS, Ib } }, + { "vpsrld", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F72_R_4_P_2 */ - { "vpsrad", { Vex, XS, Ib } }, + { "vpsrad", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F72_R_6_P_2 */ - { "vpslld", { Vex, XS, Ib } }, + { "vpslld", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F73_R_2_P_2 */ - { "vpsrlq", { Vex, XS, Ib } }, + { "vpsrlq", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F73_R_3_P_2 */ - { "vpsrldq", { Vex, XS, Ib } }, + { "vpsrldq", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F73_R_6_P_2 */ - { "vpsllq", { Vex, XS, Ib } }, + { "vpsllq", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F73_R_7_P_2 */ - { "vpslldq", { Vex, XS, Ib } }, + { "vpslldq", { Vex, XS, Ib }, 0 }, }, { /* VEX_W_0F74_P_2 */ - { "vpcmpeqb", { XM, Vex, EXx } }, + { "vpcmpeqb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F75_P_2 */ - { "vpcmpeqw", { XM, Vex, EXx } }, + { "vpcmpeqw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F76_P_2 */ - { "vpcmpeqd", { XM, Vex, EXx } }, + { "vpcmpeqd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F77_P_0 */ - { "", { VZERO } }, + { "", { VZERO }, 0 }, }, { /* VEX_W_0F7C_P_2 */ - { "vhaddpd", { XM, Vex, EXx } }, + { "vhaddpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F7C_P_3 */ - { "vhaddps", { XM, Vex, EXx } }, + { "vhaddps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F7D_P_2 */ - { "vhsubpd", { XM, Vex, EXx } }, + { "vhsubpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F7D_P_3 */ - { "vhsubps", { XM, Vex, EXx } }, + { "vhsubps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F7E_P_1 */ - { "vmovq", { XMScalar, EXqScalar } }, + { "vmovq", { XMScalar, EXqScalar }, 0 }, }, { /* VEX_W_0F7F_P_1 */ - { "vmovdqu", { EXxS, XM } }, + { "vmovdqu", { EXxS, XM }, 0 }, }, { /* VEX_W_0F7F_P_2 */ - { "vmovdqa", { EXxS, XM } }, + { "vmovdqa", { EXxS, XM }, 0 }, }, { /* VEX_W_0F90_P_0_LEN_0 */ - { "kmovw", { MaskG, MaskE } }, + { "kmovw", { MaskG, MaskE }, 0 }, + { "kmovq", { MaskG, MaskE }, 0 }, + }, + { + /* VEX_W_0F90_P_2_LEN_0 */ + { "kmovb", { MaskG, MaskBDE }, 0 }, + { "kmovd", { MaskG, MaskBDE }, 0 }, }, { /* VEX_W_0F91_P_0_LEN_0 */ - { "kmovw", { Ew, MaskG } }, + { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, + }, + { + /* VEX_W_0F91_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, }, { /* VEX_W_0F92_P_0_LEN_0 */ - { "kmovw", { MaskG, Rdq } }, + { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, + }, + { + /* VEX_W_0F92_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, + }, + { + /* VEX_W_0F92_P_3_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, }, { /* VEX_W_0F93_P_0_LEN_0 */ - { "kmovw", { Gdq, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, + }, + { + /* VEX_W_0F93_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, + }, + { + /* VEX_W_0F93_P_3_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, }, { /* VEX_W_0F98_P_0_LEN_0 */ - { "kortestw", { MaskG, MaskR } }, + { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, + }, + { + /* VEX_W_0F98_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, + }, + { + /* VEX_W_0F99_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, + }, + { + /* VEX_W_0F99_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, }, { /* VEX_W_0FAE_R_2_M_0 */ - { "vldmxcsr", { Md } }, + { "vldmxcsr", { Md }, 0 }, }, { /* VEX_W_0FAE_R_3_M_0 */ - { "vstmxcsr", { Md } }, + { "vstmxcsr", { Md }, 0 }, }, { /* VEX_W_0FC2_P_0 */ - { "vcmpps", { XM, Vex, EXx, VCMP } }, + { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, }, { /* VEX_W_0FC2_P_1 */ - { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } }, + { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, }, { /* VEX_W_0FC2_P_2 */ - { "vcmppd", { XM, Vex, EXx, VCMP } }, + { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, }, { /* VEX_W_0FC2_P_3 */ - { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } }, + { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, }, { /* VEX_W_0FC4_P_2 */ - { "vpinsrw", { XM, Vex128, Edqw, Ib } }, + { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, }, { /* VEX_W_0FC5_P_2 */ - { "vpextrw", { Gdq, XS, Ib } }, + { "vpextrw", { Gdq, XS, Ib }, 0 }, }, { /* VEX_W_0FD0_P_2 */ - { "vaddsubpd", { XM, Vex, EXx } }, + { "vaddsubpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FD0_P_3 */ - { "vaddsubps", { XM, Vex, EXx } }, + { "vaddsubps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FD1_P_2 */ - { "vpsrlw", { XM, Vex, EXxmm } }, + { "vpsrlw", { XM, Vex, EXxmm }, 0 }, }, { /* VEX_W_0FD2_P_2 */ - { "vpsrld", { XM, Vex, EXxmm } }, + { "vpsrld", { XM, Vex, EXxmm }, 0 }, }, { /* VEX_W_0FD3_P_2 */ - { "vpsrlq", { XM, Vex, EXxmm } }, + { "vpsrlq", { XM, Vex, EXxmm }, 0 }, }, { /* VEX_W_0FD4_P_2 */ - { "vpaddq", { XM, Vex, EXx } }, + { "vpaddq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FD5_P_2 */ - { "vpmullw", { XM, Vex, EXx } }, + { "vpmullw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FD6_P_2 */ - { "vmovq", { EXqScalarS, XMScalar } }, + { "vmovq", { EXqScalarS, XMScalar }, 0 }, }, { /* VEX_W_0FD7_P_2_M_1 */ - { "vpmovmskb", { Gdq, XS } }, + { "vpmovmskb", { Gdq, XS }, 0 }, }, { /* VEX_W_0FD8_P_2 */ - { "vpsubusb", { XM, Vex, EXx } }, + { "vpsubusb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FD9_P_2 */ - { "vpsubusw", { XM, Vex, EXx } }, + { "vpsubusw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FDA_P_2 */ - { "vpminub", { XM, Vex, EXx } }, + { "vpminub", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FDB_P_2 */ - { "vpand", { XM, Vex, EXx } }, + { "vpand", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FDC_P_2 */ - { "vpaddusb", { XM, Vex, EXx } }, + { "vpaddusb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FDD_P_2 */ - { "vpaddusw", { XM, Vex, EXx } }, + { "vpaddusw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FDE_P_2 */ - { "vpmaxub", { XM, Vex, EXx } }, + { "vpmaxub", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FDF_P_2 */ - { "vpandn", { XM, Vex, EXx } }, + { "vpandn", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FE0_P_2 */ - { "vpavgb", { XM, Vex, EXx } }, + { "vpavgb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FE1_P_2 */ - { "vpsraw", { XM, Vex, EXxmm } }, + { "vpsraw", { XM, Vex, EXxmm }, 0 }, }, { /* VEX_W_0FE2_P_2 */ - { "vpsrad", { XM, Vex, EXxmm } }, + { "vpsrad", { XM, Vex, EXxmm }, 0 }, }, { /* VEX_W_0FE3_P_2 */ - { "vpavgw", { XM, Vex, EXx } }, + { "vpavgw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FE4_P_2 */ - { "vpmulhuw", { XM, Vex, EXx } }, + { "vpmulhuw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FE5_P_2 */ - { "vpmulhw", { XM, Vex, EXx } }, + { "vpmulhw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FE6_P_1 */ - { "vcvtdq2pd", { XM, EXxmmq } }, + { "vcvtdq2pd", { XM, EXxmmq }, 0 }, }, { /* VEX_W_0FE6_P_2 */ - { "vcvttpd2dq%XY", { XMM, EXx } }, + { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, }, { /* VEX_W_0FE6_P_3 */ - { "vcvtpd2dq%XY", { XMM, EXx } }, + { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, }, { /* VEX_W_0FE7_P_2_M_0 */ - { "vmovntdq", { Mx, XM } }, + { "vmovntdq", { Mx, XM }, 0 }, }, { /* VEX_W_0FE8_P_2 */ - { "vpsubsb", { XM, Vex, EXx } }, + { "vpsubsb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FE9_P_2 */ - { "vpsubsw", { XM, Vex, EXx } }, + { "vpsubsw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FEA_P_2 */ - { "vpminsw", { XM, Vex, EXx } }, + { "vpminsw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FEB_P_2 */ - { "vpor", { XM, Vex, EXx } }, + { "vpor", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FEC_P_2 */ - { "vpaddsb", { XM, Vex, EXx } }, + { "vpaddsb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FED_P_2 */ - { "vpaddsw", { XM, Vex, EXx } }, + { "vpaddsw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FEE_P_2 */ - { "vpmaxsw", { XM, Vex, EXx } }, + { "vpmaxsw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FEF_P_2 */ - { "vpxor", { XM, Vex, EXx } }, + { "vpxor", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FF0_P_3_M_0 */ - { "vlddqu", { XM, M } }, + { "vlddqu", { XM, M }, 0 }, }, { /* VEX_W_0FF1_P_2 */ - { "vpsllw", { XM, Vex, EXxmm } }, + { "vpsllw", { XM, Vex, EXxmm }, 0 }, }, { /* VEX_W_0FF2_P_2 */ - { "vpslld", { XM, Vex, EXxmm } }, + { "vpslld", { XM, Vex, EXxmm }, 0 }, }, { /* VEX_W_0FF3_P_2 */ - { "vpsllq", { XM, Vex, EXxmm } }, + { "vpsllq", { XM, Vex, EXxmm }, 0 }, }, { /* VEX_W_0FF4_P_2 */ - { "vpmuludq", { XM, Vex, EXx } }, + { "vpmuludq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FF5_P_2 */ - { "vpmaddwd", { XM, Vex, EXx } }, + { "vpmaddwd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FF6_P_2 */ - { "vpsadbw", { XM, Vex, EXx } }, + { "vpsadbw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FF7_P_2 */ - { "vmaskmovdqu", { XM, XS } }, + { "vmaskmovdqu", { XM, XS }, 0 }, }, { /* VEX_W_0FF8_P_2 */ - { "vpsubb", { XM, Vex, EXx } }, + { "vpsubb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FF9_P_2 */ - { "vpsubw", { XM, Vex, EXx } }, + { "vpsubw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FFA_P_2 */ - { "vpsubd", { XM, Vex, EXx } }, + { "vpsubd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FFB_P_2 */ - { "vpsubq", { XM, Vex, EXx } }, + { "vpsubq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FFC_P_2 */ - { "vpaddb", { XM, Vex, EXx } }, + { "vpaddb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FFD_P_2 */ - { "vpaddw", { XM, Vex, EXx } }, + { "vpaddw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0FFE_P_2 */ - { "vpaddd", { XM, Vex, EXx } }, + { "vpaddd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3800_P_2 */ - { "vpshufb", { XM, Vex, EXx } }, + { "vpshufb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3801_P_2 */ - { "vphaddw", { XM, Vex, EXx } }, + { "vphaddw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3802_P_2 */ - { "vphaddd", { XM, Vex, EXx } }, + { "vphaddd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3803_P_2 */ - { "vphaddsw", { XM, Vex, EXx } }, + { "vphaddsw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3804_P_2 */ - { "vpmaddubsw", { XM, Vex, EXx } }, + { "vpmaddubsw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3805_P_2 */ - { "vphsubw", { XM, Vex, EXx } }, + { "vphsubw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3806_P_2 */ - { "vphsubd", { XM, Vex, EXx } }, + { "vphsubd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3807_P_2 */ - { "vphsubsw", { XM, Vex, EXx } }, + { "vphsubsw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3808_P_2 */ - { "vpsignb", { XM, Vex, EXx } }, + { "vpsignb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3809_P_2 */ - { "vpsignw", { XM, Vex, EXx } }, + { "vpsignw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F380A_P_2 */ - { "vpsignd", { XM, Vex, EXx } }, + { "vpsignd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F380B_P_2 */ - { "vpmulhrsw", { XM, Vex, EXx } }, + { "vpmulhrsw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F380C_P_2 */ - { "vpermilps", { XM, Vex, EXx } }, + { "vpermilps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F380D_P_2 */ - { "vpermilpd", { XM, Vex, EXx } }, + { "vpermilpd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F380E_P_2 */ - { "vtestps", { XM, EXx } }, + { "vtestps", { XM, EXx }, 0 }, }, { /* VEX_W_0F380F_P_2 */ - { "vtestpd", { XM, EXx } }, + { "vtestpd", { XM, EXx }, 0 }, }, { /* VEX_W_0F3816_P_2 */ - { "vpermps", { XM, Vex, EXx } }, + { "vpermps", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3817_P_2 */ - { "vptest", { XM, EXx } }, + { "vptest", { XM, EXx }, 0 }, }, { /* VEX_W_0F3818_P_2 */ - { "vbroadcastss", { XM, EXxmm_md } }, + { "vbroadcastss", { XM, EXxmm_md }, 0 }, }, { /* VEX_W_0F3819_P_2 */ - { "vbroadcastsd", { XM, EXxmm_mq } }, + { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, }, { /* VEX_W_0F381A_P_2_M_0 */ - { "vbroadcastf128", { XM, Mxmm } }, + { "vbroadcastf128", { XM, Mxmm }, 0 }, }, { /* VEX_W_0F381C_P_2 */ - { "vpabsb", { XM, EXx } }, + { "vpabsb", { XM, EXx }, 0 }, }, { /* VEX_W_0F381D_P_2 */ - { "vpabsw", { XM, EXx } }, + { "vpabsw", { XM, EXx }, 0 }, }, { /* VEX_W_0F381E_P_2 */ - { "vpabsd", { XM, EXx } }, + { "vpabsd", { XM, EXx }, 0 }, }, { /* VEX_W_0F3820_P_2 */ - { "vpmovsxbw", { XM, EXxmmq } }, + { "vpmovsxbw", { XM, EXxmmq }, 0 }, }, { /* VEX_W_0F3821_P_2 */ - { "vpmovsxbd", { XM, EXxmmqd } }, + { "vpmovsxbd", { XM, EXxmmqd }, 0 }, }, { /* VEX_W_0F3822_P_2 */ - { "vpmovsxbq", { XM, EXxmmdw } }, + { "vpmovsxbq", { XM, EXxmmdw }, 0 }, }, { /* VEX_W_0F3823_P_2 */ - { "vpmovsxwd", { XM, EXxmmq } }, + { "vpmovsxwd", { XM, EXxmmq }, 0 }, }, { /* VEX_W_0F3824_P_2 */ - { "vpmovsxwq", { XM, EXxmmqd } }, + { "vpmovsxwq", { XM, EXxmmqd }, 0 }, }, { /* VEX_W_0F3825_P_2 */ - { "vpmovsxdq", { XM, EXxmmq } }, + { "vpmovsxdq", { XM, EXxmmq }, 0 }, }, { /* VEX_W_0F3828_P_2 */ - { "vpmuldq", { XM, Vex, EXx } }, + { "vpmuldq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3829_P_2 */ - { "vpcmpeqq", { XM, Vex, EXx } }, + { "vpcmpeqq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F382A_P_2_M_0 */ - { "vmovntdqa", { XM, Mx } }, + { "vmovntdqa", { XM, Mx }, 0 }, }, { /* VEX_W_0F382B_P_2 */ - { "vpackusdw", { XM, Vex, EXx } }, + { "vpackusdw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F382C_P_2_M_0 */ - { "vmaskmovps", { XM, Vex, Mx } }, + { "vmaskmovps", { XM, Vex, Mx }, 0 }, }, { /* VEX_W_0F382D_P_2_M_0 */ - { "vmaskmovpd", { XM, Vex, Mx } }, + { "vmaskmovpd", { XM, Vex, Mx }, 0 }, }, { /* VEX_W_0F382E_P_2_M_0 */ - { "vmaskmovps", { Mx, Vex, XM } }, + { "vmaskmovps", { Mx, Vex, XM }, 0 }, }, { /* VEX_W_0F382F_P_2_M_0 */ - { "vmaskmovpd", { Mx, Vex, XM } }, + { "vmaskmovpd", { Mx, Vex, XM }, 0 }, }, { /* VEX_W_0F3830_P_2 */ - { "vpmovzxbw", { XM, EXxmmq } }, + { "vpmovzxbw", { XM, EXxmmq }, 0 }, }, { /* VEX_W_0F3831_P_2 */ - { "vpmovzxbd", { XM, EXxmmqd } }, + { "vpmovzxbd", { XM, EXxmmqd }, 0 }, }, { /* VEX_W_0F3832_P_2 */ - { "vpmovzxbq", { XM, EXxmmdw } }, + { "vpmovzxbq", { XM, EXxmmdw }, 0 }, }, { /* VEX_W_0F3833_P_2 */ - { "vpmovzxwd", { XM, EXxmmq } }, + { "vpmovzxwd", { XM, EXxmmq }, 0 }, }, { /* VEX_W_0F3834_P_2 */ - { "vpmovzxwq", { XM, EXxmmqd } }, + { "vpmovzxwq", { XM, EXxmmqd }, 0 }, }, { /* VEX_W_0F3835_P_2 */ - { "vpmovzxdq", { XM, EXxmmq } }, + { "vpmovzxdq", { XM, EXxmmq }, 0 }, }, { /* VEX_W_0F3836_P_2 */ - { "vpermd", { XM, Vex, EXx } }, + { "vpermd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3837_P_2 */ - { "vpcmpgtq", { XM, Vex, EXx } }, + { "vpcmpgtq", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3838_P_2 */ - { "vpminsb", { XM, Vex, EXx } }, + { "vpminsb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3839_P_2 */ - { "vpminsd", { XM, Vex, EXx } }, + { "vpminsd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F383A_P_2 */ - { "vpminuw", { XM, Vex, EXx } }, + { "vpminuw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F383B_P_2 */ - { "vpminud", { XM, Vex, EXx } }, + { "vpminud", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F383C_P_2 */ - { "vpmaxsb", { XM, Vex, EXx } }, + { "vpmaxsb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F383D_P_2 */ - { "vpmaxsd", { XM, Vex, EXx } }, + { "vpmaxsd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F383E_P_2 */ - { "vpmaxuw", { XM, Vex, EXx } }, + { "vpmaxuw", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F383F_P_2 */ - { "vpmaxud", { XM, Vex, EXx } }, + { "vpmaxud", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3840_P_2 */ - { "vpmulld", { XM, Vex, EXx } }, + { "vpmulld", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3841_P_2 */ - { "vphminposuw", { XM, EXx } }, + { "vphminposuw", { XM, EXx }, 0 }, }, { /* VEX_W_0F3846_P_2 */ - { "vpsravd", { XM, Vex, EXx } }, + { "vpsravd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3858_P_2 */ - { "vpbroadcastd", { XM, EXxmm_md } }, + { "vpbroadcastd", { XM, EXxmm_md }, 0 }, }, { /* VEX_W_0F3859_P_2 */ - { "vpbroadcastq", { XM, EXxmm_mq } }, + { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, }, { /* VEX_W_0F385A_P_2_M_0 */ - { "vbroadcasti128", { XM, Mxmm } }, + { "vbroadcasti128", { XM, Mxmm }, 0 }, }, { /* VEX_W_0F3878_P_2 */ - { "vpbroadcastb", { XM, EXxmm_mb } }, + { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, }, { /* VEX_W_0F3879_P_2 */ - { "vpbroadcastw", { XM, EXxmm_mw } }, + { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, }, { /* VEX_W_0F38DB_P_2 */ - { "vaesimc", { XM, EXx } }, + { "vaesimc", { XM, EXx }, 0 }, }, { /* VEX_W_0F38DC_P_2 */ - { "vaesenc", { XM, Vex128, EXx } }, + { "vaesenc", { XM, Vex128, EXx }, 0 }, }, { /* VEX_W_0F38DD_P_2 */ - { "vaesenclast", { XM, Vex128, EXx } }, + { "vaesenclast", { XM, Vex128, EXx }, 0 }, }, { /* VEX_W_0F38DE_P_2 */ - { "vaesdec", { XM, Vex128, EXx } }, + { "vaesdec", { XM, Vex128, EXx }, 0 }, }, { /* VEX_W_0F38DF_P_2 */ - { "vaesdeclast", { XM, Vex128, EXx } }, + { "vaesdeclast", { XM, Vex128, EXx }, 0 }, }, { /* VEX_W_0F3A00_P_2 */ { Bad_Opcode }, - { "vpermq", { XM, EXx, Ib } }, + { "vpermq", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A01_P_2 */ { Bad_Opcode }, - { "vpermpd", { XM, EXx, Ib } }, + { "vpermpd", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A02_P_2 */ - { "vpblendd", { XM, Vex, EXx, Ib } }, + { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A04_P_2 */ - { "vpermilps", { XM, EXx, Ib } }, + { "vpermilps", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A05_P_2 */ - { "vpermilpd", { XM, EXx, Ib } }, + { "vpermilpd", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A06_P_2 */ - { "vperm2f128", { XM, Vex256, EXx, Ib } }, + { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A08_P_2 */ - { "vroundps", { XM, EXx, Ib } }, + { "vroundps", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A09_P_2 */ - { "vroundpd", { XM, EXx, Ib } }, + { "vroundpd", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A0A_P_2 */ - { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } }, + { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, }, { /* VEX_W_0F3A0B_P_2 */ - { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } }, + { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, }, { /* VEX_W_0F3A0C_P_2 */ - { "vblendps", { XM, Vex, EXx, Ib } }, + { "vblendps", { XM, Vex, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A0D_P_2 */ - { "vblendpd", { XM, Vex, EXx, Ib } }, + { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A0E_P_2 */ - { "vpblendw", { XM, Vex, EXx, Ib } }, + { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A0F_P_2 */ - { "vpalignr", { XM, Vex, EXx, Ib } }, + { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A14_P_2 */ - { "vpextrb", { Edqb, XM, Ib } }, + { "vpextrb", { Edqb, XM, Ib }, 0 }, }, { /* VEX_W_0F3A15_P_2 */ - { "vpextrw", { Edqw, XM, Ib } }, + { "vpextrw", { Edqw, XM, Ib }, 0 }, }, { /* VEX_W_0F3A18_P_2 */ - { "vinsertf128", { XM, Vex256, EXxmm, Ib } }, + { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, }, { /* VEX_W_0F3A19_P_2 */ - { "vextractf128", { EXxmm, XM, Ib } }, + { "vextractf128", { EXxmm, XM, Ib }, 0 }, }, { /* VEX_W_0F3A20_P_2 */ - { "vpinsrb", { XM, Vex128, Edqb, Ib } }, + { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, }, { /* VEX_W_0F3A21_P_2 */ - { "vinsertps", { XM, Vex128, EXd, Ib } }, + { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, }, { - /* VEX_W_0F3A30_P_2 */ - { Bad_Opcode }, - { "kshiftrw", { MaskG, MaskR, Ib } }, + /* VEX_W_0F3A30_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, }, { - /* VEX_W_0F3A32_P_2 */ - { Bad_Opcode }, - { "kshiftlw", { MaskG, MaskR, Ib } }, + /* VEX_W_0F3A31_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, + }, + { + /* VEX_W_0F3A32_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, + }, + { + /* VEX_W_0F3A33_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, }, { /* VEX_W_0F3A38_P_2 */ - { "vinserti128", { XM, Vex256, EXxmm, Ib } }, + { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, }, { /* VEX_W_0F3A39_P_2 */ - { "vextracti128", { EXxmm, XM, Ib } }, + { "vextracti128", { EXxmm, XM, Ib }, 0 }, }, { /* VEX_W_0F3A40_P_2 */ - { "vdpps", { XM, Vex, EXx, Ib } }, + { "vdpps", { XM, Vex, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A41_P_2 */ - { "vdppd", { XM, Vex128, EXx, Ib } }, + { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A42_P_2 */ - { "vmpsadbw", { XM, Vex, EXx, Ib } }, + { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A44_P_2 */ - { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } }, + { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, }, { /* VEX_W_0F3A46_P_2 */ - { "vperm2i128", { XM, Vex256, EXx, Ib } }, + { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A48_P_2 */ - { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, - { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, + { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, + { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, }, { /* VEX_W_0F3A49_P_2 */ - { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, - { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } }, + { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, + { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, }, { /* VEX_W_0F3A4A_P_2 */ - { "vblendvps", { XM, Vex, EXx, XMVexI4 } }, + { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, }, { /* VEX_W_0F3A4B_P_2 */ - { "vblendvpd", { XM, Vex, EXx, XMVexI4 } }, + { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, }, { /* VEX_W_0F3A4C_P_2 */ - { "vpblendvb", { XM, Vex, EXx, XMVexI4 } }, + { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, }, { /* VEX_W_0F3A60_P_2 */ - { "vpcmpestrm", { XM, EXx, Ib } }, + { "vpcmpestrm", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A61_P_2 */ - { "vpcmpestri", { XM, EXx, Ib } }, + { "vpcmpestri", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A62_P_2 */ - { "vpcmpistrm", { XM, EXx, Ib } }, + { "vpcmpistrm", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3A63_P_2 */ - { "vpcmpistri", { XM, EXx, Ib } }, + { "vpcmpistri", { XM, EXx, Ib }, 0 }, }, { /* VEX_W_0F3ADF_P_2 */ - { "vaeskeygenassist", { XM, EXx, Ib } }, + { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, }, #define NEED_VEX_W_TABLE #include "i386-dis-evex.h" @@ -11048,7 +11644,7 @@ static const struct dis386 vex_w_table[][2] = { static const struct dis386 mod_table[][2] = { { /* MOD_8D */ - { "leaS", { Gv, M } }, + { "leaS", { Gv, M }, 0 }, }, { /* MOD_C6_REG_7 */ @@ -11062,11 +11658,11 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_FF_REG_3 */ - { "Jcall{T|}", { indirEp } }, + { "Jcall^", { indirEp }, 0 }, }, { /* MOD_FF_REG_5 */ - { "Jjmp{T|}", { indirEp } }, + { "Jjmp^", { indirEp }, 0 }, }, { /* MOD_0F01_REG_0 */ @@ -11090,159 +11686,139 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F01_REG_7 */ - { "invlpg", { Mb } }, + { "invlpg", { Mb }, 0 }, { RM_TABLE (RM_0F01_REG_7) }, }, { /* MOD_0F12_PREFIX_0 */ - { "movlps", { XM, EXq } }, - { "movhlps", { XM, EXq } }, + { "movlps", { XM, EXq }, PREFIX_OPCODE }, + { "movhlps", { XM, EXq }, PREFIX_OPCODE }, }, { /* MOD_0F13 */ - { "movlpX", { EXq, XM } }, + { "movlpX", { EXq, XM }, PREFIX_OPCODE }, }, { /* MOD_0F16_PREFIX_0 */ - { "movhps", { XM, EXq } }, - { "movlhps", { XM, EXq } }, + { "movhps", { XM, EXq }, 0 }, + { "movlhps", { XM, EXq }, 0 }, }, { /* MOD_0F17 */ - { "movhpX", { EXq, XM } }, + { "movhpX", { EXq, XM }, PREFIX_OPCODE }, }, { /* MOD_0F18_REG_0 */ - { "prefetchnta", { Mb } }, + { "prefetchnta", { Mb }, 0 }, }, { /* MOD_0F18_REG_1 */ - { "prefetcht0", { Mb } }, + { "prefetcht0", { Mb }, 0 }, }, { /* MOD_0F18_REG_2 */ - { "prefetcht1", { Mb } }, + { "prefetcht1", { Mb }, 0 }, }, { /* MOD_0F18_REG_3 */ - { "prefetcht2", { Mb } }, + { "prefetcht2", { Mb }, 0 }, }, { /* MOD_0F18_REG_4 */ - { "nop/reserved", { Mb } }, + { "nop/reserved", { Mb }, 0 }, }, { /* MOD_0F18_REG_5 */ - { "nop/reserved", { Mb } }, + { "nop/reserved", { Mb }, 0 }, }, { /* MOD_0F18_REG_6 */ - { "nop/reserved", { Mb } }, + { "nop/reserved", { Mb }, 0 }, }, { /* MOD_0F18_REG_7 */ - { "nop/reserved", { Mb } }, + { "nop/reserved", { Mb }, 0 }, }, { /* MOD_0F1A_PREFIX_0 */ - { "bndldx", { Gbnd, Ev_bnd } }, - { "nopQ", { Ev } }, + { "bndldx", { Gbnd, Ev_bnd }, 0 }, + { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1B_PREFIX_0 */ - { "bndstx", { Ev_bnd, Gbnd } }, - { "nopQ", { Ev } }, + { "bndstx", { Ev_bnd, Gbnd }, 0 }, + { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1B_PREFIX_1 */ - { "bndmk", { Gbnd, Ev_bnd } }, - { "nopQ", { Ev } }, - }, - { - /* MOD_0F20 */ - { Bad_Opcode }, - { "movZ", { Rm, Cm } }, - }, - { - /* MOD_0F21 */ - { Bad_Opcode }, - { "movZ", { Rm, Dm } }, - }, - { - /* MOD_0F22 */ - { Bad_Opcode }, - { "movZ", { Cm, Rm } }, - }, - { - /* MOD_0F23 */ - { Bad_Opcode }, - { "movZ", { Dm, Rm } }, + { "bndmk", { Gbnd, Ev_bnd }, 0 }, + { "nopQ", { Ev }, 0 }, }, { /* MOD_0F24 */ { Bad_Opcode }, - { "movL", { Rd, Td } }, + { "movL", { Rd, Td }, 0 }, }, { /* MOD_0F26 */ { Bad_Opcode }, - { "movL", { Td, Rd } }, + { "movL", { Td, Rd }, 0 }, }, { /* MOD_0F2B_PREFIX_0 */ - {"movntps", { Mx, XM } }, + {"movntps", { Mx, XM }, PREFIX_OPCODE }, }, { /* MOD_0F2B_PREFIX_1 */ - {"movntss", { Md, XM } }, + {"movntss", { Md, XM }, PREFIX_OPCODE }, }, { /* MOD_0F2B_PREFIX_2 */ - {"movntpd", { Mx, XM } }, + {"movntpd", { Mx, XM }, PREFIX_OPCODE }, }, { /* MOD_0F2B_PREFIX_3 */ - {"movntsd", { Mq, XM } }, + {"movntsd", { Mq, XM }, PREFIX_OPCODE }, }, { /* MOD_0F51 */ { Bad_Opcode }, - { "movmskpX", { Gdq, XS } }, + { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, }, { /* MOD_0F71_REG_2 */ { Bad_Opcode }, - { "psrlw", { MS, Ib } }, + { "psrlw", { MS, Ib }, 0 }, }, { /* MOD_0F71_REG_4 */ { Bad_Opcode }, - { "psraw", { MS, Ib } }, + { "psraw", { MS, Ib }, 0 }, }, { /* MOD_0F71_REG_6 */ { Bad_Opcode }, - { "psllw", { MS, Ib } }, + { "psllw", { MS, Ib }, 0 }, }, { /* MOD_0F72_REG_2 */ { Bad_Opcode }, - { "psrld", { MS, Ib } }, + { "psrld", { MS, Ib }, 0 }, }, { /* MOD_0F72_REG_4 */ { Bad_Opcode }, - { "psrad", { MS, Ib } }, + { "psrad", { MS, Ib }, 0 }, }, { /* MOD_0F72_REG_6 */ { Bad_Opcode }, - { "pslld", { MS, Ib } }, + { "pslld", { MS, Ib }, 0 }, }, { /* MOD_0F73_REG_2 */ { Bad_Opcode }, - { "psrlq", { MS, Ib } }, + { "psrlq", { MS, Ib }, 0 }, }, { /* MOD_0F73_REG_3 */ @@ -11252,7 +11828,7 @@ static const struct dis386 mod_table[][2] = { { /* MOD_0F73_REG_6 */ { Bad_Opcode }, - { "psllq", { MS, Ib } }, + { "psllq", { MS, Ib }, 0 }, }, { /* MOD_0F73_REG_7 */ @@ -11261,36 +11837,36 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FAE_REG_0 */ - { "fxsave", { FXSAVE } }, + { "fxsave", { FXSAVE }, 0 }, { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, }, { /* MOD_0FAE_REG_1 */ - { "fxrstor", { FXSAVE } }, + { "fxrstor", { FXSAVE }, 0 }, { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, }, { /* MOD_0FAE_REG_2 */ - { "ldmxcsr", { Md } }, + { "ldmxcsr", { Md }, 0 }, { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, }, { /* MOD_0FAE_REG_3 */ - { "stmxcsr", { Md } }, + { "stmxcsr", { Md }, 0 }, { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, }, { /* MOD_0FAE_REG_4 */ - { "xsave", { FXSAVE } }, + { "xsave", { FXSAVE }, 0 }, }, { /* MOD_0FAE_REG_5 */ - { "xrstor", { FXSAVE } }, + { "xrstor", { FXSAVE }, 0 }, { RM_TABLE (RM_0FAE_REG_5) }, }, { /* MOD_0FAE_REG_6 */ - { "xsaveopt", { FXSAVE } }, + { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, { RM_TABLE (RM_0FAE_REG_6) }, }, { @@ -11300,68 +11876,72 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FB2 */ - { "lssS", { Gv, Mp } }, + { "lssS", { Gv, Mp }, 0 }, }, { /* MOD_0FB4 */ - { "lfsS", { Gv, Mp } }, + { "lfsS", { Gv, Mp }, 0 }, }, { /* MOD_0FB5 */ - { "lgsS", { Gv, Mp } }, + { "lgsS", { Gv, Mp }, 0 }, + }, + { + /* MOD_0FC3 */ + { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, }, { /* MOD_0FC7_REG_3 */ - { "xrstors", { FXSAVE } }, + { "xrstors", { FXSAVE }, 0 }, }, { /* MOD_0FC7_REG_4 */ - { "xsavec", { FXSAVE } }, + { "xsavec", { FXSAVE }, 0 }, }, { /* MOD_0FC7_REG_5 */ - { "xsaves", { FXSAVE } }, + { "xsaves", { FXSAVE }, 0 }, }, { /* MOD_0FC7_REG_6 */ - { PREFIX_TABLE (PREFIX_0FC7_REG_6) }, - { "rdrand", { Ev } }, + { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, + { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } }, { /* MOD_0FC7_REG_7 */ - { "vmptrst", { Mq } }, - { "rdseed", { Ev } }, + { "vmptrst", { Mq }, 0 }, + { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } }, { /* MOD_0FD7 */ { Bad_Opcode }, - { "pmovmskb", { Gdq, MS } }, + { "pmovmskb", { Gdq, MS }, 0 }, }, { /* MOD_0FE7_PREFIX_2 */ - { "movntdq", { Mx, XM } }, + { "movntdq", { Mx, XM }, 0 }, }, { /* MOD_0FF0_PREFIX_3 */ - { "lddqu", { XM, M } }, + { "lddqu", { XM, M }, 0 }, }, { /* MOD_0F382A_PREFIX_2 */ - { "movntdqa", { XM, Mx } }, + { "movntdqa", { XM, Mx }, 0 }, }, { /* MOD_62_32BIT */ - { "bound{S|}", { Gv, Ma } }, + { "bound{S|}", { Gv, Ma }, 0 }, { EVEX_TABLE (EVEX_0F) }, }, { /* MOD_C4_32BIT */ - { "lesS", { Gv, Mp } }, + { "lesS", { Gv, Mp }, 0 }, { VEX_C4_TABLE (VEX_0F) }, }, { /* MOD_C5_32BIT */ - { "ldsS", { Gv, Mp } }, + { "ldsS", { Gv, Mp }, 0 }, { VEX_C5_TABLE (VEX_0F) }, }, { @@ -11387,184 +11967,486 @@ static const struct dis386 mod_table[][2] = { { VEX_W_TABLE (VEX_W_0F2B_M_0) }, }, { - /* MOD_VEX_0F50 */ + /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F50_M_0) }, + { "kandw", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F71_REG_2 */ + /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, + { "kandq", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F71_REG_4 */ + /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, + { "kandb", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F71_REG_6 */ + /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, + { "kandd", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F72_REG_2 */ + /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, + { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F72_REG_4 */ + /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, + { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F72_REG_6 */ + /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, + { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F73_REG_2 */ + /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, + { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F73_REG_3 */ + /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, + { "knotw", { MaskG, MaskR }, 0 }, }, { - /* MOD_VEX_0F73_REG_6 */ + /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, + { "knotq", { MaskG, MaskR }, 0 }, }, { - /* MOD_VEX_0F73_REG_7 */ + /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, + { "knotb", { MaskG, MaskR }, 0 }, }, { - /* MOD_VEX_0FAE_REG_2 */ - { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, + /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ + { Bad_Opcode }, + { "knotd", { MaskG, MaskR }, 0 }, }, { - /* MOD_VEX_0FAE_REG_3 */ - { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, + /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ + { Bad_Opcode }, + { "korw", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0FD7_PREFIX_2 */ + /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, + { "korq", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0FE7_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, + /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ + { Bad_Opcode }, + { "korb", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0FF0_PREFIX_3 */ - { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, + /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ + { Bad_Opcode }, + { "kord", { MaskG, MaskVex, MaskR }, 0 }, }, - { - /* MOD_VEX_0F381A_PREFIX_2 */ - { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, + { + /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ + { Bad_Opcode }, + { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F382A_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, + /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ + { Bad_Opcode }, + { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F382C_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, + /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ + { Bad_Opcode }, + { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F382D_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, + /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ + { Bad_Opcode }, + { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F382E_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, + /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ + { Bad_Opcode }, + { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F382F_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, + /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ + { Bad_Opcode }, + { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F385A_PREFIX_2 */ - { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, + /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ + { Bad_Opcode }, + { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F388C_PREFIX_2 */ - { "vpmaskmov%LW", { XM, Vex, Mx } }, + /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ + { Bad_Opcode }, + { "kxord", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* MOD_VEX_0F388E_PREFIX_2 */ - { "vpmaskmov%LW", { Mx, Vex, XM } }, + /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ + { Bad_Opcode }, + { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, }, -#define NEED_MOD_TABLE -#include "i386-dis-evex.h" -#undef NEED_MOD_TABLE -}; - -static const struct dis386 rm_table[][8] = { { - /* RM_C6_REG_7 */ - { "xabort", { Skip_MODRM, Ib } }, + /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ + { Bad_Opcode }, + { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* RM_C7_REG_7 */ - { "xbeginT", { Skip_MODRM, Jv } }, + /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ + { Bad_Opcode }, + { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* RM_0F01_REG_0 */ + /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ { Bad_Opcode }, - { "vmcall", { Skip_MODRM } }, - { "vmlaunch", { Skip_MODRM } }, - { "vmresume", { Skip_MODRM } }, - { "vmxoff", { Skip_MODRM } }, + { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* RM_0F01_REG_1 */ - { "monitor", { { OP_Monitor, 0 } } }, - { "mwait", { { OP_Mwait, 0 } } }, - { "clac", { Skip_MODRM } }, - { "stac", { Skip_MODRM } }, + /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ + { Bad_Opcode }, + { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* RM_0F01_REG_2 */ - { "xgetbv", { Skip_MODRM } }, - { "xsetbv", { Skip_MODRM } }, - { Bad_Opcode }, - { Bad_Opcode }, - { "vmfunc", { Skip_MODRM } }, - { "xend", { Skip_MODRM } }, - { "xtest", { Skip_MODRM } }, + /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ { Bad_Opcode }, + { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* RM_0F01_REG_3 */ - { "vmrun", { Skip_MODRM } }, - { "vmmcall", { Skip_MODRM } }, - { "vmload", { Skip_MODRM } }, - { "vmsave", { Skip_MODRM } }, - { "stgi", { Skip_MODRM } }, - { "clgi", { Skip_MODRM } }, - { "skinit", { Skip_MODRM } }, - { "invlpga", { Skip_MODRM } }, + /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ + { Bad_Opcode }, + { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, }, { - /* RM_0F01_REG_7 */ - { "swapgs", { Skip_MODRM } }, - { "rdtscp", { Skip_MODRM } }, + /* MOD_VEX_0F50 */ + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F50_M_0) }, + }, + { + /* MOD_VEX_0F71_REG_2 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, + }, + { + /* MOD_VEX_0F71_REG_4 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, + }, + { + /* MOD_VEX_0F71_REG_6 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, + }, + { + /* MOD_VEX_0F72_REG_2 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, + }, + { + /* MOD_VEX_0F72_REG_4 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, + }, + { + /* MOD_VEX_0F72_REG_6 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, + }, + { + /* MOD_VEX_0F73_REG_2 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, + }, + { + /* MOD_VEX_0F73_REG_3 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, + }, + { + /* MOD_VEX_0F73_REG_6 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, + }, + { + /* MOD_VEX_0F73_REG_7 */ + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, + }, + { + /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ + { "kmovw", { Ew, MaskG }, 0 }, + { Bad_Opcode }, + }, + { + /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ + { "kmovq", { Eq, MaskG }, 0 }, + { Bad_Opcode }, + }, + { + /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ + { "kmovb", { Eb, MaskG }, 0 }, + { Bad_Opcode }, + }, + { + /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ + { "kmovd", { Ed, MaskG }, 0 }, + { Bad_Opcode }, + }, + { + /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ + { Bad_Opcode }, + { "kmovw", { MaskG, Rdq }, 0 }, + }, + { + /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ + { Bad_Opcode }, + { "kmovb", { MaskG, Rdq }, 0 }, + }, + { + /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ + { Bad_Opcode }, + { "kmovd", { MaskG, Rdq }, 0 }, + }, + { + /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ + { Bad_Opcode }, + { "kmovq", { MaskG, Rdq }, 0 }, + }, + { + /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ + { Bad_Opcode }, + { "kmovw", { Gdq, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ + { Bad_Opcode }, + { "kmovb", { Gdq, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ + { Bad_Opcode }, + { "kmovd", { Gdq, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ + { Bad_Opcode }, + { "kmovq", { Gdq, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ + { Bad_Opcode }, + { "kortestw", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ + { Bad_Opcode }, + { "kortestq", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ + { Bad_Opcode }, + { "kortestb", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ + { Bad_Opcode }, + { "kortestd", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ + { Bad_Opcode }, + { "ktestw", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ + { Bad_Opcode }, + { "ktestq", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ + { Bad_Opcode }, + { "ktestb", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ + { Bad_Opcode }, + { "ktestd", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_0FAE_REG_2 */ + { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, + }, + { + /* MOD_VEX_0FAE_REG_3 */ + { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, + }, + { + /* MOD_VEX_0FD7_PREFIX_2 */ + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, + }, + { + /* MOD_VEX_0FE7_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, + }, + { + /* MOD_VEX_0FF0_PREFIX_3 */ + { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, + }, + { + /* MOD_VEX_0F381A_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382A_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382C_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382D_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382E_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, + }, + { + /* MOD_VEX_0F382F_PREFIX_2 */ + { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, + }, + { + /* MOD_VEX_0F385A_PREFIX_2 */ + { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, + }, + { + /* MOD_VEX_0F388C_PREFIX_2 */ + { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, + }, + { + /* MOD_VEX_0F388E_PREFIX_2 */ + { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, + }, + { + /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftld", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, + }, +#define NEED_MOD_TABLE +#include "i386-dis-evex.h" +#undef NEED_MOD_TABLE +}; + +static const struct dis386 rm_table[][8] = { + { + /* RM_C6_REG_7 */ + { "xabort", { Skip_MODRM, Ib }, 0 }, + }, + { + /* RM_C7_REG_7 */ + { "xbeginT", { Skip_MODRM, Jv }, 0 }, + }, + { + /* RM_0F01_REG_0 */ + { Bad_Opcode }, + { "vmcall", { Skip_MODRM }, 0 }, + { "vmlaunch", { Skip_MODRM }, 0 }, + { "vmresume", { Skip_MODRM }, 0 }, + { "vmxoff", { Skip_MODRM }, 0 }, + }, + { + /* RM_0F01_REG_1 */ + { "monitor", { { OP_Monitor, 0 } }, 0 }, + { "mwait", { { OP_Mwait, 0 } }, 0 }, + { "clac", { Skip_MODRM }, 0 }, + { "stac", { Skip_MODRM }, 0 }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "encls", { Skip_MODRM }, 0 }, + }, + { + /* RM_0F01_REG_2 */ + { "xgetbv", { Skip_MODRM }, 0 }, + { "xsetbv", { Skip_MODRM }, 0 }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vmfunc", { Skip_MODRM }, 0 }, + { "xend", { Skip_MODRM }, 0 }, + { "xtest", { Skip_MODRM }, 0 }, + { "enclu", { Skip_MODRM }, 0 }, + }, + { + /* RM_0F01_REG_3 */ + { "vmrun", { Skip_MODRM }, 0 }, + { "vmmcall", { Skip_MODRM }, 0 }, + { "vmload", { Skip_MODRM }, 0 }, + { "vmsave", { Skip_MODRM }, 0 }, + { "stgi", { Skip_MODRM }, 0 }, + { "clgi", { Skip_MODRM }, 0 }, + { "skinit", { Skip_MODRM }, 0 }, + { "invlpga", { Skip_MODRM }, 0 }, + }, + { + /* RM_0F01_REG_7 */ + { "swapgs", { Skip_MODRM }, 0 }, + { "rdtscp", { Skip_MODRM }, 0 }, + { "monitorx", { { OP_Monitor, 0 } }, 0 }, + { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, + { "clzero", { Skip_MODRM }, 0 }, }, { /* RM_0FAE_REG_5 */ - { "lfence", { Skip_MODRM } }, + { "lfence", { Skip_MODRM }, 0 }, }, { /* RM_0FAE_REG_6 */ - { "mfence", { Skip_MODRM } }, + { "mfence", { Skip_MODRM }, 0 }, }, { /* RM_0FAE_REG_7 */ - { "sfence", { Skip_MODRM } }, + { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, }, }; @@ -11572,10 +12454,6 @@ static const struct dis386 rm_table[][8] = { /* We use the high bit to indicate different name for the same prefix. */ -#define ADDR16_PREFIX (0x67 | 0x100) -#define ADDR32_PREFIX (0x67 | 0x200) -#define DATA16_PREFIX (0x66 | 0x100) -#define DATA32_PREFIX (0x66 | 0x200) #define REP_PREFIX (0xf3 | 0x100) #define XACQUIRE_PREFIX (0xf2 | 0x200) #define XRELEASE_PREFIX (0xf3 | 0x400) @@ -11597,6 +12475,8 @@ ckprefix (void) last_addr_prefix = -1; last_rex_prefix = -1; last_seg_prefix = -1; + fwait_prefix = -1; + active_seg_prefix = 0; for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) all_prefixes[i] = 0; i = 0; @@ -11646,26 +12526,32 @@ ckprefix (void) case 0x2e: prefixes |= PREFIX_CS; last_seg_prefix = i; + active_seg_prefix = PREFIX_CS; break; case 0x36: prefixes |= PREFIX_SS; last_seg_prefix = i; + active_seg_prefix = PREFIX_SS; break; case 0x3e: prefixes |= PREFIX_DS; last_seg_prefix = i; + active_seg_prefix = PREFIX_DS; break; case 0x26: prefixes |= PREFIX_ES; last_seg_prefix = i; + active_seg_prefix = PREFIX_ES; break; case 0x64: prefixes |= PREFIX_FS; last_seg_prefix = i; + active_seg_prefix = PREFIX_FS; break; case 0x65: prefixes |= PREFIX_GS; last_seg_prefix = i; + active_seg_prefix = PREFIX_GS; break; case 0x66: prefixes |= PREFIX_DATA; @@ -11679,6 +12565,7 @@ ckprefix (void) /* fwait is really an instruction. If there are prefixes before the fwait, they belong to the fwait, *not* to the following instruction. */ + fwait_prefix = i; if (prefixes || rex) { prefixes |= PREFIX_FWAIT; @@ -11708,28 +12595,6 @@ ckprefix (void) return 0; } -static int -seg_prefix (int pref) -{ - switch (pref) - { - case 0x2e: - return PREFIX_CS; - case 0x36: - return PREFIX_SS; - case 0x3e: - return PREFIX_DS; - case 0x26: - return PREFIX_ES; - case 0x64: - return PREFIX_FS; - case 0x65: - return PREFIX_GS; - default: - return 0; - } -} - /* Return the name of the prefix byte PREF, or NULL if PREF is not a prefix byte. */ @@ -11803,14 +12668,6 @@ prefix_name (int pref, int sizeflag) return (sizeflag & AFLAG) ? "addr16" : "addr32"; case FWAIT_OPCODE: return "fwait"; - case ADDR16_PREFIX: - return "addr16"; - case ADDR32_PREFIX: - return "addr32"; - case DATA16_PREFIX: - return "data16"; - case DATA32_PREFIX: - return "data32"; case REP_PREFIX: return "rep"; case XACQUIRE_PREFIX: @@ -11847,6 +12704,14 @@ static char close_char; static char separator_char; static char scale_char; +enum x86_64_isa +{ + amd64 = 0, + intel64 +}; + +static enum x86_64_isa isa64; + /* Here for backwards compatibility. When gdb stops using print_insn_i386_att and print_insn_i386_intel these functions can disappear, and print_insn_i386 be merged into print_insn. */ @@ -11896,10 +12761,12 @@ with the -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _(" data32 Assume 32bit data size\n")); fprintf (stream, _(" data16 Assume 16bit data size\n")); fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); + fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); + fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); } /* Bad opcode. */ -static const struct dis386 bad_opcode = { "(bad)", { XX } }; +static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; /* Get a pointer to struct dis386 with a valid name. */ @@ -11951,32 +12818,45 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) } else { + int last_prefix = -1; + int prefix = 0; vindex = 0; - used_prefixes |= (prefixes & PREFIX_REPZ); - if (prefixes & PREFIX_REPZ) - { - vindex = 1; - all_prefixes[last_repz_prefix] = 0; - } - else + /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. + When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the + last one wins. */ + if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) { - /* We should check PREFIX_REPNZ and PREFIX_REPZ before - PREFIX_DATA. */ - used_prefixes |= (prefixes & PREFIX_REPNZ); - if (prefixes & PREFIX_REPNZ) + if (last_repz_prefix > last_repnz_prefix) { - vindex = 3; - all_prefixes[last_repnz_prefix] = 0; + vindex = 1; + prefix = PREFIX_REPZ; + last_prefix = last_repz_prefix; } else { - used_prefixes |= (prefixes & PREFIX_DATA); - if (prefixes & PREFIX_DATA) - { - vindex = 2; - all_prefixes[last_data_prefix] = 0; - } + vindex = 3; + prefix = PREFIX_REPNZ; + last_prefix = last_repnz_prefix; } + + /* Check if prefix should be ignored. */ + if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement + & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) + & prefix) != 0) + vindex = 0; + } + + if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) + { + vindex = 2; + prefix = PREFIX_DATA; + last_prefix = last_data_prefix; + } + + if (vindex != 0) + { + used_prefixes |= prefix; + all_prefixes[last_prefix] = 0; } } dp = &prefix_table[dp->op[1].bytemode][vindex]; @@ -11991,6 +12871,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) FETCH_DATA (info, codep + 2); vindex = *codep++; dp = &three_byte_table[dp->op[1].bytemode][vindex]; + end_codep = codep; modrm.mod = (*codep >> 6) & 3; modrm.reg = (*codep >> 3) & 7; modrm.rm = *codep & 7; @@ -12073,6 +12954,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vindex = *codep++; dp = &xop_table[vex_table_index][vindex]; + end_codep = codep; FETCH_DATA (info, codep + 1); modrm.mod = (*codep >> 6) & 3; modrm.reg = (*codep >> 3) & 7; @@ -12134,6 +13016,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) codep++; vindex = *codep++; dp = &vex_table[vex_table_index][vindex]; + end_codep = codep; /* There is no MODRM byte for VEX [82|77]. */ if (vindex != 0x77 && vindex != 0x82) { @@ -12182,6 +13065,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) codep++; vindex = *codep++; dp = &vex_table[dp->op[1].bytemode][vindex]; + end_codep = codep; /* There is no MODRM byte for VEX [82|77]. */ if (vindex != 0x77 && vindex != 0x82) { @@ -12276,6 +13160,7 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) codep++; vindex = *codep++; dp = &evex_table[vex_table_index][vindex]; + end_codep = codep; FETCH_DATA (info, codep + 1); modrm.mod = (*codep >> 6) & 3; modrm.reg = (*codep >> 3) & 7; @@ -12340,11 +13225,10 @@ print_insn (bfd_vma pc, disassemble_info *info) int i; char *op_txt[MAX_OPERANDS]; int needcomma; - int sizeflag; + int sizeflag, orig_sizeflag; const char *p; struct dis_private priv; int prefix_length; - int default_prefixes; priv.orig_sizeflag = AFLAG | DFLAG; if ((info->mach & bfd_mach_i386_i386) != 0) @@ -12362,7 +13246,11 @@ print_insn (bfd_vma pc, disassemble_info *info) for (p = info->disassembler_options; p != NULL; ) { - if (CONST_STRNEQ (p, "x86-64")) + if (CONST_STRNEQ (p, "amd64")) + isa64 = amd64; + else if (CONST_STRNEQ (p, "intel64")) + isa64 = intel64; + else if (CONST_STRNEQ (p, "x86-64")) { address_mode = mode_64bit; priv.orig_sizeflag = AFLAG | DFLAG; @@ -12490,7 +13378,7 @@ print_insn (bfd_vma pc, disassemble_info *info) start_codep = priv.the_buffer; codep = priv.the_buffer; - if (setjmp (priv.bailout) != 0) + if (OPCODES_SIGSETJMP (priv.bailout) != 0) { const char *name; @@ -12538,15 +13426,22 @@ print_insn (bfd_vma pc, disassemble_info *info) if (((prefixes & PREFIX_FWAIT) && ((*codep < 0xd8) || (*codep > 0xdf)))) { + /* Handle prefixes before fwait. */ + for (i = 0; i < fwait_prefix && all_prefixes[i]; + i++) + (*info->fprintf_func) (info->stream, "%s ", + prefix_name (all_prefixes[i], sizeflag)); (*info->fprintf_func) (info->stream, "fwait"); - return 1; + return i + 1; } if (*codep == 0x0f) { unsigned char threebyte; - FETCH_DATA (info, codep + 2); - threebyte = *++codep; + + codep++; + FETCH_DATA (info, codep + 1); + threebyte = *codep; dp = &dis386_twobyte[threebyte]; need_modrm = twobyte_has_modrm[*codep]; codep++; @@ -12558,47 +13453,16 @@ print_insn (bfd_vma pc, disassemble_info *info) codep++; } - if ((prefixes & PREFIX_REPZ)) - used_prefixes |= PREFIX_REPZ; - if ((prefixes & PREFIX_REPNZ)) - used_prefixes |= PREFIX_REPNZ; - if ((prefixes & PREFIX_LOCK)) - used_prefixes |= PREFIX_LOCK; - - default_prefixes = 0; + /* Save sizeflag for printing the extra prefixes later before updating + it for mnemonic and operand processing. The prefix names depend + only on the address mode. */ + orig_sizeflag = sizeflag; if (prefixes & PREFIX_ADDR) - { - sizeflag ^= AFLAG; - if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax) - { - if ((sizeflag & AFLAG) || address_mode == mode_64bit) - all_prefixes[last_addr_prefix] = ADDR32_PREFIX; - else - all_prefixes[last_addr_prefix] = ADDR16_PREFIX; - default_prefixes |= PREFIX_ADDR; - } - } - + sizeflag ^= AFLAG; if ((prefixes & PREFIX_DATA)) - { - sizeflag ^= DFLAG; - if (dp->op[2].bytemode == cond_jump_mode - && dp->op[0].bytemode == v_mode - && !intel_syntax) - { - if (sizeflag & DFLAG) - all_prefixes[last_data_prefix] = DATA32_PREFIX; - else - all_prefixes[last_data_prefix] = DATA16_PREFIX; - default_prefixes |= PREFIX_DATA; - } - else if (rex & REX_W) - { - /* REX_W will override PREFIX_DATA. */ - default_prefixes |= PREFIX_DATA; - } - } + sizeflag ^= DFLAG; + end_codep = codep; if (need_modrm) { FETCH_DATA (info, codep + 1); @@ -12647,24 +13511,6 @@ print_insn (bfd_vma pc, disassemble_info *info) } } - /* See if any prefixes were not used. If so, print the first one - separately. If we don't do this, we'll wind up printing an - instruction stream which does not precisely correspond to the - bytes we are disassembling. */ - if ((prefixes & ~(used_prefixes | default_prefixes)) != 0) - { - for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) - if (all_prefixes[i]) - { - const char *name; - name = prefix_name (all_prefixes[i], priv.orig_sizeflag); - if (name == NULL) - name = INTERNAL_DISASSEMBLER_ERROR; - (*info->fprintf_func) (info->stream, "%s", name); - return 1; - } - } - /* Check if the REX prefix is used. */ if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) all_prefixes[last_rex_prefix] = 0; @@ -12672,8 +13518,7 @@ print_insn (bfd_vma pc, disassemble_info *info) /* Check if the SEG prefix is used. */ if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES | PREFIX_FS | PREFIX_GS)) != 0 - && (used_prefixes - & seg_prefix (all_prefixes[last_seg_prefix])) != 0) + && (used_prefixes & active_seg_prefix) != 0) all_prefixes[last_seg_prefix] = 0; /* Check if the ADDR prefix is used. */ @@ -12686,18 +13531,39 @@ print_insn (bfd_vma pc, disassemble_info *info) && (used_prefixes & PREFIX_DATA) != 0) all_prefixes[last_data_prefix] = 0; + /* Print the extra prefixes. */ prefix_length = 0; for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) if (all_prefixes[i]) { const char *name; - name = prefix_name (all_prefixes[i], sizeflag); + name = prefix_name (all_prefixes[i], orig_sizeflag); if (name == NULL) abort (); prefix_length += strlen (name) + 1; (*info->fprintf_func) (info->stream, "%s ", name); } + /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is + unused, opcode is invalid. Since the PREFIX_DATA prefix may be + used by putop and MMX/SSE operand and may be overriden by the + PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix + separately. */ + if (dp->prefix_requirement == PREFIX_OPCODE + && dp != &bad_opcode + && (((prefixes + & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 + && (used_prefixes + & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) + || ((((prefixes + & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) + == PREFIX_DATA) + && (used_prefixes & PREFIX_DATA) == 0)))) + { + (*info->fprintf_func) (info->stream, "(bad)"); + return end_codep - priv.the_buffer; + } + /* Check maximum code length. */ if ((codep - start_codep) > MAX_CODE_LENGTH) { @@ -12720,6 +13586,13 @@ print_insn (bfd_vma pc, disassemble_info *info) for (i = 0; i < MAX_OPERANDS; ++i) op_txt[i] = op_out[i]; + if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding + && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) + { + op_txt[2] = op_out[3]; + op_txt[3] = op_out[2]; + } + for (i = 0; i < (MAX_OPERANDS >> 1); ++i) { op_ad = op_index[i]; @@ -12913,32 +13786,32 @@ static const unsigned char float_mem_mode[] = { #define ST { OP_ST, 0 } #define STi { OP_STi, 0 } -#define FGRPd9_2 NULL, { { NULL, 0 } } -#define FGRPd9_4 NULL, { { NULL, 1 } } -#define FGRPd9_5 NULL, { { NULL, 2 } } -#define FGRPd9_6 NULL, { { NULL, 3 } } -#define FGRPd9_7 NULL, { { NULL, 4 } } -#define FGRPda_5 NULL, { { NULL, 5 } } -#define FGRPdb_4 NULL, { { NULL, 6 } } -#define FGRPde_3 NULL, { { NULL, 7 } } -#define FGRPdf_4 NULL, { { NULL, 8 } } +#define FGRPd9_2 NULL, { { NULL, 0 } }, 0 +#define FGRPd9_4 NULL, { { NULL, 1 } }, 0 +#define FGRPd9_5 NULL, { { NULL, 2 } }, 0 +#define FGRPd9_6 NULL, { { NULL, 3 } }, 0 +#define FGRPd9_7 NULL, { { NULL, 4 } }, 0 +#define FGRPda_5 NULL, { { NULL, 5 } }, 0 +#define FGRPdb_4 NULL, { { NULL, 6 } }, 0 +#define FGRPde_3 NULL, { { NULL, 7 } }, 0 +#define FGRPdf_4 NULL, { { NULL, 8 } }, 0 static const struct dis386 float_reg[][8] = { /* d8 */ { - { "fadd", { ST, STi } }, - { "fmul", { ST, STi } }, - { "fcom", { STi } }, - { "fcomp", { STi } }, - { "fsub", { ST, STi } }, - { "fsubr", { ST, STi } }, - { "fdiv", { ST, STi } }, - { "fdivr", { ST, STi } }, + { "fadd", { ST, STi }, 0 }, + { "fmul", { ST, STi }, 0 }, + { "fcom", { STi }, 0 }, + { "fcomp", { STi }, 0 }, + { "fsub", { ST, STi }, 0 }, + { "fsubr", { ST, STi }, 0 }, + { "fdiv", { ST, STi }, 0 }, + { "fdivr", { ST, STi }, 0 }, }, /* d9 */ { - { "fld", { STi } }, - { "fxch", { STi } }, + { "fld", { STi }, 0 }, + { "fxch", { STi }, 0 }, { FGRPd9_2 }, { Bad_Opcode }, { FGRPd9_4 }, @@ -12948,10 +13821,10 @@ static const struct dis386 float_reg[][8] = { }, /* da */ { - { "fcmovb", { ST, STi } }, - { "fcmove", { ST, STi } }, - { "fcmovbe",{ ST, STi } }, - { "fcmovu", { ST, STi } }, + { "fcmovb", { ST, STi }, 0 }, + { "fcmove", { ST, STi }, 0 }, + { "fcmovbe",{ ST, STi }, 0 }, + { "fcmovu", { ST, STi }, 0 }, { Bad_Opcode }, { FGRPda_5 }, { Bad_Opcode }, @@ -12959,57 +13832,57 @@ static const struct dis386 float_reg[][8] = { }, /* db */ { - { "fcmovnb",{ ST, STi } }, - { "fcmovne",{ ST, STi } }, - { "fcmovnbe",{ ST, STi } }, - { "fcmovnu",{ ST, STi } }, + { "fcmovnb",{ ST, STi }, 0 }, + { "fcmovne",{ ST, STi }, 0 }, + { "fcmovnbe",{ ST, STi }, 0 }, + { "fcmovnu",{ ST, STi }, 0 }, { FGRPdb_4 }, - { "fucomi", { ST, STi } }, - { "fcomi", { ST, STi } }, + { "fucomi", { ST, STi }, 0 }, + { "fcomi", { ST, STi }, 0 }, { Bad_Opcode }, }, /* dc */ { - { "fadd", { STi, ST } }, - { "fmul", { STi, ST } }, + { "fadd", { STi, ST }, 0 }, + { "fmul", { STi, ST }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "fsub!M", { STi, ST } }, - { "fsubM", { STi, ST } }, - { "fdiv!M", { STi, ST } }, - { "fdivM", { STi, ST } }, + { "fsub!M", { STi, ST }, 0 }, + { "fsubM", { STi, ST }, 0 }, + { "fdiv!M", { STi, ST }, 0 }, + { "fdivM", { STi, ST }, 0 }, }, /* dd */ { - { "ffree", { STi } }, + { "ffree", { STi }, 0 }, { Bad_Opcode }, - { "fst", { STi } }, - { "fstp", { STi } }, - { "fucom", { STi } }, - { "fucomp", { STi } }, + { "fst", { STi }, 0 }, + { "fstp", { STi }, 0 }, + { "fucom", { STi }, 0 }, + { "fucomp", { STi }, 0 }, { Bad_Opcode }, { Bad_Opcode }, }, /* de */ { - { "faddp", { STi, ST } }, - { "fmulp", { STi, ST } }, + { "faddp", { STi, ST }, 0 }, + { "fmulp", { STi, ST }, 0 }, { Bad_Opcode }, { FGRPde_3 }, - { "fsub!Mp", { STi, ST } }, - { "fsubMp", { STi, ST } }, - { "fdiv!Mp", { STi, ST } }, - { "fdivMp", { STi, ST } }, + { "fsub!Mp", { STi, ST }, 0 }, + { "fsubMp", { STi, ST }, 0 }, + { "fdiv!Mp", { STi, ST }, 0 }, + { "fdivMp", { STi, ST }, 0 }, }, /* df */ { - { "ffreep", { STi } }, + { "ffreep", { STi }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { FGRPdf_4 }, - { "fucomip", { ST, STi } }, - { "fcomip", { ST, STi } }, + { "fucomip", { ST, STi }, 0 }, + { "fcomip", { ST, STi }, 0 }, { Bad_Opcode }, }, }; @@ -13328,6 +14201,34 @@ case_B: *obufp++ = 'd'; break; case 'Z': + if (l != 0 || len != 1) + { + if (l != 1 || len != 2 || last[0] != 'X') + { + SAVE_LAST (*p); + break; + } + if (!need_vex || !vex.evex) + abort (); + if (intel_syntax + || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) + break; + switch (vex.length) + { + case 128: + *obufp++ = 'x'; + break; + case 256: + *obufp++ = 'y'; + break; + case 512: + *obufp++ = 'z'; + break; + default: + abort (); + } + break; + } if (intel_syntax) break; if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) @@ -13379,32 +14280,62 @@ case_L: break; } /* Fall through. */ + goto case_P; case 'P': - if (intel_syntax) + if (l == 0 && len == 1) { - if ((rex & REX_W) == 0 - && (prefixes & PREFIX_DATA)) +case_P: + if (intel_syntax) { - if ((sizeflag & DFLAG) == 0) - *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); + if ((rex & REX_W) == 0 + && (prefixes & PREFIX_DATA)) + { + if ((sizeflag & DFLAG) == 0) + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + } + if ((prefixes & PREFIX_DATA) + || (rex & REX_W) + || (sizeflag & SUFFIX_ALWAYS)) + { + USED_REX (REX_W); + if (rex & REX_W) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } } - break; } - if ((prefixes & PREFIX_DATA) - || (rex & REX_W) - || (sizeflag & SUFFIX_ALWAYS)) + else { - USED_REX (REX_W); - if (rex & REX_W) - *obufp++ = 'q'; - else + if (l != 1 || len != 2 || last[0] != 'L') + { + SAVE_LAST (*p); + break; + } + + if ((prefixes & PREFIX_DATA) + || (rex & REX_W) + || (sizeflag & SUFFIX_ALWAYS)) { - if (sizeflag & DFLAG) - *obufp++ = 'l'; - else - *obufp++ = 'w'; - used_prefixes |= (prefixes & PREFIX_DATA); + USED_REX (REX_W); + if (rex & REX_W) + *obufp++ = 'q'; + else + { + if (sizeflag & DFLAG) + *obufp++ = intel_syntax ? 'd' : 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } } } break; @@ -13596,7 +14527,7 @@ case_S: if (!need_vex) abort (); if (intel_syntax - || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) + || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) break; switch (vex.length) { @@ -13606,8 +14537,10 @@ case_S: case 256: *obufp++ = 'y'; break; + case 512: + if (!vex.evex) default: - abort (); + abort (); } } break; @@ -13648,6 +14581,32 @@ case_S: *obufp++ = vex.w ? 'q': 'd'; } break; + case '^': + if (intel_syntax) + break; + if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) + { + if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case '@': + if (intel_syntax) + break; + if (address_mode == mode_64bit + && (isa64 == intel64 + || ((sizeflag & DFLAG) || (rex & REX_W)))) + *obufp++ = 'q'; + else if ((prefixes & PREFIX_DATA)) + { + if (!(sizeflag & DFLAG)) + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; } alt = 0; } @@ -13665,35 +14624,33 @@ oappend (const char *s) static void append_seg (void) { - if (prefixes & PREFIX_CS) + /* Only print the active segment register. */ + if (!active_seg_prefix) + return; + + used_prefixes |= active_seg_prefix; + switch (active_seg_prefix) { - used_prefixes |= PREFIX_CS; + case PREFIX_CS: oappend_maybe_intel ("%cs:"); - } - if (prefixes & PREFIX_DS) - { - used_prefixes |= PREFIX_DS; + break; + case PREFIX_DS: oappend_maybe_intel ("%ds:"); - } - if (prefixes & PREFIX_SS) - { - used_prefixes |= PREFIX_SS; + break; + case PREFIX_SS: oappend_maybe_intel ("%ss:"); - } - if (prefixes & PREFIX_ES) - { - used_prefixes |= PREFIX_ES; + break; + case PREFIX_ES: oappend_maybe_intel ("%es:"); - } - if (prefixes & PREFIX_FS) - { - used_prefixes |= PREFIX_FS; + break; + case PREFIX_FS: oappend_maybe_intel ("%fs:"); - } - if (prefixes & PREFIX_GS) - { - used_prefixes |= PREFIX_GS; + break; + case PREFIX_GS: oappend_maybe_intel ("%gs:"); + break; + default: + break; } } @@ -13825,10 +14782,13 @@ intel_operand_size (int bytemode, int sizeflag) case b_mode: case b_swap_mode: case dqb_mode: + case db_mode: oappend ("BYTE PTR "); break; case w_mode: + case dw_mode: case dqw_mode: + case dqw_swap_mode: oappend ("WORD PTR "); break; case stack_v_mode: @@ -14105,20 +15065,58 @@ intel_operand_size (int bytemode, int sizeflag) } else { - if (vex.length != 512) - abort (); - oappend ("ZMMWORD PTR "); + switch (vex.length) + { + case 128: + oappend ("XMMWORD PTR "); + break; + case 256: + oappend ("YMMWORD PTR "); + break; + case 512: + oappend ("ZMMWORD PTR "); + break; + default: + abort (); + } + } + break; + case vex_vsib_q_w_d_mode: + case vex_vsib_d_w_d_mode: + if (!need_vex || !vex.evex) + abort (); + + switch (vex.length) + { + case 128: + oappend ("QWORD PTR "); + break; + case 256: + oappend ("XMMWORD PTR "); + break; + case 512: + oappend ("YMMWORD PTR "); + break; + default: + abort (); } + + break; + case mask_bd_mode: + if (!need_vex || vex.length != 128) + abort (); + if (vex.w) + oappend ("DWORD PTR "); + else + oappend ("BYTE PTR "); break; case mask_mode: if (!need_vex) abort (); - /* Currently the only instructions, which allows either mask or - memory operand, are AVX512's KMOVW instructions. They need - Word-sized operand. */ - if (vex.w || vex.length != 128) - abort (); - oappend ("WORD PTR "); + if (vex.w) + oappend ("QWORD PTR "); + else + oappend ("WORD PTR "); break; case v_bnd_mode: default: @@ -14137,7 +15135,9 @@ OP_E_register (int bytemode, int sizeflag) reg += 8; if ((sizeflag & SUFFIX_ALWAYS) - && (bytemode == b_swap_mode || bytemode == v_swap_mode)) + && (bytemode == b_swap_mode + || bytemode == v_swap_mode + || bytemode == dqw_swap_mode)) swap_operand (); switch (bytemode) @@ -14154,6 +15154,8 @@ OP_E_register (int bytemode, int sizeflag) names = names16; break; case d_mode: + case dw_mode: + case db_mode: names = names32; break; case q_mode: @@ -14180,6 +15182,7 @@ OP_E_register (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: + case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) names = names64; @@ -14194,6 +15197,7 @@ OP_E_register (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case mask_bd_mode: case mask_mode: names = names_mask; break; @@ -14219,6 +15223,7 @@ OP_E_memory (int bytemode, int sizeflag) /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ if (vex.b && bytemode != x_mode + && bytemode != xmmq_mode && bytemode != evex_half_bcst_xmmq_mode) { BadOp (); @@ -14226,14 +15231,26 @@ OP_E_memory (int bytemode, int sizeflag) } switch (bytemode) { + case dqw_mode: + case dw_mode: + case dqw_swap_mode: + shift = 1; + break; + case dqb_mode: + case db_mode: + shift = 0; + break; case vex_vsib_d_w_dq_mode: + case vex_vsib_d_w_d_mode: case vex_vsib_q_w_dq_mode: + case vex_vsib_q_w_d_mode: case evex_x_gscat_mode: case xmm_mdq_mode: shift = vex.w ? 3 : 2; break; case x_mode: case evex_half_bcst_xmmq_mode: + case xmmq_mode: if (vex.b) { shift = vex.w ? 3 : 2; @@ -14242,7 +15259,6 @@ OP_E_memory (int bytemode, int sizeflag) /* Fall through if vex.b == 0. */ case xmmqd_mode: case xmmdw_mode: - case xmmq_mode: case ymmq_mode: case evex_x_nobcst_mode: case x_swap_mode: @@ -14297,14 +15313,16 @@ OP_E_memory (int bytemode, int sizeflag) operand). We might want to make it 3, 4 or 5 (e.g. for xmmq_mode). In case of broadcast enabled the corrections aren't needed, as element size is always 32 or 64 bits. */ - if (bytemode == xmmq_mode - || (bytemode == evex_half_bcst_xmmq_mode - && !vex.b)) + if (!vex.b + && (bytemode == xmmq_mode + || bytemode == evex_half_bcst_xmmq_mode)) shift -= 1; else if (bytemode == xmmqd_mode) shift -= 2; else if (bytemode == xmmdw_mode) shift -= 3; + else if (bytemode == ymmq_mode && vex.length == 128) + shift -= 1; } else shift = 0; @@ -14346,7 +15364,9 @@ OP_E_memory (int bytemode, int sizeflag) switch (bytemode) { case vex_vsib_d_w_dq_mode: + case vex_vsib_d_w_d_mode: case vex_vsib_q_w_dq_mode: + case vex_vsib_q_w_d_mode: if (!need_vex) abort (); if (vex.evex) @@ -14362,13 +15382,17 @@ OP_E_memory (int bytemode, int sizeflag) indexes64 = indexes32 = names_xmm; break; case 256: - if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) + if (!vex.w + || bytemode == vex_vsib_q_w_dq_mode + || bytemode == vex_vsib_q_w_d_mode) indexes64 = indexes32 = names_ymm; else indexes64 = indexes32 = names_xmm; break; case 512: - if (!vex.w || bytemode == vex_vsib_q_w_dq_mode) + if (!vex.w + || bytemode == vex_vsib_q_w_dq_mode + || bytemode == vex_vsib_q_w_d_mode) indexes64 = indexes32 = names_zmm; else indexes64 = indexes32 = names_ymm; @@ -14509,10 +15533,7 @@ OP_E_memory (int bytemode, int sizeflag) { if (modrm.mod != 0 || base == 5) { - if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS)) - ; - else + if (!active_seg_prefix) { oappend (names_seg[ds_reg - es_reg]); oappend (":"); @@ -14585,10 +15606,7 @@ OP_E_memory (int bytemode, int sizeflag) } else if (intel_syntax) { - if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS)) - ; - else + if (!active_seg_prefix) { oappend (names_seg[ds_reg - es_reg]); oappend (":"); @@ -14599,12 +15617,45 @@ OP_E_memory (int bytemode, int sizeflag) } if (vex.evex && vex.b && (bytemode == x_mode + || bytemode == xmmq_mode || bytemode == evex_half_bcst_xmmq_mode)) { - if (vex.w || bytemode == evex_half_bcst_xmmq_mode) - oappend ("{1to8}"); + if (vex.w + || bytemode == xmmq_mode + || bytemode == evex_half_bcst_xmmq_mode) + { + switch (vex.length) + { + case 128: + oappend ("{1to2}"); + break; + case 256: + oappend ("{1to4}"); + break; + case 512: + oappend ("{1to8}"); + break; + default: + abort (); + } + } else - oappend ("{1to16}"); + { + switch (vex.length) + { + case 128: + oappend ("{1to4}"); + break; + case 256: + oappend ("{1to8}"); + break; + case 512: + oappend ("{1to16}"); + break; + default: + abort (); + } + } } } @@ -14641,6 +15692,8 @@ OP_G (int bytemode, int sizeflag) oappend (names16[modrm.reg + add]); break; case d_mode: + case db_mode: + case dw_mode: oappend (names32[modrm.reg + add]); break; case q_mode: @@ -14654,6 +15707,7 @@ OP_G (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: + case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) oappend (names64[modrm.reg + add]); @@ -14672,6 +15726,7 @@ OP_G (int bytemode, int sizeflag) else oappend (names32[modrm.reg + add]); break; + case mask_bd_mode: case mask_mode: oappend (names_mask[modrm.reg + add]); break; @@ -14693,11 +15748,11 @@ get64 (void) a = *codep++ & 0xff; a |= (*codep++ & 0xff) << 8; a |= (*codep++ & 0xff) << 16; - a |= (*codep++ & 0xff) << 24; + a |= (*codep++ & 0xffu) << 24; b = *codep++ & 0xff; b |= (*codep++ & 0xff) << 8; b |= (*codep++ & 0xff) << 16; - b |= (*codep++ & 0xff) << 24; + b |= (*codep++ & 0xffu) << 24; x = a + ((bfd_vma) b << 32); #else abort (); @@ -15068,8 +16123,11 @@ OP_J (int bytemode, int sizeflag) disp -= 0x100; break; case v_mode: - USED_REX (REX_W); - if ((sizeflag & DFLAG) || (rex & REX_W)) + if (isa64 == amd64) + USED_REX (REX_W); + if ((sizeflag & DFLAG) + || (address_mode == mode_64bit + && (isa64 != amd64 || (rex & REX_W)))) disp = get32s (); else { @@ -15085,7 +16143,8 @@ OP_J (int bytemode, int sizeflag) segment = ((start_pc + codep - start_codep) & ~((bfd_vma) 0xffff)); } - if (!(rex & REX_W)) + if (address_mode != mode_64bit + || (isa64 == amd64 && !(rex & REX_W))) used_prefixes |= (prefixes & PREFIX_DATA); break; default: @@ -15146,8 +16205,7 @@ OP_OFF (int bytemode, int sizeflag) if (intel_syntax) { - if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS))) + if (!active_seg_prefix) { oappend (names_seg[ds_reg - es_reg]); oappend (":"); @@ -15177,8 +16235,7 @@ OP_OFF64 (int bytemode, int sizeflag) if (intel_syntax) { - if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS))) + if (!active_seg_prefix) { oappend (names_seg[ds_reg - es_reg]); oappend (":"); @@ -15254,14 +16311,10 @@ OP_DSreg (int code, int sizeflag) intel_operand_size (b_mode, sizeflag); } } - if ((prefixes - & (PREFIX_CS - | PREFIX_DS - | PREFIX_SS - | PREFIX_ES - | PREFIX_FS - | PREFIX_GS)) == 0) - prefixes |= PREFIX_DS; + /* Set active_seg_prefix to PREFIX_DS if it is unset so that the + default segment register DS is printed. */ + if (!active_seg_prefix) + active_seg_prefix = PREFIX_DS; append_seg (); ptr_reg (code, sizeflag); } @@ -15313,10 +16366,10 @@ OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) static void OP_R (int bytemode, int sizeflag) { - if (modrm.mod == 3) - OP_E (bytemode, sizeflag); - else - BadOp (); + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + OP_E_register (bytemode, sizeflag); } static void @@ -15366,7 +16419,9 @@ OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) names = names_xmm; break; case 256: - if (vex.w || bytemode != vex_vsib_q_w_dq_mode) + if (vex.w + || (bytemode != vex_vsib_q_w_dq_mode + && bytemode != vex_vsib_q_w_d_mode)) names = names_ymm; else names = names_xmm; @@ -15502,6 +16557,7 @@ OP_EX (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == x_swap_mode || bytemode == d_swap_mode + || bytemode == dqw_swap_mode || bytemode == d_scalar_swap_mode || bytemode == q_swap_mode || bytemode == q_scalar_swap_mode)) @@ -15757,6 +16813,25 @@ CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) } } +static void +OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + /* mwaitx %eax,%ecx,%ebx */ + if (!intel_syntax) + { + const char **names = (address_mode == mode_64bit + ? names64 : names32); + strcpy (op_out[0], names[0]); + strcpy (op_out[1], names[1]); + strcpy (op_out[2], names[3]); + two_source_ops = 1; + } + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; +} + static void OP_Mwait (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) @@ -16072,6 +17147,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) case vex_mode: case vex128_mode: case vex_vsib_q_w_dq_mode: + case vex_vsib_q_w_d_mode: names = names_xmm; break; case dq_mode: @@ -16080,6 +17156,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) else names = names32; break; + case mask_bd_mode: case mask_mode: names = names_mask; break; @@ -16096,8 +17173,10 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) names = names_ymm; break; case vex_vsib_q_w_dq_mode: + case vex_vsib_q_w_d_mode: names = vex.w ? names_ymm : names_xmm; break; + case mask_bd_mode: case mask_mode: names = names_mask; break; @@ -16684,7 +17763,7 @@ static void OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { if (!vex.evex - || bytemode != mask_mode) + || (bytemode != mask_mode && bytemode != mask_bd_mode)) abort (); USED_REX (REX_R);