X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fi386-gen.c;h=18115dfcaab38282303ea79272668b81cda03ad4;hb=24b368f8532b4775f9fd5bcc7958a84d4218aa46;hp=7f66a1e26134afb193ac86e2c406a07121f11b17;hpb=2f81ff928644e457e4edbff1257e663845857f6b;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 7f66a1e261..18115dfcaa 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -1,5 +1,4 @@ -/* Copyright 2007, 2008, 2009, 2010, 2011, 2012, 2013 - Free Software Foundation, Inc. +/* Copyright (C) 2007-2015 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -81,7 +80,7 @@ static initializer cpu_flag_init[] = { "CPU_K6_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CpuMMX" }, { "CPU_K6_2_FLAGS", - "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CpuNop|CpuMMX|Cpu3dnow" }, + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CpuMMX|Cpu3dnow" }, { "CPU_ATHLON_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|Cpu387|Cpu687|CpuNop|CpuMMX|Cpu3dnow|Cpu3dnowA" }, { "CPU_K8_FLAGS", @@ -93,7 +92,11 @@ static initializer cpu_flag_init[] = { "CPU_BDVER2_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuFMA4|CpuXOP|CpuLWP|CpuBMI|CpuTBM|CpuF16C|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" }, { "CPU_BDVER3_FLAGS", - "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuFMA4|CpuXOP|CpuLWP|CpuBMI|CpuTBM|CpuF16C|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuXsave|CpuXsaveopt" }, + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuFMA4|CpuXOP|CpuLWP|CpuBMI|CpuTBM|CpuF16C|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuXsave|CpuXsaveopt|CpuFSGSBase" }, + { "CPU_BDVER4_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuFMA4|CpuXOP|CpuLWP|CpuBMI|CpuTBM|CpuF16C|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuXsave|CpuXsaveopt|CpuFSGSBase|CpuAVX2|CpuMovbe|CpuBMI2|CpuRdRnd|CpuMWAITX" }, + { "CPU_ZNVER1_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuFISTTP|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM|CpuFMA|CpuBMI|CpuF16C|CpuCX16|CpuClflush|CpuSSSE3|CpuSVME|CpuSSE4_1|CpuSSE4_2|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuXsave|CpuXsaveopt|CpuFSGSBase|CpuAVX2|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" }, { "CPU_BTVER1_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSYSCALL|CpuRdtscp|Cpu387|Cpu687|CpuNop|CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4a|CpuABM|CpuLM|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME|CpuLZCNT" }, { "CPU_BTVER2_FLAGS", @@ -127,7 +130,7 @@ static initializer cpu_flag_init[] = { "CPU_SSE4_2_FLAGS", "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" }, { "CPU_ANY_SSE_FLAGS", - "CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuAVX|CpuAVX2" }, + "CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, { "CPU_VMX_FLAGS", "CpuVMX" }, { "CPU_SMX_FLAGS", @@ -194,18 +197,64 @@ static initializer cpu_flag_init[] = "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX" }, { "CPU_AVX2_FLAGS", "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2" }, + { "CPU_AVX512F_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F" }, + { "CPU_AVX512CD_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD" }, + { "CPU_AVX512ER_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512ER" }, + { "CPU_AVX512PF_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512PF" }, { "CPU_ANY_AVX_FLAGS", - "CpuAVX|CpuAVX2" }, + "CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF" }, { "CPU_L1OM_FLAGS", "unknown" }, { "CPU_K1OM_FLAGS", "unknown" }, + { "CPU_IAMCU_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586" }, + { "CPU_IAMCU_COMPAT_FLAGS", + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuNo64|CpuNop" }, { "CPU_ADX_FLAGS", "CpuADX" }, { "CPU_RDSEED_FLAGS", "CpuRdSeed" }, { "CPU_PRFCHW_FLAGS", "CpuPRFCHW" }, + { "CPU_SMAP_FLAGS", + "CpuSMAP" }, + { "CPU_MPX_FLAGS", + "CpuMPX" }, + { "CPU_SHA_FLAGS", + "CpuSHA" }, + { "CPU_CLFLUSHOPT_FLAGS", + "CpuClflushOpt" }, + { "CPU_XSAVES_FLAGS", + "CpuXSAVES" }, + { "CPU_XSAVEC_FLAGS", + "CpuXSAVEC" }, + { "CPU_PREFETCHWT1_FLAGS", + "CpuPREFETCHWT1" }, + { "CPU_SE1_FLAGS", + "CpuSE1" }, + { "CPU_AVX512DQ_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512DQ" }, + { "CPU_AVX512BW_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512BW" }, + { "CPU_AVX512VL_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VL" }, + { "CPU_CLWB_FLAGS", + "CpuCLWB" }, + { "CPU_PCOMMIT_FLAGS", + "CpuPCOMMIT" }, + { "CPU_AVX512IFMA_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512IFMA" }, + { "CPU_AVX512VBMI_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VBMI" }, + { "CPU_CLZERO_FLAGS", + "CpuCLZERO" }, + { "CPU_MWAITX_FLAGS", + "CpuMWAITX" }, }; static initializer operand_type_init[] = @@ -274,6 +323,10 @@ static initializer operand_type_init[] = "RegXMM" }, { "OPERAND_TYPE_REGYMM", "RegYMM" }, + { "OPERAND_TYPE_REGZMM", + "RegZMM" }, + { "OPERAND_TYPE_REGMASK", + "RegMask" }, { "OPERAND_TYPE_ESSEG", "EsSeg" }, { "OPERAND_TYPE_ACC32", @@ -306,6 +359,10 @@ static initializer operand_type_init[] = "Imm32|Imm32S|Imm64|Disp32|Disp64" }, { "OPERAND_TYPE_VEC_IMM4", "Vec_Imm4" }, + { "OPERAND_TYPE_REGBND", + "RegBND" }, + { "OPERAND_TYPE_VEC_DISP8", + "Vec_Disp8" }, }; typedef struct bitfield @@ -342,8 +399,16 @@ static bitfield cpu_flags[] = BITFIELD (CpuSSE4_2), BITFIELD (CpuAVX), BITFIELD (CpuAVX2), + BITFIELD (CpuAVX512F), + BITFIELD (CpuAVX512CD), + BITFIELD (CpuAVX512ER), + BITFIELD (CpuAVX512PF), + BITFIELD (CpuAVX512VL), + BITFIELD (CpuAVX512DQ), + BITFIELD (CpuAVX512BW), BITFIELD (CpuL1OM), BITFIELD (CpuK1OM), + BITFIELD (CpuIAMCU), BITFIELD (CpuSSE4a), BITFIELD (Cpu3dnow), BITFIELD (Cpu3dnowA), @@ -379,8 +444,25 @@ static bitfield cpu_flags[] = BITFIELD (CpuRDSEED), BITFIELD (CpuADX), BITFIELD (CpuPRFCHW), + BITFIELD (CpuSMAP), + BITFIELD (CpuSHA), + BITFIELD (CpuVREX), + BITFIELD (CpuClflushOpt), + BITFIELD (CpuXSAVES), + BITFIELD (CpuXSAVEC), + BITFIELD (CpuPREFETCHWT1), + BITFIELD (CpuSE1), + BITFIELD (CpuCLWB), + BITFIELD (CpuPCOMMIT), BITFIELD (Cpu64), BITFIELD (CpuNo64), + BITFIELD (CpuMPX), + BITFIELD (CpuAVX512IFMA), + BITFIELD (CpuAVX512VBMI), + BITFIELD (CpuMWAITX), + BITFIELD (CpuCLZERO), + BITFIELD (CpuAMD64), + BITFIELD (CpuIntel64), #ifdef CpuUnused BITFIELD (CpuUnused), #endif @@ -414,6 +496,7 @@ static bitfield opcode_modifiers[] = BITFIELD (No_ldSuf), BITFIELD (FWait), BITFIELD (IsString), + BITFIELD (BNDPrefixOk), BITFIELD (IsLockable), BITFIELD (RegKludge), BITFIELD (FirstXmm0), @@ -437,6 +520,14 @@ static bitfield opcode_modifiers[] = BITFIELD (VecSIB), BITFIELD (SSE2AVX), BITFIELD (NoAVX), + BITFIELD (EVex), + BITFIELD (Masking), + BITFIELD (VecESize), + BITFIELD (Broadcast), + BITFIELD (StaticRounding), + BITFIELD (SAE), + BITFIELD (Disp8MemShift), + BITFIELD (NoDefMask), BITFIELD (OldGcc), BITFIELD (ATTMnemonic), BITFIELD (ATTSyntax), @@ -453,6 +544,8 @@ static bitfield operand_types[] = BITFIELD (RegMMX), BITFIELD (RegXMM), BITFIELD (RegYMM), + BITFIELD (RegZMM), + BITFIELD (RegMask), BITFIELD (Imm1), BITFIELD (Imm8), BITFIELD (Imm8S), @@ -487,9 +580,12 @@ static bitfield operand_types[] = BITFIELD (Tbyte), BITFIELD (Xmmword), BITFIELD (Ymmword), + BITFIELD (Zmmword), BITFIELD (Unspecified), BITFIELD (Anysize), BITFIELD (Vec_Imm4), + BITFIELD (RegBND), + BITFIELD (Vec_Disp8), #ifdef OTUnused BITFIELD (OTUnused), #endif @@ -521,8 +617,7 @@ static void process_copyright (FILE *fp) { fprintf (fp, "/* This file is automatically generated by i386-gen. Do not edit! */\n\ -/* Copyright 2007, 2008, 2009, 2010, 2011, 2012, 2013\n\ - Free Software Foundation, Inc.\n\ +/* Copyright (C) 2007-2015 Free Software Foundation, Inc.\n\ \n\ This file is part of the GNU opcodes library.\n\ \n\ @@ -658,7 +753,10 @@ output_cpu_flags (FILE *table, bitfield *flags, unsigned int size, for (i = 0; i < size - 1; i++) { - fprintf (table, "%d, ", flags[i].value); + if (((i + 1) % 20) != 0) + fprintf (table, "%d, ", flags[i].value); + else + fprintf (table, "%d,", flags[i].value); if (((i + 1) % 20) == 0) { /* We need \\ for macro. */ @@ -746,7 +844,10 @@ output_opcode_modifier (FILE *table, bitfield *modifier, unsigned int size) for (i = 0; i < size - 1; i++) { - fprintf (table, "%d, ", modifier[i].value); + if (((i + 1) % 20) != 0) + fprintf (table, "%d, ", modifier[i].value); + else + fprintf (table, "%d,", modifier[i].value); if (((i + 1) % 20) == 0) fprintf (table, "\n "); } @@ -787,12 +888,15 @@ output_operand_type (FILE *table, bitfield *types, unsigned int size, for (i = 0; i < size - 1; i++) { - fprintf (table, "%d, ", types[i].value); + if (((i + 1) % 20) != 0) + fprintf (table, "%d, ", types[i].value); + else + fprintf (table, "%d,", types[i].value); if (((i + 1) % 20) == 0) { /* We need \\ for macro. */ if (macro) - fprintf (table, "\\\n%s", indent); + fprintf (table, " \\\n%s", indent); else fprintf (table, "\n%s", indent); }