X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fi386-opc.h;h=a8f63330a7750850a334470f63323e61325a44db;hb=ddb9f679fa9f54633442c46574b8e5b0ca45a786;hp=1a791e4d2a4220a26c3c6f33006529555ba4a4a4;hpb=6c30d220f19d7f4fe197fa5f62a472b2e5e84d7c;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 1a791e4d2a..a8f63330a7 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -1,6 +1,5 @@ /* Declarations for Intel 80386 opcode table - Copyright 2007, 2008, 2009, 2010 - Free Software Foundation, Inc. + Copyright (C) 2007-2014 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -94,8 +93,25 @@ enum CpuAVX, /* AVX2 support required */ CpuAVX2, + /* Intel AVX-512 Foundation Instructions support required */ + CpuAVX512F, + /* Intel AVX-512 Conflict Detection Instructions support required */ + CpuAVX512CD, + /* Intel AVX-512 Exponential and Reciprocal Instructions support + required */ + CpuAVX512ER, + /* Intel AVX-512 Prefetch Instructions support required */ + CpuAVX512PF, + /* Intel AVX-512 VL Instructions support required. */ + CpuAVX512VL, + /* Intel AVX-512 DQ Instructions support required. */ + CpuAVX512DQ, + /* Intel AVX-512 BW Instructions support required. */ + CpuAVX512BW, /* Intel L1OM support required */ CpuL1OM, + /* Intel K1OM support required */ + CpuK1OM, /* Xsave/xrstor New Instructions support required */ CpuXsave, /* Xsaveopt New Instructions support required */ @@ -118,6 +134,8 @@ enum CpuTBM, /* MOVBE Instruction support required */ CpuMovbe, + /* CMPXCHG16B instruction support required. */ + CpuCX16, /* EPT Instructions required */ CpuEPT, /* RDTSCP Instruction support required */ @@ -132,10 +150,48 @@ enum CpuBMI2, /* LZCNT support required */ CpuLZCNT, + /* HLE support required */ + CpuHLE, + /* RTM support required */ + CpuRTM, /* INVPCID Instructions required */ CpuINVPCID, + /* VMFUNC Instruction required */ + CpuVMFUNC, + /* Intel MPX Instructions required */ + CpuMPX, /* 64bit support available, used by -march= in assembler. */ CpuLM, + /* RDRSEED instruction required. */ + CpuRDSEED, + /* Multi-presisionn add-carry instructions are required. */ + CpuADX, + /* Supports prefetchw and prefetch instructions. */ + CpuPRFCHW, + /* SMAP instructions required. */ + CpuSMAP, + /* SHA instructions required. */ + CpuSHA, + /* VREX support required */ + CpuVREX, + /* CLFLUSHOPT instruction required */ + CpuClflushOpt, + /* XSAVES/XRSTORS instruction required */ + CpuXSAVES, + /* XSAVEC instruction required */ + CpuXSAVEC, + /* PREFETCHWT1 instruction required */ + CpuPREFETCHWT1, + /* SE1 instruction required */ + CpuSE1, + /* CLWB instruction required */ + CpuCLWB, + /* PCOMMIT instruction required */ + CpuPCOMMIT, + /* Intel AVX-512 IFMA Instructions support required. */ + CpuAVX512IFMA, + /* Intel AVX-512 VBMI Instructions support required. */ + CpuAVX512VBMI, /* 64bit support required */ Cpu64, /* Not supported in the 64bit mode */ @@ -190,7 +246,15 @@ typedef union i386_cpu_flags unsigned int cpusse4_2:1; unsigned int cpuavx:1; unsigned int cpuavx2:1; + unsigned int cpuavx512f:1; + unsigned int cpuavx512cd:1; + unsigned int cpuavx512er:1; + unsigned int cpuavx512pf:1; + unsigned int cpuavx512vl:1; + unsigned int cpuavx512dq:1; + unsigned int cpuavx512bw:1; unsigned int cpul1om:1; + unsigned int cpuk1om:1; unsigned int cpuxsave:1; unsigned int cpuxsaveopt:1; unsigned int cpuaes:1; @@ -202,6 +266,7 @@ typedef union i386_cpu_flags unsigned int cpubmi:1; unsigned int cputbm:1; unsigned int cpumovbe:1; + unsigned int cpucx16:1; unsigned int cpuept:1; unsigned int cpurdtscp:1; unsigned int cpufsgsbase:1; @@ -209,8 +274,27 @@ typedef union i386_cpu_flags unsigned int cpuf16c:1; unsigned int cpubmi2:1; unsigned int cpulzcnt:1; + unsigned int cpuhle:1; + unsigned int cpurtm:1; unsigned int cpuinvpcid:1; + unsigned int cpuvmfunc:1; + unsigned int cpumpx:1; unsigned int cpulm:1; + unsigned int cpurdseed:1; + unsigned int cpuadx:1; + unsigned int cpuprfchw:1; + unsigned int cpusmap:1; + unsigned int cpusha:1; + unsigned int cpuvrex:1; + unsigned int cpuclflushopt:1; + unsigned int cpuxsaves:1; + unsigned int cpuxsavec:1; + unsigned int cpuprefetchwt1:1; + unsigned int cpuse1:1; + unsigned int cpuclwb:1; + unsigned int cpupcommit:1; + unsigned int cpuavx512ifma:1; + unsigned int cpuavx512vbmi:1; unsigned int cpu64:1; unsigned int cpuno64:1; #ifdef CpuUnused @@ -278,6 +362,8 @@ enum FWait, /* quick test for string instructions */ IsString, + /* quick test if branch instruction is MPX supported */ + BNDPrefixOk, /* quick test for lockable instructions */ IsLockable, /* fake an extra reg operand for clr, imul and special register @@ -287,6 +373,18 @@ enum FirstXmm0, /* An implicit xmm0 as the first operand */ Implicit1stXmm0, + /* The HLE prefix is OK: + 1. With a LOCK prefix. + 2. With or without a LOCK prefix. + 3. With a RELEASE (0xf3) prefix. + */ +#define HLEPrefixNone 0 +#define HLEPrefixLock 1 +#define HLEPrefixAny 2 +#define HLEPrefixRelease 3 + HLEPrefixOk, + /* An instruction on which a "rep" prefix is acceptable. */ + RepPrefixOk, /* Convert to DWORD */ ToDword, /* Convert to QWORD */ @@ -316,7 +414,7 @@ enum 0: VEX.vvvv must be 1111b. 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where the content of source registers will be preserved. - VEX.DDS. The second register operand is encoded in VEX.vvvv + VEX.DDS. The second register operand is encoded in VEX.vvvv where the content of first source register will be overwritten by the result. VEX.NDD2. The second destination register operand is encoded in @@ -368,14 +466,69 @@ enum /* Instruction with vector SIB byte: 1: 128bit vector register. 2: 256bit vector register. + 3: 512bit vector register. */ #define VecSIB128 1 #define VecSIB256 2 +#define VecSIB512 3 VecSIB, /* SSE to AVX support required */ SSE2AVX, /* No AVX equivalent */ NoAVX, + + /* insn has EVEX prefix: + 1: 512bit EVEX prefix. + 2: 128bit EVEX prefix. + 3: 256bit EVEX prefix. + 4: Length-ignored (LIG) EVEX prefix. + */ +#define EVEX512 1 +#define EVEX128 2 +#define EVEX256 3 +#define EVEXLIG 4 + EVex, + + /* AVX512 masking support: + 1: Zeroing-masking. + 2: Merging-masking. + 3: Both zeroing and merging masking. + */ +#define ZEROING_MASKING 1 +#define MERGING_MASKING 2 +#define BOTH_MASKING 3 + Masking, + + /* Input element size of vector insn: + 0: 32bit. + 1: 64bit. + */ + VecESize, + + /* Broadcast factor. + 0: No broadcast. + 1: 1to16 broadcast. + 2: 1to8 broadcast. + */ +#define NO_BROADCAST 0 +#define BROADCAST_1TO16 1 +#define BROADCAST_1TO8 2 +#define BROADCAST_1TO4 3 +#define BROADCAST_1TO2 4 + Broadcast, + + /* Static rounding control is supported. */ + StaticRounding, + + /* Supress All Exceptions is supported. */ + SAE, + + /* Copressed Disp8*N attribute. */ + Disp8MemShift, + + /* Default mask isn't allowed. */ + NoDefMask, + /* Compatible with old (<= 2.8.1) versions of gcc */ OldGcc, /* AT&T mnemonic. */ @@ -416,10 +569,13 @@ typedef struct i386_opcode_modifier unsigned int no_ldsuf:1; unsigned int fwait:1; unsigned int isstring:1; + unsigned int bndprefixok:1; unsigned int islockable:1; unsigned int regkludge:1; unsigned int firstxmm0:1; unsigned int implicit1stxmm0:1; + unsigned int hleprefixok:2; + unsigned int repprefixok:1; unsigned int todword:1; unsigned int toqword:1; unsigned int addrprefixop0:1; @@ -437,6 +593,14 @@ typedef struct i386_opcode_modifier unsigned int vecsib:2; unsigned int sse2avx:1; unsigned int noavx:1; + unsigned int evex:3; + unsigned int masking:2; + unsigned int vecesize:1; + unsigned int broadcast:3; + unsigned int staticrounding:1; + unsigned int sae:1; + unsigned int disp8memshift:3; + unsigned int nodefmask:1; unsigned int oldgcc:1; unsigned int attmnemonic:1; unsigned int attsyntax:1; @@ -463,6 +627,10 @@ enum RegXMM, /* AVX registers */ RegYMM, + /* AVX512 registers */ + RegZMM, + /* Vector Mask registers */ + RegMask, /* Control register */ Control, /* Debug register */ @@ -542,6 +710,8 @@ enum Xmmword, /* YMMWORD memory. */ Ymmword, + /* ZMMWORD memory. */ + Zmmword, /* Unspecified memory size. */ Unspecified, /* Any memory size. */ @@ -550,6 +720,12 @@ enum /* Vector 4 bit immediate. */ Vec_Imm4, + /* Bound register. */ + RegBND, + + /* Vector 8bit displacement */ + Vec_Disp8, + /* The last bitfield in i386_operand_type. */ OTMax }; @@ -575,6 +751,8 @@ typedef union i386_operand_type unsigned int regmmx:1; unsigned int regxmm:1; unsigned int regymm:1; + unsigned int regzmm:1; + unsigned int regmask:1; unsigned int control:1; unsigned int debug:1; unsigned int test:1; @@ -609,9 +787,12 @@ typedef union i386_operand_type unsigned int tbyte:1; unsigned int xmmword:1; unsigned int ymmword:1; + unsigned int zmmword:1; unsigned int unspecified:1; unsigned int anysize:1; unsigned int vec_imm4:1; + unsigned int regbnd:1; + unsigned int vec_disp8:1; #ifdef OTUnused unsigned int unused:(OTNumOfBits - OTUnused); #endif @@ -639,7 +820,7 @@ typedef struct insn_template /* extension_opcode is the 3 bit extension for group insns. This field is also used to store the 8-bit opcode suffix for the AMD 3DNow! instructions. - If this template has no extension opcode (the usual case) use None + If this template has no extension opcode (the usual case) use None Instructions */ unsigned int extension_opcode; #define None 0xffff /* If no extension_opcode is possible. */ @@ -673,6 +854,7 @@ typedef struct unsigned char reg_flags; #define RegRex 0x1 /* Extended register. */ #define RegRex64 0x2 /* Extended 8 bit register. */ +#define RegVRex 0x4 /* Extended vector register. */ unsigned char reg_num; #define RegRip ((unsigned char ) ~0) #define RegEip (RegRip - 1)