X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fm32r-asm.c;h=4a2106c2fbfdd54810c926cca4bf64d9425364af;hb=68e52bc7ecfbfdc8d5f85716a8ac7668e211f360;hp=0aa62ce1a155cae54df6b4bd970086241812c269;hpb=d0352a18a504a4e7b761f6b3264cf11347d8d056;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index 0aa62ce1a1..4a2106c2fb 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -1,32 +1,33 @@ +/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. + Copyright (C) 1996-2020 Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of libopcodes. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ #include "sysdep.h" -#include #include #include "ansidecl.h" #include "bfd.h" @@ -34,27 +35,30 @@ along with this program; if not, write to the Free Software Foundation, Inc., #include "m32r-desc.h" #include "m32r-opc.h" #include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); -/* -- assembler routines inserted here */ +/* -- assembler routines inserted here. */ /* -- asm.c */ +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); /* Handle '#' prefixes (i.e. skip over them). */ static const char * -parse_hash (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) { if (**strp == '#') ++*strp; @@ -64,11 +68,10 @@ parse_hash (cd, strp, opindex, valuep) /* Handle shigh(), high(). */ static const char * -parse_hi16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -81,13 +84,16 @@ parse_hi16 (cd, strp, opindex, valuep) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value >>= 16; + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value >>= 16; + value &= 0xffff; + } *valuep = value; return errmsg; } @@ -95,13 +101,17 @@ parse_hi16 (cd, strp, opindex, valuep) { *strp += 6; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = (value >> 16) + (value & 0x8000 ? 1 : 0); + { + value += 0x8000; + value >>= 16; + value &= 0xffff; + } *valuep = value; return errmsg; } @@ -114,11 +124,10 @@ parse_hi16 (cd, strp, opindex, valuep) handles the case where low() isn't present. */ static const char * -parse_slo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_slo16 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -131,13 +140,13 @@ parse_slo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; + value = ((value & 0xffff) ^ 0x8000) - 0x8000; *valuep = value; return errmsg; } @@ -146,9 +155,9 @@ parse_slo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, - NULL, &value); + NULL, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; *valuep = value; return errmsg; @@ -162,11 +171,10 @@ parse_slo16 (cd, strp, opindex, valuep) handles the case where low() isn't present. */ static const char * -parse_ulo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -179,9 +187,9 @@ parse_ulo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -195,6 +203,9 @@ parse_ulo16 (cd, strp, opindex, valuep) /* -- */ +const char * m32r_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + /* Main entry point for operand parsing. This function is basically just a big switch statement. Earlier versions @@ -206,19 +217,17 @@ parse_ulo16 (cd, strp, opindex, valuep) This function could be moved into `parse_insn_normal', but keeping it separate makes clear the interface between `parse_insn_normal' and each of - the handlers. -*/ + the handlers. */ const char * -m32r_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +m32r_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ - long junk; + long junk ATTRIBUTE_UNUSED; switch (opindex) { @@ -236,21 +245,21 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields) break; case M32R_OPERAND_DISP16 : { - bfd_vma value; + bfd_vma value = 0; errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP16, 0, NULL, & value); fields->f_disp16 = value; } break; case M32R_OPERAND_DISP24 : { - bfd_vma value; + bfd_vma value = 0; errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP24, 0, NULL, & value); fields->f_disp24 = value; } break; case M32R_OPERAND_DISP8 : { - bfd_vma value; + bfd_vma value = 0; errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP8, 0, NULL, & value); fields->f_disp8 = value; } @@ -259,25 +268,25 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields) errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1); break; case M32R_OPERAND_HASH : - errmsg = parse_hash (cd, strp, M32R_OPERAND_HASH, &junk); + errmsg = parse_hash (cd, strp, M32R_OPERAND_HASH, (long *) (& junk)); break; case M32R_OPERAND_HI16 : - errmsg = parse_hi16 (cd, strp, M32R_OPERAND_HI16, &fields->f_hi16); + errmsg = parse_hi16 (cd, strp, M32R_OPERAND_HI16, (unsigned long *) (& fields->f_hi16)); break; case M32R_OPERAND_IMM1 : - errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_IMM1, &fields->f_imm1); + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_IMM1, (unsigned long *) (& fields->f_imm1)); break; case M32R_OPERAND_SCR : errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_cr_names, & fields->f_r2); break; case M32R_OPERAND_SIMM16 : - errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM16, &fields->f_simm16); + errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM16, (long *) (& fields->f_simm16)); break; case M32R_OPERAND_SIMM8 : - errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM8, &fields->f_simm8); + errmsg = cgen_parse_signed_integer (cd, strp, M32R_OPERAND_SIMM8, (long *) (& fields->f_simm8)); break; case M32R_OPERAND_SLO16 : - errmsg = parse_slo16 (cd, strp, M32R_OPERAND_SLO16, &fields->f_simm16); + errmsg = parse_slo16 (cd, strp, M32R_OPERAND_SLO16, (long *) (& fields->f_simm16)); break; case M32R_OPERAND_SR : errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2); @@ -289,47 +298,179 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields) errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r2); break; case M32R_OPERAND_UIMM16 : - errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM16, &fields->f_uimm16); + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM16, (unsigned long *) (& fields->f_uimm16)); break; case M32R_OPERAND_UIMM24 : { - bfd_vma value; + bfd_vma value = 0; errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_UIMM24, 0, NULL, & value); fields->f_uimm24 = value; } break; + case M32R_OPERAND_UIMM3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM3, (unsigned long *) (& fields->f_uimm3)); + break; case M32R_OPERAND_UIMM4 : - errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4); + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, (unsigned long *) (& fields->f_uimm4)); break; case M32R_OPERAND_UIMM5 : - errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5); + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, (unsigned long *) (& fields->f_uimm5)); + break; + case M32R_OPERAND_UIMM8 : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM8, (unsigned long *) (& fields->f_uimm8)); break; case M32R_OPERAND_ULO16 : - errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, &fields->f_uimm16); + errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, (unsigned long *) (& fields->f_uimm16)); break; default : /* xgettext:c-format */ - fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + opcodes_error_handler + (_("internal error: unrecognized field %d while parsing"), + opindex); abort (); } return errmsg; } -cgen_parse_fn * const m32r_cgen_parse_handlers[] = +cgen_parse_fn * const m32r_cgen_parse_handlers[] = { parse_insn_normal, }; void -m32r_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +m32r_cgen_init_asm (CGEN_CPU_DESC cd) { m32r_cgen_init_opcode_table (cd); m32r_cgen_init_ibld_table (cd); cd->parse_handlers = & m32r_cgen_parse_handlers[0]; cd->parse_operand = m32r_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by m32r_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +m32r_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } } @@ -344,22 +485,20 @@ m32r_cgen_init_asm (cd) but that can be handled there. Not handling backtracking here may get expensive in the case of the m68k. Deal with later. - Returns NULL for success, an error message for failure. -*/ + Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const char *str = *strp; const char *errmsg; const char *p; - const unsigned char * syn; + const CGEN_SYNTAX_CHAR_TYPE * syn; #ifdef CGEN_MNEMONIC_OPERANDS /* FIXME: wip */ int past_opcode_p; @@ -370,14 +509,14 @@ parse_insn_normal (cd, insn, strp, fields) GAS's input scrubber will ensure mnemonics are lowercase, but we may not be called from GAS. */ p = CGEN_INSN_MNEMONIC (insn); - while (*p && tolower (*p) == tolower (*str)) + while (*p && TOLOWER (*p) == TOLOWER (*str)) ++p, ++str; if (* p) return _("unrecognized instruction"); #ifndef CGEN_MNEMONIC_OPERANDS - if (* str && !isspace (* str)) + if (* str && ! ISSPACE (* str)) return _("unrecognized instruction"); #endif @@ -406,28 +545,43 @@ parse_insn_normal (cd, insn, strp, fields) first char after the mnemonic part is a space. */ /* FIXME: We also take inappropriate advantage of the fact that GAS's input scrubber will remove extraneous blanks. */ - if (*str == CGEN_SYNTAX_CHAR (* syn)) + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) { #ifdef CGEN_MNEMONIC_OPERANDS - if (* syn == ' ') + if (CGEN_SYNTAX_CHAR(* syn) == ' ') past_opcode_p = 1; #endif ++ syn; ++ str; } - else + else if (*str) { /* Syntax char didn't match. Can't be this insn. */ - /* FIXME: would like to return something like - "expected char `c'" */ - return _("syntax error"); + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; } continue; } +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif /* We have an operand of some sort. */ - errmsg = m32r_cgen_parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), - &str, fields); + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); if (errmsg) return errmsg; @@ -436,13 +590,13 @@ parse_insn_normal (cd, insn, strp, fields) } /* If we're at the end of the syntax string, we're done. */ - if (* syn == '\0') + if (* syn == 0) { /* FIXME: For the moment we assume a valid `str' can only contain blanks now. IE: We needn't try again with a longer version of the insn and it is assumed that longer versions of insns appear before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (isspace (* str)) + while (ISSPACE (* str)) ++ str; if (* str != '\0') @@ -477,19 +631,20 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +m32r_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; - const char *tmp_errmsg; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; /* Skip leading white space. */ - while (isspace (* str)) + while (ISSPACE (* str)) ++ str; /* The instructions are stored in hashed lists. @@ -497,94 +652,87 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) ilist = CGEN_ASM_LOOKUP_INSN (cd, str); /* Keep looking until we find a match. */ - start = str; for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) { const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; -#ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* not usually needed as unsupported opcodes shouldn't be in the hash lists */ +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ /* Is this insn supported by the selected cpu? */ if (! m32r_cgen_insn_supported (cd, insn)) continue; #endif - - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + /* Allow parse/insert handlers to obtain length of insn. */ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - if (!(tmp_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields))) - { - /* ??? 0 is passed for `pc' */ - if (CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0) - != NULL) - continue; - /* It is up to the caller to actually output the insn and any - queued relocs. */ - return insn; - } + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; - /* Try the next entry. */ + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; } { static char errbuf[150]; - + const char *tmp_errmsg; #ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS - /* if verbose error messages, use errmsg from CGEN_PARSE_FN */ - if (strlen (start) > 50) - /* xgettext:c-format */ - sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); - else - /* xgettext:c-format */ - sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#define be_verbose 1 #else - if (strlen (start) > 50) - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s...'"), start); - else - /* xgettext:c-format */ - sprintf (errbuf, _("bad instruction `%.50s'"), start); +#define be_verbose 0 #endif - + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + *errmsg = errbuf; return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -m32r_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! m32r_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */