X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fm32r-ibld.c;h=3f24756104e2b3c95918f3ed6b2a26e1be8ff0d4;hb=f69656d00fe3154519ea21668d964bf8cc50c01b;hp=2e108642c2b3e4d221cd3e09c9bb538ec60ae55f;hpb=6f3b91a62110eaea42cd7df18d6f9293f5d60fa2;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c index 2e108642c2..3f24756104 100644 --- a/opcodes/m32r-ibld.c +++ b/opcodes/m32r-ibld.c @@ -1,10 +1,10 @@ +/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ /* Instruction building/extraction support for m32r. -*- C -*- THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. - the resultant file is machine generated, cgen-ibld.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, - 2008 Free Software Foundation, Inc. + Copyright (C) 1996-2019 Free Software Foundation, Inc. This file is part of libopcodes. @@ -33,6 +33,7 @@ #include "symcat.h" #include "m32r-desc.h" #include "m32r-opc.h" +#include "cgen/basic-modes.h" #include "opintl.h" #include "safe-ctype.h" @@ -137,7 +138,7 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; - if (word_length > 32) + if (word_length > 8 * sizeof (CGEN_INSN_INT)) abort (); /* For architectures with insns smaller than the base-insn-bitsize, @@ -154,7 +155,7 @@ insert_normal (CGEN_CPU_DESC cd, { long minval = - (1L << (length - 1)); unsigned long maxval = mask; - + if ((value > 0 && (unsigned long) value > maxval) || value < minval) { @@ -192,7 +193,7 @@ insert_normal (CGEN_CPU_DESC cd, { long minval = - (1L << (length - 1)); long maxval = (1L << (length - 1)) - 1; - + if (value < minval || value > maxval) { sprintf @@ -207,12 +208,19 @@ insert_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P { - int shift; + int shift_within_word, shift_to_word, shift; + /* How to shift the value to BIT0 of the word. */ + shift_to_word = total_length - (word_offset + word_length); + + /* How to shift the value to the field within the word. */ if (CGEN_INSN_LSB0_P) - shift = (word_offset + start + 1) - length; + shift_within_word = start + 1 - length; else - shift = total_length - (word_offset + start + length); + shift_within_word = word_length - start - length; + + /* The total SHIFT, then mask in the value. */ + shift = shift_to_word + shift_within_word; *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); } @@ -441,7 +449,7 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } - if (word_length > 32) + if (word_length > 8 * sizeof (CGEN_INSN_INT)) abort (); /* For architectures with insns smaller than the insn-base-bitsize, @@ -468,7 +476,7 @@ extract_normal (CGEN_CPU_DESC cd, { unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; - if (word_length > 32) + if (word_length > 8 * sizeof (CGEN_INSN_INT)) abort (); if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) @@ -580,21 +588,21 @@ m32r_cgen_insert_operand (CGEN_CPU_DESC cd, case M32R_OPERAND_DISP16 : { long value = fields->f_disp16; - value = ((int) (((value) - (pc))) >> (2)); + value = ((SI) (((value) - (pc))) >> (2)); errmsg = insert_normal (cd, value, 0|(1<f_disp24; - value = ((int) (((value) - (pc))) >> (2)); + value = ((SI) (((value) - (pc))) >> (2)); errmsg = insert_normal (cd, value, 0|(1<f_disp8; - value = ((int) (((value) - (((pc) & (-4))))) >> (2)); + value = ((SI) (((value) - (((pc) & (-4))))) >> (2)); errmsg = insert_normal (cd, value, 0|(1<