X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fm32r-opc.c;h=9e76c64db72e32a8060cbd2b37eaf3ddb8d63e87;hb=470c0b1c9a1d69e3c4f9281600399b1dadd40614;hp=7669eb6187c41d6127336cb899bca9399fc17a71;hpb=fb53f5a81a23dd5fc2eac009274e90b9753e1f22;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index 7669eb6187..9e76c64db7 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -1,24 +1,25 @@ +/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ /* Instruction opcode table for m32r. THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2005 Free Software Foundation, Inc. +Copyright (C) 1996-2019 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -63,11 +64,7 @@ static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define F(f) & m32r_cgen_ifld_table[M32R_##f] -#else -#define F(f) & m32r_cgen_ifld_table[M32R_/**/f] -#endif static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { 0, 0, 0x0, { { 0 } } }; @@ -210,16 +207,8 @@ static const CGEN_IFMT ifmt_btst ATTRIBUTE_UNUSED = { #undef F -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_INSN_##a) -#else -#define A(a) (1 << CGEN_INSN_/**/a) -#endif -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define OPERAND(op) M32R_OPERAND_##op -#else -#define OPERAND(op) M32R_OPERAND_/**/op -#endif #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) @@ -1128,11 +1117,7 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] = /* Formats for ALIAS macro-insns. */ -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define F(f) & m32r_cgen_ifld_table[M32R_##f] -#else -#define F(f) & m32r_cgen_ifld_table[M32R_/**/f] -#endif static const CGEN_IFMT ifmt_bc8r ATTRIBUTE_UNUSED = { 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } } }; @@ -1281,16 +1266,8 @@ static const CGEN_IFMT ifmt_push ATTRIBUTE_UNUSED = { /* Each non-simple macro entry points to an array of expansion possibilities. */ -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_INSN_##a) -#else -#define A(a) (1 << CGEN_INSN_/**/a) -#endif -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define OPERAND(op) M32R_OPERAND_##op -#else -#define OPERAND(op) M32R_OPERAND_/**/op -#endif #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) @@ -1719,15 +1696,13 @@ static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] = Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ static int -asm_hash_insn_p (insn) - const CGEN_INSN *insn ATTRIBUTE_UNUSED; +asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED) { return CGEN_ASM_HASH_P (insn); } static int -dis_hash_insn_p (insn) - const CGEN_INSN *insn; +dis_hash_insn_p (const CGEN_INSN *insn) { /* If building the hash table and the NO-DIS attribute is present, ignore. */ @@ -1759,8 +1734,7 @@ dis_hash_insn_p (insn) Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ static unsigned int -asm_hash_insn (mnem) - const char * mnem; +asm_hash_insn (const char *mnem) { return CGEN_ASM_HASH (mnem); } @@ -1769,9 +1743,8 @@ asm_hash_insn (mnem) VALUE is the first base_insn_bitsize bits as an int in host order. */ static unsigned int -dis_hash_insn (buf, value) - const char * buf ATTRIBUTE_UNUSED; - CGEN_INSN_INT value ATTRIBUTE_UNUSED; +dis_hash_insn (const char *buf ATTRIBUTE_UNUSED, + CGEN_INSN_INT value ATTRIBUTE_UNUSED) { return CGEN_DIS_HASH (buf, value); } @@ -1797,7 +1770,10 @@ m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd) const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0]; CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); - memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + /* This test has been added to avoid a warning generated + if memset is called with a third argument of value zero. */ + if (num_macros >= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { insns[i].base = &ib[i];