X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fmcore-opc.h;h=1160e07269189d7184491319efdcf00aa2c00b97;hb=6867aac05b9677ff9e0f388d7c10d3bc38fc524b;hp=606ba846efd4619922c2e7ebb5dc8e17726c344b;hpb=252b5132c753830d5fd56823373aed85f2a0db63;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/mcore-opc.h b/opcodes/mcore-opc.h
index 606ba846ef..1160e07269 100644
--- a/opcodes/mcore-opc.h
+++ b/opcodes/mcore-opc.h
@@ -1,20 +1,22 @@
-/* Assembler instructions for Motorolla's Mcore processor
-   Copyright (C) 1999 Free Software Foundation, Inc.
+/* Assembler instructions for Motorola's Mcore processor
+   Copyright (C) 1999-2020 Free Software Foundation, Inc.
 
-   
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This file is part of the GNU opcodes library.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include "ansidecl.h"
 
@@ -24,13 +26,14 @@ typedef enum
   OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
   RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
   O1R1,  OMb,  OMc,  SIa,
+  MULSH, OPSR,
   JC,    JU,   JL,   RSI,  DO21,  OB2
 }
 mcore_opclass;
 
 typedef struct inst
 {
-  char *         name;
+  const char *   name;
   mcore_opclass  opclass;
   unsigned char  transfer;
   unsigned short inst;
@@ -38,7 +41,7 @@ typedef struct inst
 mcore_opcode_info;
 
 #ifdef DEFINE_TABLE
-mcore_opcode_info mcore_table[] =
+const mcore_opcode_info mcore_table[] =
 {
   { "bkpt",	O0,	0,	0x0000 },
   { "sync",	O0,	0,	0x0001 },
@@ -48,6 +51,7 @@ mcore_opcode_info mcore_table[] =
   { "stop",	O0,	0,	0x0004 },
   { "wait",	O0,	0,	0x0005 },
   { "doze",	O0,	0,	0x0006 },
+  { "idly4",    O0,     0,      0x0007 },
   { "trap",	OT,	0,	0x0008 },
 /* SPACE:                       0x000C - 0x000F */
 /* SPACE:                       0x0010 - 0x001F */
@@ -99,6 +103,8 @@ mcore_opcode_info mcore_table[] =
   { "tst",	O2,	0,	0x0E00 },
   { "cmpne",	O2,	0,	0x0F00 },
   { "mfcr",	OC,	0,	0x1000 },
+  { "psrclr",	OPSR,	0,	0x11F0 },
+  { "psrset",	OPSR,	0,	0x11F8 },
   { "mov",	O2,	0,	0x1200 },
   { "bgenr",	O2,	0,	0x1300 },
   { "rsub",	O2,	0,	0x1400 },
@@ -109,6 +115,7 @@ mcore_opcode_info mcore_table[] =
   { "asr",	O2,	0,	0x1A00 },
   { "lsl",	O2,	0,	0x1B00 },
   { "addu",	O2,	0,	0x1C00 },
+  { "add",	O2,	0,	0x1C00 }, /* Official alias.  */
   { "ixh",	O2,	0,	0x1D00 },
   { "or",	O2,	0,	0x1E00 },
   { "andn",	O2,	0,	0x1F00 },
@@ -121,14 +128,14 @@ mcore_opcode_info mcore_table[] =
   { "cmpnei",	OB,	0,	0x2A00 },
   { "bmaski",	OMa,	0,	0x2C00 },
   { "divu",	O1R1,	0,	0x2C10 },
-/* SPACE:                       0x2c20 - 0x2c7f */  
+/* SPACE:                       0x2c20 - 0x2c7f */
   { "bmaski",	OMb,	0,	0x2C80 },
   { "bmaski",	OMc,	0,	0x2D00 },
   { "andi",	OB,	0,	0x2E00 },
   { "bclri",	OB,	0,	0x3000 },
 /* SPACE:                       0x3200 - 0x320f */
   { "divs",	O1R1,	0,	0x3210 },
-/* SPACE:                       0x3220 - 0x326f */  
+/* SPACE:                       0x3220 - 0x326f */
   { "bgeni",	OBRa,	0,	0x3270 },
   { "bgeni",	OBRb,	0,	0x3280 },
   { "bgeni",	OBRc,	0,	0x3300 },
@@ -146,6 +153,8 @@ mcore_opcode_info mcore_table[] =
   { "movi",	I7,	0,	0x6000 },
 #define MCORE_INST_BMASKI_ALT	0x6000
 #define MCORE_INST_BGENI_ALT	0x6000
+  { "mulsh",    MULSH,  0,      0x6800 },
+  { "muls.h",   MULSH,  0,      0x6800 },
 /* SPACE:                       0x6900 - 0x6FFF */
   { "jmpi",	LJ,	1,	0x7000 },
   { "jsri",	LJ,	0,	0x7F00 },
@@ -197,6 +206,5 @@ mcore_opcode_info mcore_table[] =
   { "rori",	RSI,	0,	0x3800 },
   { "rotri",	RSI,    0,	0x3800 },
   { "nop",	O0,     0,	0x1200 },  /* mov r0, r0 */
-  { 0,		0,	0,      0 }
 };
 #endif