X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Friscv-dis.c;h=47f9db02691d3afe1298678fcbdddafe9934499f;hb=456e800a63def18484f69a51f59c2338a5cc4568;hp=cb263505d169390fb8deecb55258be5d6679790f;hpb=2922d21da14b4711872371abacb16e8ab7c70894;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index cb263505d1..47f9db0269 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1,5 +1,5 @@
 /* RISC-V disassembler
-   Copyright 2011-2016 Free Software Foundation, Inc.
+   Copyright (C) 2011-2020 Free Software Foundation, Inc.
 
    Contributed by Andrew Waterman (andrew@sifive.com).
    Based on MIPS target.
@@ -21,14 +21,14 @@
    see <http://www.gnu.org/licenses/>.  */
 
 #include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
 #include "libiberty.h"
 #include "opcode/riscv.h"
 #include "opintl.h"
 #include "elf-bfd.h"
 #include "elf/riscv.h"
 
-#include <stdint.h>
+#include "bfd_stdint.h"
 #include <ctype.h>
 
 struct riscv_private_data
@@ -64,8 +64,8 @@ parse_riscv_dis_option (const char *option)
     }
   else
     {
-      /* Invalid option.  */
-      fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option);
+      /* xgettext:c-format */
+      opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
     }
 }
 
@@ -101,7 +101,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
-      pd->print_addr = pd->hi_addr[base_reg] + offset;
+      pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
       pd->hi_addr[base_reg] = -1;
     }
   else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 	    case 'i':
 	      print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
 	      break;
+	    case 'o':
 	    case 'j':
 	      print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
 	      break;
@@ -225,6 +226,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 
 	case 'b':
 	case 's':
+	  if ((l & MASK_JALR) == MATCH_JALR)
+	    maybe_print_address (pd, rs1, 0);
 	  print (info->stream, "%s", riscv_gpr_names[rs1]);
 	  break;
 
@@ -255,6 +258,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 
 	case 'o':
 	  maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
+	  /* Fall through.  */
 	case 'j':
 	  if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
 	      || (l & MASK_JALR) == MATCH_JALR)
@@ -383,7 +387,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	pd->hi_addr[i] = -1;
 
       for (i = 0; i < info->symtab_size; i++)
-	if (strcmp (bfd_asymbol_name (info->symtab[i]), "_gp") == 0)
+	if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
 	  pd->gp = bfd_asymbol_value (info->symtab[i]);
     }
   else
@@ -391,9 +395,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 
   insnlen = riscv_insn_length (word);
 
+  /* RISC-V instructions are always little-endian.  */
+  info->endian_code = BFD_ENDIAN_LITTLE;
+
   info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
   info->bytes_per_line = 8;
-  info->display_endian = info->endian;
+  /* We don't support constant pools, so this must be code.  */
+  info->display_endian = info->endian_code;
   info->insn_info_valid = 1;
   info->branch_delay_insns = 0;
   info->data_size = 0;
@@ -404,7 +412,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
   op = riscv_hash[OP_HASH_IDX (word)];
   if (op != NULL)
     {
-      int xlen = 0;
+      unsigned xlen = 0;
 
       /* If XLEN is not known, get its value from the ELF class.  */
       if (info->mach == bfd_mach_riscv64)
@@ -426,7 +434,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	  if (no_aliases && (op->pinfo & INSN_ALIAS))
 	    continue;
 	  /* Is this instruction restricted to a certain value of XLEN?  */
-	  if (isdigit (op->subset[0]) && atoi (op->subset) != xlen)
+	  if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
 	    continue;
 
 	  /* It's a match.  */
@@ -442,6 +450,32 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 	      pd->print_addr = -1;
 	    }
 
+	  /* Finish filling out insn_info fields.  */
+	  switch (op->pinfo & INSN_TYPE)
+	    {
+	    case INSN_BRANCH:
+	      info->insn_type = dis_branch;
+	      break;
+	    case INSN_CONDBRANCH:
+	      info->insn_type = dis_condbranch;
+	      break;
+	    case INSN_JSR:
+	      info->insn_type = dis_jsr;
+	      break;
+	    case INSN_DREF:
+	      info->insn_type = dis_dref;
+	      break;
+	    default:
+	      break;
+	    }
+
+	  if (op->pinfo & INSN_DATA_SIZE)
+	    {
+	      int size = ((op->pinfo & INSN_DATA_SIZE)
+			  >> INSN_DATA_SIZE_SHIFT);
+	      info->data_size = 1 << (size - 1);
+	    }
+
 	  return insnlen;
 	}
     }
@@ -488,6 +522,23 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
   return riscv_disassemble_insn (memaddr, insn, info);
 }
 
+/* Prevent use of the fake labels that are generated as part of the DWARF
+   and for relaxable relocations in the assembler.  */
+
+bfd_boolean
+riscv_symbol_is_valid (asymbol * sym,
+                       struct disassemble_info * info ATTRIBUTE_UNUSED)
+{
+  const char * name;
+
+  if (sym == NULL)
+    return FALSE;
+
+  name = bfd_asymbol_name (sym);
+
+  return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
+}
+
 void
 print_riscv_disassembler_options (FILE *stream)
 {
@@ -496,7 +547,7 @@ The following RISC-V-specific disassembler options are supported for use\n\
 with the -M switch (multiple options should be separated by commas):\n"));
 
   fprintf (stream, _("\n\
-  numeric       Print numeric reigster names, rather than ABI names.\n"));
+  numeric       Print numeric register names, rather than ABI names.\n"));
 
   fprintf (stream, _("\n\
   no-aliases    Disassemble only into canonical instructions, rather\n\