X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=opcodes%2Fs390-opc.c;h=a1e761cdf9a09363055e36040820d7514f04eb38;hb=701000146a01f1966c59f50d7b638915917b6378;hp=90dc4308db69e4bbd2ac7df82ef04535f12ba625;hpb=9c1c2a0bb14ff5f74e68a7f1d67b8a7021c71cdf;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 90dc4308db..a1e761cdf9 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -1,5 +1,5 @@ /* s390-opc.c -- S390 opcode list - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2017 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of the GNU opcodes library. @@ -84,30 +84,26 @@ const struct s390_operand s390_operands[] = { 4, 12, S390_OPERAND_FPR }, #define F_16 17 /* FPR starting at position 16 */ { 4, 16, S390_OPERAND_FPR }, -#define F_20 18 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR }, -#define F_24 19 /* FPR starting at position 24 */ +#define F_24 18 /* FPR starting at position 24 */ { 4, 24, S390_OPERAND_FPR }, -#define F_28 20 /* FPR starting at position 28 */ +#define F_28 19 /* FPR starting at position 28 */ { 4, 28, S390_OPERAND_FPR }, -#define F_32 21 /* FPR starting at position 32 */ +#define F_32 20 /* FPR starting at position 32 */ { 4, 32, S390_OPERAND_FPR }, /* Floating point register pair operands. */ -#define FE_8 22 /* FPR starting at position 8 */ +#define FE_8 21 /* FPR starting at position 8 */ { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_12 23 /* FPR starting at position 12 */ +#define FE_12 22 /* FPR starting at position 12 */ { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_16 24 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_20 25 /* FPR starting at position 16 */ +#define FE_16 23 /* FPR starting at position 16 */ { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_24 26 /* FPR starting at position 24 */ +#define FE_24 24 /* FPR starting at position 24 */ { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_28 27 /* FPR starting at position 28 */ +#define FE_28 25 /* FPR starting at position 28 */ { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, -#define FE_32 28 /* FPR starting at position 32 */ +#define FE_32 26 /* FPR starting at position 32 */ { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, /* Vector register operands. */ @@ -115,137 +111,139 @@ const struct s390_operand s390_operands[] = /* For each of these operands and additional bit in the RXB operand is needed. */ -#define V_8 29 /* Vector reg. starting at position 8 */ +#define V_8 27 /* Vector reg. starting at position 8 */ { 4, 8, S390_OPERAND_VR }, -#define V_12 30 /* Vector reg. starting at position 12 */ +#define V_12 28 /* Vector reg. starting at position 12 */ { 4, 12, S390_OPERAND_VR }, -#define V_CP16_12 31 /* Vector reg. starting at position 12 */ +#define V_CP16_12 29 /* Vector reg. starting at position 12 */ { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ -#define V_16 32 /* Vector reg. starting at position 16 */ +#define V_16 30 /* Vector reg. starting at position 16 */ { 4, 16, S390_OPERAND_VR }, -#define V_32 33 /* Vector reg. starting at position 32 */ +#define V_32 31 /* Vector reg. starting at position 32 */ { 4, 32, S390_OPERAND_VR }, /* Access register operands. */ -#define A_8 34 /* Access reg. starting at position 8 */ +#define A_8 32 /* Access reg. starting at position 8 */ { 4, 8, S390_OPERAND_AR }, -#define A_12 35 /* Access reg. starting at position 12 */ +#define A_12 33 /* Access reg. starting at position 12 */ { 4, 12, S390_OPERAND_AR }, -#define A_24 36 /* Access reg. starting at position 24 */ +#define A_24 34 /* Access reg. starting at position 24 */ { 4, 24, S390_OPERAND_AR }, -#define A_28 37 /* Access reg. starting at position 28 */ +#define A_28 35 /* Access reg. starting at position 28 */ { 4, 28, S390_OPERAND_AR }, /* Control register operands. */ -#define C_8 38 /* Control reg. starting at position 8 */ +#define C_8 36 /* Control reg. starting at position 8 */ { 4, 8, S390_OPERAND_CR }, -#define C_12 39 /* Control reg. starting at position 12 */ +#define C_12 37 /* Control reg. starting at position 12 */ { 4, 12, S390_OPERAND_CR }, /* Base register operands. */ -#define B_16 40 /* Base register starting at position 16 */ +#define B_16 38 /* Base register starting at position 16 */ { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, -#define B_32 41 /* Base register starting at position 32 */ +#define B_32 39 /* Base register starting at position 32 */ { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, -#define X_12 42 /* Index register starting at position 12 */ +#define X_12 40 /* Index register starting at position 12 */ { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, -#define VX_12 43 /* Vector index register starting at position 12 */ +#define VX_12 41 /* Vector index register starting at position 12 */ { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, /* Address displacement operands. */ -#define D_20 44 /* Displacement starting at position 20 */ +#define D_20 42 /* Displacement starting at position 20 */ { 12, 20, S390_OPERAND_DISP }, -#define D_36 45 /* Displacement starting at position 36 */ +#define D_36 43 /* Displacement starting at position 36 */ { 12, 36, S390_OPERAND_DISP }, -#define D20_20 46 /* 20 bit displacement starting at 20 */ +#define D20_20 44 /* 20 bit displacement starting at 20 */ { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, /* Length operands. */ -#define L4_8 47 /* 4 bit length starting at position 8 */ +#define L4_8 45 /* 4 bit length starting at position 8 */ { 4, 8, S390_OPERAND_LENGTH }, -#define L4_12 48 /* 4 bit length starting at position 12 */ +#define L4_12 46 /* 4 bit length starting at position 12 */ { 4, 12, S390_OPERAND_LENGTH }, -#define L8_8 49 /* 8 bit length starting at position 8 */ +#define L8_8 47 /* 8 bit length starting at position 8 */ { 8, 8, S390_OPERAND_LENGTH }, /* Signed immediate operands. */ -#define I8_8 50 /* 8 bit signed value starting at 8 */ +#define I8_8 48 /* 8 bit signed value starting at 8 */ { 8, 8, S390_OPERAND_SIGNED }, -#define I8_32 51 /* 8 bit signed value starting at 32 */ +#define I8_32 49 /* 8 bit signed value starting at 32 */ { 8, 32, S390_OPERAND_SIGNED }, -#define I12_12 52 /* 12 bit signed value starting at 12 */ +#define I12_12 50 /* 12 bit signed value starting at 12 */ { 12, 12, S390_OPERAND_SIGNED }, -#define I16_16 53 /* 16 bit signed value starting at 16 */ +#define I16_16 51 /* 16 bit signed value starting at 16 */ { 16, 16, S390_OPERAND_SIGNED }, -#define I16_32 54 /* 16 bit signed value starting at 32 */ +#define I16_32 52 /* 16 bit signed value starting at 32 */ { 16, 32, S390_OPERAND_SIGNED }, -#define I24_24 55 /* 24 bit signed value starting at 24 */ +#define I24_24 53 /* 24 bit signed value starting at 24 */ { 24, 24, S390_OPERAND_SIGNED }, -#define I32_16 56 /* 32 bit signed value starting at 16 */ +#define I32_16 54 /* 32 bit signed value starting at 16 */ { 32, 16, S390_OPERAND_SIGNED }, /* Unsigned immediate operands. */ -#define U4_8 57 /* 4 bit unsigned value starting at 8 */ +#define U4_8 55 /* 4 bit unsigned value starting at 8 */ { 4, 8, 0 }, -#define U4_12 58 /* 4 bit unsigned value starting at 12 */ +#define U4_12 56 /* 4 bit unsigned value starting at 12 */ { 4, 12, 0 }, -#define U4_16 59 /* 4 bit unsigned value starting at 16 */ +#define U4_16 57 /* 4 bit unsigned value starting at 16 */ { 4, 16, 0 }, -#define U4_20 60 /* 4 bit unsigned value starting at 20 */ +#define U4_20 58 /* 4 bit unsigned value starting at 20 */ { 4, 20, 0 }, -#define U4_24 61 /* 4 bit unsigned value starting at 24 */ +#define U4_24 59 /* 4 bit unsigned value starting at 24 */ { 4, 24, 0 }, -#define U4_OR1_24 62 /* 4 bit unsigned value starting at 24 */ - { 4, 24, S390_OPERAND_OR1 }, -#define U4_OR2_24 63 /* 4 bit unsigned value starting at 24 */ - { 4, 24, S390_OPERAND_OR2 }, -#define U4_OR3_24 64 /* 4 bit unsigned value starting at 24 */ - { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, -#define U4_28 65 /* 4 bit unsigned value starting at 28 */ +#define U4_OR1_24 60 /* 4 bit unsigned value ORed with 1 */ + { 4, 24, S390_OPERAND_OR1 }, /* starting at 24 */ +#define U4_OR2_24 61 /* 4 bit unsigned value ORed with 2 */ + { 4, 24, S390_OPERAND_OR2 }, /* starting at 24 */ +#define U4_OR3_24 62 /* 4 bit unsigned value ORed with 3 */ + { 4, 24, S390_OPERAND_OR1 | S390_OPERAND_OR2 }, /* starting at 24 */ +#define U4_28 63 /* 4 bit unsigned value starting at 28 */ { 4, 28, 0 }, -#define U4_OR8_28 66 - { 4, 28, S390_OPERAND_OR8 }, -#define U4_32 67 /* 4 bit unsigned value starting at 32 */ +#define U4_OR8_28 64 /* 4 bit unsigned value ORed with 8 */ + { 4, 28, S390_OPERAND_OR8 }, /* starting at 28 */ +#define U4_32 65 /* 4 bit unsigned value starting at 32 */ { 4, 32, 0 }, -#define U4_36 68 /* 4 bit unsigned value starting at 36 */ +#define U4_36 66 /* 4 bit unsigned value starting at 36 */ { 4, 36, 0 }, -#define U8_8 69 /* 8 bit unsigned value starting at 8 */ +#define U8_8 67 /* 8 bit unsigned value starting at 8 */ { 8, 8, 0 }, -#define U8_16 70 /* 8 bit unsigned value starting at 16 */ +#define U8_16 68 /* 8 bit unsigned value starting at 16 */ { 8, 16, 0 }, -#define U8_24 71 /* 8 bit unsigned value starting at 24 */ +#define U8_24 69 /* 8 bit unsigned value starting at 24 */ { 8, 24, 0 }, -#define U8_32 72 /* 8 bit unsigned value starting at 32 */ +#define U8_28 70 /* 8 bit unsigned value starting at 28 */ + { 8, 28, 0 }, +#define U8_32 71 /* 8 bit unsigned value starting at 32 */ { 8, 32, 0 }, -#define U12_16 73 /* 12 bit unsigned value starting at 16 */ +#define U12_16 72 /* 12 bit unsigned value starting at 16 */ { 12, 16, 0 }, -#define U16_16 74 /* 16 bit unsigned value starting at 16 */ +#define U16_16 73 /* 16 bit unsigned value starting at 16 */ { 16, 16, 0 }, -#define U16_32 75 /* 16 bit unsigned value starting at 32 */ +#define U16_32 74 /* 16 bit unsigned value starting at 32 */ { 16, 32, 0 }, -#define U32_16 76 /* 32 bit unsigned value starting at 16 */ +#define U32_16 75 /* 32 bit unsigned value starting at 16 */ { 32, 16, 0 }, /* PC-relative address operands. */ -#define J12_12 77 /* 12 bit PC relative offset at 12 */ +#define J12_12 76 /* 12 bit PC relative offset at 12 */ { 12, 12, S390_OPERAND_PCREL }, -#define J16_16 78 /* 16 bit PC relative offset at 16 */ +#define J16_16 77 /* 16 bit PC relative offset at 16 */ { 16, 16, S390_OPERAND_PCREL }, -#define J16_32 79 /* 24 bit PC relative offset at 24 */ +#define J16_32 78 /* 16 bit PC relative offset at 32 */ { 16, 32, S390_OPERAND_PCREL }, -#define J24_24 80 /* 24 bit PC relative offset at 24 */ +#define J24_24 79 /* 24 bit PC relative offset at 24 */ { 24, 24, S390_OPERAND_PCREL }, -#define J32_16 81 /* 32 bit PC relative offset at 16 */ +#define J32_16 80 /* 32 bit PC relative offset at 16 */ { 32, 16, S390_OPERAND_PCREL }, }; @@ -357,7 +355,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ -#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ +#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. ipte */ #define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ @@ -374,8 +372,10 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */ #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */ -#define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. troo */ +#define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. cu24 */ #define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ +#define INSTR_RRF_0URF 4, { R_24,F_28,U4_20,0,0,0 } /* e.g. csdtr */ +#define INSTR_RRF_0UREFE 4, { RE_24,FE_28,U4_20,0,0,0 } /* e.g. csxtr */ #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ #define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ #define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ @@ -429,12 +429,14 @@ const struct s390_operand s390_operands[] = #define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ +#define INSTR_RXY_0RRD 6, { D20_20,X_12,B_16,0,0 } /* e.g. bic */ #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ #define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ #define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ +#define INSTR_SI_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ #define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ @@ -452,29 +454,35 @@ const struct s390_operand s390_operands[] = #define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ #define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ #define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ -#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ +#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */ #define INSTR_VRV_VVXRDU 6, { V_8,D_20,VX_12,B_16,U4_32,0 } /* e.g. vgef */ #define INSTR_VRI_V0U 6, { V_8,U16_16,0,0,0,0 } /* e.g. vgbm */ #define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */ #define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */ #define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */ +#define INSTR_VRI_V0UU2 6, { V_8,U16_16,U4_32,0,0,0 } /* e.g. vlip */ #define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */ #define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */ #define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */ #define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */ #define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */ #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ +#define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ #define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ +#define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */ +#define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */ #define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ #define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ -#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrp */ +#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */ #define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */ #define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */ #define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */ #define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */ #define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ #define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ +#define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */ +#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ @@ -503,6 +511,9 @@ const struct s390_operand s390_operands[] = #define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ #define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ +#define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */ +#define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */ +#define INSTR_VSI_URDV 6, { V_32,D_20,B_16,U8_8,0,0 } /* e.g. vlrl */ #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } @@ -582,6 +593,8 @@ const struct s390_operand s390_operands[] = #define MASK_RRF_U0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_0URF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UREFE { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } #define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } @@ -635,12 +648,14 @@ const struct s390_operand s390_operands[] = #define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SI_RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } @@ -664,14 +679,18 @@ const struct s390_operand s390_operands[] = #define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff } #define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_V0UU2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } #define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff } #define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } #define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } +#define MASK_VRI_VVV0UU2 { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } #define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff } #define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } #define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } #define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } #define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } @@ -681,6 +700,8 @@ const struct s390_operand s390_operands[] = #define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } #define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } #define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } #define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } #define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } @@ -709,36 +730,46 @@ const struct s390_operand s390_operands[] = #define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } #define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } +#define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff } +#define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } +#define MASK_VSI_URDV { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + /* The opcode formats table (blueprints for .insn pseudo mnemonic). */ const struct s390_opcode s390_opformats[] = { - { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, - { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, - { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, - { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, - { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, - { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 ,0 }, - { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, - { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, - { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, - { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 ,0 }, - { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, - { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, - { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, - { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, - { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, - { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, - { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 ,0 }, - { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, - { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, - { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, - { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, - { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, - { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 ,0 }, - { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, - { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 ,0 }, + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, + { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, + { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6 ,0 }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, + { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6 ,0 }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, + { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0 ,0 }, + { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, + { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, + { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0 ,0 }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, + { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0 ,0 }, + { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9 ,0 }, + { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9 ,0 }, + { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9 ,0 }, + { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9 ,0 }, + { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9 ,0 }, + { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10 ,0 }, }; const int s390_num_opformats =