X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=sim%2Fm32r%2Fdecode.h;h=d3bf1553e242b52a5ea023cf9fe1fa58d46d9da6;hb=refs%2Fheads%2Fconcurrent-displaced-stepping-2020-04-01;hp=3b095a748080d724b0ba1755bf730661a581e26d;hpb=4744ac1bb0d2f2294c7762577262fdcafb67883b;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h index 3b095a7480..d3bf1553e2 100644 --- a/sim/m32r/decode.h +++ b/sim/m32r/decode.h @@ -2,22 +2,22 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. +Copyright 1996-2020 Free Software Foundation, Inc. This file is part of the GNU simulators. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3 of the License, or -(at your option) any later version. + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program. If not, see . + You should have received a copy of the GNU General Public License along + with this program; if not, see . */ @@ -25,7 +25,7 @@ along with this program. If not, see . #define M32RBF_DECODE_H extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR, - CGEN_INSN_INT, CGEN_INSN_INT, + CGEN_INSN_WORD, CGEN_INSN_WORD, ARGBUF *); extern void m32rbf_init_idesc_table (SIM_CPU *); extern void m32rbf_sem_init_idesc_table (SIM_CPU *);