X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=sim%2Fmips%2Fsim-main.c;h=d61ce61fc888d6a5ae2b08aec9c033ad2fbf0935;hb=3318ac0e53a673f9989f5e9bbaa9d1c5d536f4e5;hp=7b3e6c61501b486b5fe84c1a687a9953ea92f4a7;hpb=56b48a7a9bec7a6d217d3ad4ff8458cb57e4a511;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c index 7b3e6c6150..d61ce61fc8 100644 --- a/sim/mips/sim-main.c +++ b/sim/mips/sim-main.c @@ -2,7 +2,7 @@ This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or + the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, @@ -11,8 +11,7 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + along with this program; if not, see . */ @@ -29,81 +28,6 @@ /*---------------------------------------------------------------------------*/ -/* Description from page A-22 of the "MIPS IV Instruction Set" manual - (revision 3.1) */ -/* Translate a virtual address to a physical address and cache - coherence algorithm describing the mechanism used to resolve the - memory reference. Given the virtual address vAddr, and whether the - reference is to Instructions ot Data (IorD), find the corresponding - physical address (pAddr) and the cache coherence algorithm (CCA) - used to resolve the reference. If the virtual address is in one of - the unmapped address spaces the physical address and the CCA are - determined directly by the virtual address. If the virtual address - is in one of the mapped address spaces then the TLB is used to - determine the physical address and access type; if the required - translation is not present in the TLB or the desired access is not - permitted the function fails and an exception is taken. - - NOTE: Normally (RAW == 0), when address translation fails, this - function raises an exception and does not return. */ - -INLINE_SIM_MAIN -(int) -address_translation (SIM_DESC sd, - sim_cpu * cpu, - address_word cia, - address_word vAddr, - int IorD, - int LorS, - address_word * pAddr, - int *CCA, - int raw) -{ - int res = -1; /* TRUE : Assume good return */ - -#ifdef DEBUG - sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "isINSTRUCTION"), (LorS ? "iSTORE" : "isLOAD")); -#endif - - /* Check that the address is valid for this memory model */ - - /* For a simple (flat) memory model, we simply pass virtual - addressess through (mostly) unchanged. */ - vAddr &= 0xFFFFFFFF; - - *pAddr = vAddr; /* default for isTARGET */ - *CCA = Uncached; /* not used for isHOST */ - - return (res); -} - - - -/* Description from page A-23 of the "MIPS IV Instruction Set" manual - (revision 3.1) */ -/* Prefetch data from memory. Prefetch is an advisory instruction for - which an implementation specific action is taken. The action taken - may increase performance, but must not change the meaning of the - program, or alter architecturally-visible state. */ - -INLINE_SIM_MAIN (void) -prefetch (SIM_DESC sd, - sim_cpu *cpu, - address_word cia, - int CCA, - address_word pAddr, - address_word vAddr, - int DATA, - int hint) -{ -#ifdef DEBUG - sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); -#endif /* DEBUG */ - - /* For our simple memory model we do nothing */ - return; -} - /* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */ /* Load a value from memory. Use the cache and main memory as @@ -153,9 +77,7 @@ load_memory (SIM_DESC SD, pr_addr (pAddr)); } -#if defined(TRACE) dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); -#endif /* TRACE */ /* Read the specified number of bytes from memory. Adjust for host/target byte ordering/ Align the least significant byte @@ -163,35 +85,35 @@ load_memory (SIM_DESC SD, switch (AccessLength) { - case AccessLength_QUADWORD : + case AccessLength_QUADWORD: { unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr); value1 = VH8_16 (val); value = VL8_16 (val); break; } - case AccessLength_DOUBLEWORD : + case AccessLength_DOUBLEWORD: value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr); break; - case AccessLength_SEPTIBYTE : + case AccessLength_SEPTIBYTE: value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr); break; - case AccessLength_SEXTIBYTE : + case AccessLength_SEXTIBYTE: value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr); break; - case AccessLength_QUINTIBYTE : + case AccessLength_QUINTIBYTE: value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr); break; - case AccessLength_WORD : + case AccessLength_WORD: value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr); break; - case AccessLength_TRIPLEBYTE : + case AccessLength_TRIPLEBYTE: value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr); break; - case AccessLength_HALFWORD : + case AccessLength_HALFWORD: value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr); break; - case AccessLength_BYTE : + case AccessLength_BYTE: value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr); break; default: @@ -265,9 +187,7 @@ store_memory (SIM_DESC SD, (LOADDRMASK + 1) << 3, pr_addr(pAddr)); -#if defined(TRACE) dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); -#endif /* TRACE */ #ifdef DEBUG printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem)); @@ -292,34 +212,34 @@ store_memory (SIM_DESC SD, switch (AccessLength) { - case AccessLength_QUADWORD : + case AccessLength_QUADWORD: { unsigned_16 val = U16_8 (MemElem1, MemElem); sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val); break; } - case AccessLength_DOUBLEWORD : + case AccessLength_DOUBLEWORD: sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_SEPTIBYTE : + case AccessLength_SEPTIBYTE: sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_SEXTIBYTE : + case AccessLength_SEXTIBYTE: sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_QUINTIBYTE : + case AccessLength_QUINTIBYTE: sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_WORD : + case AccessLength_WORD: sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_TRIPLEBYTE : + case AccessLength_TRIPLEBYTE: sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_HALFWORD : + case AccessLength_HALFWORD: sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem); break; - case AccessLength_BYTE : + case AccessLength_BYTE: sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem); break; default: @@ -342,15 +262,13 @@ ifetch32 (SIM_DESC SD, address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); unsigned int byte; - address_word paddr; - int uncached; + address_word paddr = vaddr; unsigned64 memval; if ((vaddr & access) != 0) SignalExceptionInstructionFetch (); - AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); - LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL); + LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL); byte = ((vaddr & mask) ^ bigendiancpu); return (memval >> (8 * byte)); } @@ -368,15 +286,13 @@ ifetch16 (SIM_DESC SD, address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); unsigned int byte; - address_word paddr; - int uncached; + address_word paddr = vaddr; unsigned64 memval; if ((vaddr & access) != 0) SignalExceptionInstructionFetch (); - AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); - LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL); + LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL); byte = ((vaddr & mask) ^ bigendiancpu); return (memval >> (8 * byte)); }