X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=sim%2Fmips%2Fsim-main.h;h=96615a2d56f5d8d27cebba2aceacd1cb8e1ccb67;hb=a1becf61f74c790d9c1134573bb9f2fa56b175b3;hp=256dd1f7c96a88bae442a7f78602e544fd37c18a;hpb=d35d4f709fbc3d254fca5ec67aaeb820bf6a43e2;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 256dd1f7c9..96615a2d56 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -1,49 +1,36 @@ /* MIPS Simulator definition. - Copyright (C) 1997, 1998 Free Software Foundation, Inc. + Copyright (C) 1997-2020 Free Software Foundation, Inc. Contributed by Cygnus Support. -This file is part of GDB, the GNU debugger. +This file is part of the MIPS sim. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ #ifndef SIM_MAIN_H #define SIM_MAIN_H -/* This simulator doesn't cache the Current Instruction Address */ -/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */ -/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */ - -#define SIM_HAVE_BIENDIAN - - -/* hobble some common features for moment */ -#define WITH_WATCHPOINTS 1 -#define WITH_MODULO_MEMORY 1 - +/* MIPS uses an unusual format for floating point quiet NaNs. */ +#define SIM_QUIET_NAN_NEGATED #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) #include "sim-basics.h" - -typedef address_word sim_cia; - #include "sim-base.h" +#include "bfd.h" - -/* Depreciated macros and types for manipulating 64bit values. Use +/* Deprecated macros and types for manipulating 64bit values. Use ../common/sim-bits.h and ../common/sim-endian.h macros instead. */ typedef signed64 word64; @@ -60,10 +47,25 @@ typedef unsigned64 uword64; #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) +typedef enum { + cp0_dmfc0, + cp0_dmtc0, + cp0_mfc0, + cp0_mtc0, + cp0_tlbr, + cp0_tlbwi, + cp0_tlbwr, + cp0_tlbp, + cp0_cache, + cp0_eret, + cp0_deret, + cp0_rfe +} CP0_operation; /* Floating-point operations: */ #include "sim-fpu.h" +#include "cp1.h" /* FPU registers must be one of the following types. All other values are reserved (and undefined). */ @@ -72,6 +74,7 @@ typedef enum { fmt_double = 1, fmt_word = 4, fmt_long = 5, + fmt_ps = 6, /* The following are well outside the normal acceptable format range, and are used in the register status vector. */ fmt_unknown = 0x10000000, @@ -80,40 +83,9 @@ typedef enum { fmt_uninterpreted_64 = 0x80000000U, } FP_formats; -unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats)); -#define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT)) - -void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value)); -#define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE)) - -int NaN PARAMS ((unsigned64 op, FP_formats fmt)); -int Infinity PARAMS ((unsigned64 op, FP_formats fmt)); -int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); -int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); -unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt)); -unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt)); -unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); -unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); -unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); -unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); -unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt)); -unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt)); -unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); -unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); -unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to)); -#define Convert(rm,op,from,to) \ -convert (SD, CPU, cia, rm, op, from, to) - -/* Macro to update FPSR condition-code field. This is complicated by - the fact that there is a hole in the index range of the bits within - the FCSR register. Also, the number of bits visible depends on the - MIPS ISA version being supported. */ - -#define SETFCC(cc,v) {\ - int bit = ((cc == 0) ? 23 : (24 + (cc)));\ - FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\ -} -#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0) +/* For paired word (pw) operations, the opcode representation is fmt_word, + but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */ +#define fmt_pw fmt_long /* This should be the COC1 value at the start of the preceding instruction: */ @@ -128,36 +100,6 @@ convert (SD, CPU, cia, rm, op, from, to) #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE) #endif -/* Standard FCRS bits: */ -#define IR (0) /* Inexact Result */ -#define UF (1) /* UnderFlow */ -#define OF (2) /* OverFlow */ -#define DZ (3) /* Division by Zero */ -#define IO (4) /* Invalid Operation */ -#define UO (5) /* Unimplemented Operation */ - -/* Get masks for individual flags: */ -#if 1 /* SAFE version */ -#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0) -#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0) -#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0) -#else -#define FP_FLAGS(b) (1 << ((b) + 2)) -#define FP_ENABLE(b) (1 << ((b) + 7)) -#define FP_CAUSE(b) (1 << ((b) + 12)) -#endif - -#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */ - -#define FP_MASK_RM (0x3) -#define FP_SH_RM (0) -#define FP_RM_NEAREST (0) /* Round to nearest (Round) */ -#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */ -#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */ -#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */ -#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM) - - @@ -278,10 +220,10 @@ memset (&(CPU)->pending, 0, sizeof ((CPU)->pending)) /* For backward compatibility */ #define PENDING_FILL(R,VAL) \ do { \ - if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \ + if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \ { \ - PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1); \ - PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \ + PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \ + PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \ } \ else \ PENDING_SCHED(GPR[(R)], VAL, 1, -1); \ @@ -296,12 +238,28 @@ enum float_operation }; +/* The internal representation of an MDMX accumulator. + Note that 24 and 48 bit accumulator elements are represented in + 32 or 64 bits. Since the accumulators are 2's complement with + overflow suppressed, high-order bits can be ignored in most contexts. */ + +typedef signed32 signed24; +typedef signed64 signed48; + +typedef union { + signed24 ob[8]; + signed48 qh[4]; +} MDMX_accumulator; + + +/* Conventional system arguments. */ +#define SIM_STATE sim_cpu *cpu, address_word cia +#define SIM_ARGS CPU, cia + struct _sim_cpu { /* The following are internal simulator state variables: */ -#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0) -#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA)) address_word dspc; /* delay-slot PC */ #define DSPC ((CPU)->dspc) @@ -353,10 +311,12 @@ struct _sim_cpu { state. */ #ifndef TM_MIPS_H -#define LAST_EMBED_REGNUM (89) +#define LAST_EMBED_REGNUM (96) #define NUM_REGS (LAST_EMBED_REGNUM + 1) - +#define FP0_REGNUM 38 /* Floating point register 0 (single float) */ +#define FCRCS_REGNUM 70 /* FP control/status */ +#define FCRIR_REGNUM 71 /* FP implementation/revision */ #endif @@ -372,15 +332,6 @@ struct _sim_cpu { #define GPR (®ISTERS[0]) #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) - /* While space is allocated for the floating point registers in the - main registers array, they are stored separatly. This is because - their size may not necessarily match the size of either the - general-purpose or system specific registers */ -#define NR_FGR (32) -#define FGRIDX (38) - fp_word fgr[NR_FGR]; -#define FGR ((CPU)->fgr) - #define LO (REGISTERS[33]) #define HI (REGISTERS[34]) #define PCIDX 37 @@ -396,6 +347,52 @@ struct _sim_cpu { #define Debug (REGISTERS[86]) #define DEPC (REGISTERS[87]) #define EPC (REGISTERS[88]) +#define ACX (REGISTERS[89]) + +#define AC0LOIDX (33) /* Must be the same register as LO */ +#define AC0HIIDX (34) /* Must be the same register as HI */ +#define AC1LOIDX (90) +#define AC1HIIDX (91) +#define AC2LOIDX (92) +#define AC2HIIDX (93) +#define AC3LOIDX (94) +#define AC3HIIDX (95) + +#define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]]) +#define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]]) + +#define DSPCRIDX (96) /* DSP control register */ +#define DSPCR (REGISTERS[DSPCRIDX]) + +#define DSPCR_POS_SHIFT (0) +#define DSPCR_POS_MASK (0x3f) +#define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT) + +#define DSPCR_SCOUNT_SHIFT (7) +#define DSPCR_SCOUNT_MASK (0x3f) +#define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT) + +#define DSPCR_CARRY_SHIFT (13) +#define DSPCR_CARRY_MASK (1) +#define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT) +#define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT) + +#define DSPCR_EFI_SHIFT (14) +#define DSPCR_EFI_MASK (1) +#define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT) +#define DSPCR_EFI (1 << DSPCR_EFI_MASK) + +#define DSPCR_OUFLAG_SHIFT (16) +#define DSPCR_OUFLAG_MASK (0xff) +#define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT) +#define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4)) +#define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5)) +#define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6)) +#define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7)) + +#define DSPCR_CCOND_SHIFT (24) +#define DSPCR_CCOND_MASK (0xf) +#define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT) /* All internal state modified by signal_exception() that may need to be rolled back for passing moment-of-exception image back to gdb. */ @@ -431,7 +428,16 @@ struct _sim_cpu { #define NR_COP0_GPR 32 unsigned_word cop0_gpr[NR_COP0_GPR]; #define COP0_GPR ((CPU)->cop0_gpr) -#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8])) +#define COP0_BADVADDR (COP0_GPR[8]) + + /* While space is allocated for the floating point registers in the + main registers array, they are stored separatly. This is because + their size may not necessarily match the size of either the + general-purpose or system specific registers. */ +#define NR_FGR (32) +#define FGR_BASE FP0_REGNUM + fp_word fgr[NR_FGR]; +#define FGR ((CPU)->fgr) /* Keep the current format state for each register: */ FP_formats fpr_state[32]; @@ -439,6 +445,10 @@ struct _sim_cpu { pending_write_queue pending; + /* The MDMX accumulator (used only for MDMX ASE). */ + MDMX_accumulator acc; +#define ACC ((CPU)->acc) + /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic read-write instructions. It is set when a linked load occurs. It is tested and cleared by the conditional store. It is cleared @@ -458,18 +468,16 @@ struct _sim_cpu { hilo_history lo_history; #define LOHISTORY (&(CPU)->lo_history) -#define check_branch_bug() -#define mark_branch_bug(TARGET) - - sim_cpu_base base; }; +extern void mips_sim_close (SIM_DESC sd, int quitting); +#define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__) /* MIPS specific simulator watch config */ -void watch_options_install PARAMS ((SIM_DESC sd)); +void watch_options_install (SIM_DESC sd); struct swatch { sim_event *pc; @@ -483,13 +491,10 @@ struct sim_state { struct swatch watch; - sim_cpu cpu[MAX_NR_PROCESSORS]; -#if (WITH_SMP) -#define STATE_CPU(sd,n) (&(sd)->cpu[n]) -#else -#define STATE_CPU(sd,n) (&(sd)->cpu[0]) -#endif + sim_cpu *cpu[MAX_NR_PROCESSORS]; + /* microMIPS ISA mode. */ + int isa_mode; sim_state_base base; }; @@ -545,6 +550,8 @@ struct sim_state { #define status_CU1 (1 << 29) /* Coprocessor 1 usable */ #define status_CU2 (1 << 30) /* Coprocessor 2 usable */ #define status_CU3 (1 << 31) /* Coprocessor 3 usable */ +/* Bits reserved for implementations: */ +#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */ #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */ #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */ @@ -585,7 +592,7 @@ struct sim_state { /* Hardware configuration. Affects endianness of LoadMemory and StoreMemory and the endianness of Kernel and Supervisor mode execution. The value is 0 for little-endian; 1 for big-endian. */ -#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) +#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) /*(state & simBE) ? 1 : 0)*/ /* ReverseEndian */ @@ -685,10 +692,10 @@ void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exceptio /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */ #define COP_Usable(coproc_num) (coproc_num == 1) -void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword)); -void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword)); -unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); -uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); +void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword); +void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword); +unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg); +uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg); #define COP_LW(coproc_num,coproc_reg,memword) \ cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword) @@ -700,25 +707,207 @@ cop_sw (SD, CPU, cia, coproc_num, coproc_reg) cop_sd (SD, CPU, cia, coproc_num, coproc_reg) -void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction)); -#define DecodeCoproc(instruction) \ -decode_coproc (SD, CPU, cia, (instruction)) +void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, + unsigned int instruction, int coprocnum, CP0_operation op, + int rt, int rd, int sel); +#define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \ + decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \ + (rt), (rd), (sel)) int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); +/* FPR access. */ +unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats); +#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT)) +void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value); +#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE)) +unsigned64 ps_lower (SIM_STATE, unsigned64 op); +#define PSLower(op) ps_lower (SIM_ARGS, op) +unsigned64 ps_upper (SIM_STATE, unsigned64 op); +#define PSUpper(op) ps_upper (SIM_ARGS, op) +unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from); +#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single) + + +/* FCR access. */ +unsigned_word value_fcr (SIM_STATE, int fcr); +#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR)) +void store_fcr (SIM_STATE, int fcr, unsigned_word value); +#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE)) +void test_fcsr (SIM_STATE); +#define TestFCSR() test_fcsr (SIM_ARGS) + + +/* FPU operations. */ +void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc); +#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc) +unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt); +#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt) +unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt); +#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt) +unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt); +#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt) +unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt); +#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt) +unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt); +#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt) +unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2, + unsigned64 op3, FP_formats fmt); +#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt) +unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2, + unsigned64 op3, FP_formats fmt); +#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt) +unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2, + unsigned64 op3, FP_formats fmt); +#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt) +unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2, + unsigned64 op3, FP_formats fmt); +#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt) +unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to); +#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to) +unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from, + FP_formats to); +#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) + + +/* MIPS-3D ASE operations. */ +#define CompareAbs(op1,op2,fmt,cond,cc) \ +fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) +unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt); +#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) +unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) +unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt); +#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) +unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt); +#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) + + +/* MDMX access. */ + +typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */ +#define ob_fmtsel(sel) (((sel)<<1)|0x0) +#define qh_fmtsel(sel) (((sel)<<2)|0x1) + +#define fmt_mdmx fmt_uninterpreted + +#define MX_VECT_AND (0) +#define MX_VECT_NOR (1) +#define MX_VECT_OR (2) +#define MX_VECT_XOR (3) +#define MX_VECT_SLL (4) +#define MX_VECT_SRL (5) +#define MX_VECT_ADD (6) +#define MX_VECT_SUB (7) +#define MX_VECT_MIN (8) +#define MX_VECT_MAX (9) +#define MX_VECT_MUL (10) +#define MX_VECT_MSGN (11) +#define MX_VECT_SRA (12) +#define MX_VECT_ABSD (13) /* SB-1 only. */ +#define MX_VECT_AVG (14) /* SB-1 only. */ + +unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); +#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel) +#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel) +#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel) +#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel) +#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel) +#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel) +#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel) +#define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel) +#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel) +#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel) +#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel) +#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel) +#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel) +#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel) +#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel) + +#define MX_C_EQ 0x1 +#define MX_C_LT 0x4 + +void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel); +#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel) + +unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel); +#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel) + +#define MX_VECT_ADDA (0) +#define MX_VECT_ADDL (1) +#define MX_VECT_MULA (2) +#define MX_VECT_MULL (3) +#define MX_VECT_MULS (4) +#define MX_VECT_MULSL (5) +#define MX_VECT_SUBA (6) +#define MX_VECT_SUBL (7) +#define MX_VECT_ABSDA (8) /* SB-1 only. */ + +void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel); +#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel) +#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel) +#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel) +#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel) +#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel) +#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel) +#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel) +#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel) +#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel) + +#define MX_FMT_OB (0) +#define MX_FMT_QH (1) + +/* The following codes chosen to indicate the units of shift. */ +#define MX_RAC_L (0) +#define MX_RAC_M (1) +#define MX_RAC_H (2) + +unsigned64 mdmx_rac_op (SIM_STATE, int, int); +#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt) + +void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64); +#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt) +void mdmx_wach (SIM_STATE, int, unsigned64); +#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs) + +#define MX_RND_AS (0) +#define MX_RND_AU (1) +#define MX_RND_ES (2) +#define MX_RND_EU (3) +#define MX_RND_ZS (4) +#define MX_RND_ZU (5) + +unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); +#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt) +#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt) +#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt) +#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt) +#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt) +#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt) + +unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64); +#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2) + + /* Memory accesses */ /* The following are generic to all versions of the MIPS architecture to date: */ -/* Memory Access Types (for CCA): */ -#define Uncached (0) -#define CachedNoncoherent (1) -#define CachedCoherent (2) -#define Cached (3) - #define isINSTRUCTION (1 == 0) /* FALSE */ #define isDATA (1 == 1) /* TRUE */ #define isLOAD (1 == 0) /* FALSE */ @@ -747,44 +936,67 @@ int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE) -INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw)); -#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ -address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) - -INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD)); -#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ -load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD) +INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD); +#define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \ +load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD) -INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr)); -#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ -store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr) +INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr); +#define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ +store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr) -INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction)); +INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction); #define CacheOp(op,pAddr,vAddr,instruction) \ cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction) -INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype)); +INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype); #define SyncOperation(stype) \ sync_operation (SD, CPU, cia, (stype)) -INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint)); -#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \ -prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint) +void unpredictable_action (sim_cpu *cpu, address_word cia); +#define NotWordValue(val) not_word_value (SD_, (val)) +#define Unpredictable() unpredictable (SD_) +#define UnpredictableResult() /* For now, do nothing. */ -INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr)); +INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) -INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr)); +INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) +#define IMEM32_MICROMIPS(CIA) \ + (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \ + (CIA + 2))) +#define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA))) + +#define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10) -void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...)); +#define MICROMIPS_DELAYSLOT_SIZE_ANY 0 +#define MICROMIPS_DELAYSLOT_SIZE_16 2 +#define MICROMIPS_DELAYSLOT_SIZE_32 4 + +extern int isa_mode; + +#define ISA_MODE_MIPS32 0 +#define ISA_MODE_MICROMIPS 1 + +address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu, + address_word cia, + int instruction_size); + +#if WITH_TRACE_ANY_P +void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...); extern FILE *tracefh; +#else +#define dotrace(sd, cpu, tracefh, type, address, width, comment, ...) +#endif + +extern int DSPLO_REGNUM[4]; +extern int DSPHI_REGNUM[4]; -INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia)); +INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia); extern SIM_CORE_SIGNAL_FN mips_core_signal; -char* pr_addr PARAMS ((SIM_ADDR addr)); -char* pr_uword64 PARAMS ((uword64 addr)); +char* pr_addr (SIM_ADDR addr); +char* pr_uword64 (uword64 addr); #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0) @@ -793,6 +1005,24 @@ void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); +#ifdef MIPS_MACH_MULTI +extern int mips_mach_multi(SIM_DESC sd); +#define MIPS_MACH(SD) mips_mach_multi(SD) +#else +#define MIPS_MACH(SD) MIPS_MACH_DEFAULT +#endif + +/* Macros for determining whether a MIPS IV or MIPS V part is subject + to the hi/lo restrictions described in mips.igen. */ + +#define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \ + (MIPS_MACH (SD) != bfd_mach_mips5500) + +#define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \ + (MIPS_MACH (SD) != bfd_mach_mips5500) + +#define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \ + (MIPS_MACH (SD) != bfd_mach_mips5500) #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE) #include "sim-main.c"