X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=sim%2Fmips%2Fsim-main.h;h=96615a2d56f5d8d27cebba2aceacd1cb8e1ccb67;hb=a1becf61f74c790d9c1134573bb9f2fa56b175b3;hp=ae8f0cc9ad04719867f5aba29d1ab0df64773955;hpb=bdca5ee4bcd2fce04de6c9eabdbef8d960298e02;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index ae8f0cc9ad..96615a2d56 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -1,8 +1,8 @@ /* MIPS Simulator definition. - Copyright (C) 1997-2014 Free Software Foundation, Inc. + Copyright (C) 1997-2020 Free Software Foundation, Inc. Contributed by Cygnus Support. -This file is part of GDB, the GNU debugger. +This file is part of the MIPS sim. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -20,25 +20,13 @@ along with this program. If not, see . */ #ifndef SIM_MAIN_H #define SIM_MAIN_H -/* This simulator doesn't cache the Current Instruction Address */ -/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */ -/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */ - -#define SIM_HAVE_BIENDIAN - - -/* hobble some common features for moment */ -#define WITH_WATCHPOINTS 1 -#define WITH_MODULO_MEMORY 1 - +/* MIPS uses an unusual format for floating point quiet NaNs. */ +#define SIM_QUIET_NAN_NEGATED #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) #include "sim-basics.h" - -typedef address_word sim_cia; - #include "sim-base.h" #include "bfd.h" @@ -59,6 +47,20 @@ typedef unsigned64 uword64; #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) +typedef enum { + cp0_dmfc0, + cp0_dmtc0, + cp0_mfc0, + cp0_mtc0, + cp0_tlbr, + cp0_tlbwi, + cp0_tlbwr, + cp0_tlbp, + cp0_cache, + cp0_eret, + cp0_deret, + cp0_rfe +} CP0_operation; /* Floating-point operations: */ @@ -258,8 +260,6 @@ struct _sim_cpu { /* The following are internal simulator state variables: */ -#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0) -#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA)) address_word dspc; /* delay-slot PC */ #define DSPC ((CPU)->dspc) @@ -472,6 +472,8 @@ struct _sim_cpu { sim_cpu_base base; }; +extern void mips_sim_close (SIM_DESC sd, int quitting); +#define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__) /* MIPS specific simulator watch config */ @@ -489,13 +491,10 @@ struct sim_state { struct swatch watch; - sim_cpu cpu[MAX_NR_PROCESSORS]; -#if (WITH_SMP) -#define STATE_CPU(sd,n) (&(sd)->cpu[n]) -#else -#define STATE_CPU(sd,n) (&(sd)->cpu[0]) -#endif + sim_cpu *cpu[MAX_NR_PROCESSORS]; + /* microMIPS ISA mode. */ + int isa_mode; sim_state_base base; }; @@ -593,7 +592,7 @@ struct sim_state { /* Hardware configuration. Affects endianness of LoadMemory and StoreMemory and the endianness of Kernel and Supervisor mode execution. The value is 0 for little-endian; 1 for big-endian. */ -#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) +#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) /*(state & simBE) ? 1 : 0)*/ /* ReverseEndian */ @@ -708,9 +707,12 @@ cop_sw (SD, CPU, cia, coproc_num, coproc_reg) cop_sd (SD, CPU, cia, coproc_num, coproc_reg) -void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction); -#define DecodeCoproc(instruction) \ -decode_coproc (SD, CPU, cia, (instruction)) +void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, + unsigned int instruction, int coprocnum, CP0_operation op, + int rt, int rd, int sel); +#define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \ + decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \ + (rt), (rd), (sel)) int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); @@ -906,12 +908,6 @@ unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64); /* The following are generic to all versions of the MIPS architecture to date: */ -/* Memory Access Types (for CCA): */ -#define Uncached (0) -#define CachedNoncoherent (1) -#define CachedCoherent (2) -#define Cached (3) - #define isINSTRUCTION (1 == 0) /* FALSE */ #define isDATA (1 == 1) /* TRUE */ #define isLOAD (1 == 0) /* FALSE */ @@ -940,17 +936,13 @@ unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64); #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE) -INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw); -#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ -address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) - INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD); -#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ -load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD) +#define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \ +load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD) INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr); -#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ -store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr) +#define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ +store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr) INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction); #define CacheOp(op,pAddr,vAddr,instruction) \ @@ -960,10 +952,6 @@ INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word c #define SyncOperation(stype) \ sync_operation (SD, CPU, cia, (stype)) -INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint); -#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \ -prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint) - void unpredictable_action (sim_cpu *cpu, address_word cia); #define NotWordValue(val) not_word_value (SD_, (val)) #define Unpredictable() unpredictable (SD_) @@ -974,9 +962,32 @@ INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word c INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) +#define IMEM32_MICROMIPS(CIA) \ + (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \ + (CIA + 2))) +#define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA))) + +#define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10) + +#define MICROMIPS_DELAYSLOT_SIZE_ANY 0 +#define MICROMIPS_DELAYSLOT_SIZE_16 2 +#define MICROMIPS_DELAYSLOT_SIZE_32 4 + +extern int isa_mode; +#define ISA_MODE_MIPS32 0 +#define ISA_MODE_MICROMIPS 1 + +address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu, + address_word cia, + int instruction_size); + +#if WITH_TRACE_ANY_P void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...); extern FILE *tracefh; +#else +#define dotrace(sd, cpu, tracefh, type, address, width, comment, ...) +#endif extern int DSPLO_REGNUM[4]; extern int DSPHI_REGNUM[4];