X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=sim%2Ftestsuite%2FChangeLog;h=3be4a00c5c7022c2032a11787429aa902af51d52;hb=78aa740b768e1e62f8bf9d216901245c452a31d9;hp=e876e1f8f679dfbc9eebe0bf8c97dbc0881d3c15;hpb=cff3e48be70e018476521d0f62705c29f4112771;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index e876e1f8f6..3be4a00c5c 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,3 +1,203 @@ +2019-12-19 Tom Tromey + + PR build/24572: + * Makefile.in (install-strip): New target. + +2019-09-23 Dimitar Dimitrov + + * configure: Regenerate. + +2017-12-12 Stafford Horne + Peter Gavin + + * configure: Regenerated. + +2016-01-10 Mike Frysinger + + * configure: Regenerate. + +2016-01-02 Mike Frysinger + + * common/bits-gen.c (main): Change BIG_ENDIAN to BFD_ENDIAN_BIG and + LITTLE_ENDIAN and BFD_ENDIAN_LITTLE. + +2015-11-24 Nick Clifton + + * configure: Regenerate. + * sim/aarch64: New directory. + +2015-11-14 Mike Frysinger + + * lib/sim-defs.exp (slurp_options): Pull in global subdir/srcdir. + Replace $srcdir and $subdir in the read option. + +2015-04-13 Hans-Peter Nilsson + + * lib/sim-defs.exp (sim_init): Unset target ldscript here. + +2015-03-30 Mike Frysinger + + * configure.ac: Add d10v-*-elf. + * configure: Regenerate. + +2015-03-29 Mike Frysinger + + * lib/sim-defs.exp (run_sim_test): Declare seen_output as 0. When + the test has an output keyword, set it to 1. Set default output only + when seen_output is 0. + +2015-03-29 Mike Frysinger + + * configure: Regenerate. + +2015-03-28 Mike Frysinger + + * configure: Regenerate. + +2015-03-28 James Bowman + + * configure: Regenerate. + +2014-03-10 Mike Frysinger + + * configure: Regenerate. + +2014-03-04 Mike Frysinger + + * common/bits-gen.c (main): Change to new style prototype. + +2013-09-23 Alan Modra + + * configure: Regenerate. + +2012-06-15 Joel Brobecker + + * configure: Regenerate. + +2012-03-24 Mike Frysinger + + * configure: Regenerate. + +2012-03-18 Mike Frysinger + + * .gitignore: New file. + +2011-10-17 Mike Frysinger + + * configure: Regenerate after bfin testsuite update. + +2011-05-16 Mike Frysinger + + * lib/sim-defs.exp: Support cc tag in test files. + (run_sim_test): Support global_cc_options in boards files. Convert + assembler options into compiler options (c_as_options) with -Wa. + Convert linker options into compiler options (c_ld_options) with -Wl. + Compile .c and .S files into .x programs. + +2011-05-04 Joseph Myers + + * configure: Regenerate. + +2010-04-26 Mike Frysinger + + * Makefile.in (arch): Set to @sim_arch@. + * configure.ac: Delete arch logic and include ../configure.tgt. + * configure: Regenerated. + * lib/sim-defs.exp (sim_run): Default sim to ../arch/run. + +2009-08-22 Ralf Wildenhues + + * configure: Regenerate. + +2009-01-18 Hans-Peter Nilsson + + * lib/sim-defs.exp (run_sim_test): New option progopts. + +2005-01-11 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2005-01-07 Andrew Cagney + + * configure.ac: Rename configure.in, require autoconf 2.59. + * configure: Re-generate. + + * configure.in: Pass literal subdirectories to AC_CONFIG_SUBDIRS. + * configure: Re-generate. + + * fr30-elf, d30v-elf: Delete directory. + +2004-11-16 Hans-Peter Nilsson + + * lib/sim-defs.exp (run_sim_test): Make multiple "output" + specifications concatenate, not override. + Support "xfail" and "kfail". + +2004-10-26 Nick Clifton + + * lib/sim-defs.exp (sim_run): Add support for the "rawsid" + protocol. + +2004-09-13 DJ Delorie + + * lib/sim-defs.exp (run_sim_test): Add global_as_options, + global_ld_options, and global_sim_options to all test cases, if + defined. + +2004-05-12 Ben Elliston + + * lib/sim-defs.exp: Remove stray semicolons. + +2004-01-26 Chris Demetriou + + * sim/mips: New directory. Tests for the MIPS simulator. + +2004-01-23 Ben Elliston + + * lib/sim-defs.exp (run_sim_test): Delete the .o and .x files if a + test passes. + +2003-08-20 Michael Snyder + On behalf of Dave Brolley + + * sim/frv: New testsuite. + * frv-elf: New testsuite. + +2003-07-09 Michael Snyder + + * sim/sh: New directory. Tests for Renesas sh family. + +2003-04-13 Michael Snyder + + * sim/h8300: New directory. Tests for Renesas h8/300 family. + +2002-06-16 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +2001-07-31 Ben Elliston + + * lib/sim-defs.exp (run_sim_test): Include a description such as + "assembling" or "linking" that identifies the phase a test fails + in, for easier analysis of failures. + +2000-11-01 Dave Brolley + + * lib/sim-defs.exp (run_sm_test): Correct comment. "output" and + "xerror" options do not use a list of machines. Clear options from + previous test case. Use "$cpu_option" to identify the machine to the + assembler, if specified. + +Tue May 23 21:39:23 2000 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-09-15 Doug Evans + + * sim/arm/b.cgs: New testcase. + * sim/arm/bic.cgs: New testcase. + * sim/arm/bl.cgs: New testcase. + Thu Sep 2 18:15:53 1999 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes. @@ -9,18 +209,6 @@ Thu Sep 2 18:15:53 1999 Andrew Cagney Delete locals AS,ASFLAGS,LD,LDFLAGS. Use target_assemble and target_link instead. -1999-04-21 Doug Evans - - * sim/m32r/nop.cgs: Add missing nop insn. - -Mon Mar 22 13:28:56 1999 Dave Brolley - - * sim/fr30/stb.cgs: Correct for unaligned access. - * sim/fr30/sth.cgs: Correct for unaligned access. - * sim/fr30/ldub.cgs: Fix typo: lduh->ldub. Correct - for unaligned access. - * sim/fr30/and.cgs: Test unaligned access. - Fri Feb 5 12:41:11 1999 Doug Evans * lib/sim-defs.exp (sim_run): Print simulator arguments log message. @@ -28,62 +216,6 @@ Fri Feb 5 12:41:11 1999 Doug Evans 1999-01-05 Doug Evans * lib/sim-defs.exp (run_sim_test): New arg all_machs. - * sim/fr30/allinsn.exp: Update. - * sim/fr30/misc.exp: Update. - * sim/m32r/allinsn.exp: Update. - * sim/m32r/misc.exp: Update. - -Fri Dec 18 17:19:34 1998 Dave Brolley - - * sim/fr30/ldres.cgs: New testcase. - * sim/fr30/copld.cgs: New testcase. - * sim/fr30/copst.cgs: New testcase. - * sim/fr30/copsv.cgs: New testcase. - * sim/fr30/nop.cgs: New testcase. - * sim/fr30/andccr.cgs: New testcase. - * sim/fr30/orccr.cgs: New testcase. - * sim/fr30/addsp.cgs: New testcase. - * sim/fr30/stilm.cgs: New testcase. - * sim/fr30/extsb.cgs: New testcase. - * sim/fr30/extub.cgs: New testcase. - * sim/fr30/extsh.cgs: New testcase. - * sim/fr30/extuh.cgs: New testcase. - * sim/fr30/enter.cgs: New testcase. - * sim/fr30/leave.cgs: New testcase. - * sim/fr30/xchb.cgs: New testcase. - * sim/fr30/dmovb.cgs: New testcase. - * sim/fr30/dmov.cgs: New testcase. - * sim/fr30/dmovh.cgs: New testcase. - -Thu Dec 17 17:18:43 1998 Dave Brolley - - * sim/fr30/testutils.inc (take_branch{_d},no_branch{_d}): New macros. - * sim/fr30/ret.cgs: Add tests fir ret:d. - * sim/fr30/inte.cgs: New testcase. - * sim/fr30/reti.cgs: New testcase. - * sim/fr30/bra.cgs: New testcase. - * sim/fr30/bno.cgs: New testcase. - * sim/fr30/beq.cgs: New testcase. - * sim/fr30/bne.cgs: New testcase. - * sim/fr30/bc.cgs: New testcase. - * sim/fr30/bnc.cgs: New testcase. - * sim/fr30/bn.cgs: New testcase. - * sim/fr30/bp.cgs: New testcase. - * sim/fr30/bv.cgs: New testcase. - * sim/fr30/bnv.cgs: New testcase. - * sim/fr30/blt.cgs: New testcase. - * sim/fr30/bge.cgs: New testcase. - * sim/fr30/ble.cgs: New testcase. - * sim/fr30/bgt.cgs: New testcase. - * sim/fr30/bls.cgs: New testcase. - * sim/fr30/bhi.cgs: New testcase. - -Tue Dec 15 17:47:13 1998 Dave Brolley - - * sim/fr30/div.cgs (int): Add signed division scenario. - * sim/fr30/int.cgs (int): Complete testcase. - * sim/fr30/testutils.inc (_start): Initialize tbr. - (test_s_user,test_s_system,set_i,test_i): New macros. 1998-12-14 Doug Evans @@ -91,78 +223,18 @@ Tue Dec 15 17:47:13 1998 Dave Brolley errors. Translate \n sequences in expected output to newline char. (slurp_options): Make parentheses optional. (sim_run): Look for board_info sim,options. - * sim/fr30/hello.ms: Add trailing \n to expected output. - * sim/m32r/hello.ms: Ditto. - * sim/m32r/hw-trap.ms: Ditto. - - * sim/m32r/trap.cgs: Properly align trap2_handler. - - * sim/m32r/uread16.ms: New testcase. - * sim/m32r/uread32.ms: New testcase. - * sim/m32r/uwrite16.ms: New testcase. - * sim/m32r/uwrite32.ms: New testcase. - -1998-12-14 Dave Brolley - - * sim/fr30/call.cgs: Test ret here as well. - * sim/fr30/ld.cgs: Remove bogus comment. - * sim/fr30/testutils.inc (save_rp,restore_rp): New macros. - * sim/fr30/div.ms: New testcase. - * sim/fr30/st.cgs: New testcase. - * sim/fr30/sth.cgs: New testcase. - * sim/fr30/stb.cgs: New testcase. - * sim/fr30/mov.cgs: New testcase. - * sim/fr30/jmp.cgs: New testcase. - * sim/fr30/ret.cgs: New testcase. - * sim/fr30/int.cgs: New testcase. - -Thu Dec 10 18:46:25 1998 Dave Brolley - - * sim/fr30/div0s.cgs: New testcase. - * sim/fr30/div0u.cgs: New testcase. - * sim/fr30/div1.cgs: New testcase. - * sim/fr30/div2.cgs: New testcase. - * sim/fr30/div3.cgs: New testcase. - * sim/fr30/div4s.cgs: New testcase. - * sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros. - -Tue Dec 8 13:16:53 1998 Dave Brolley - - * sim/fr30/testutils.inc (set_s_user): Correct Mask. - (set_s_system): Correct Mask. - * sim/fr30/ld.cgs (ld): Move previously failing test back - into place. - * sim/fr30/ldm0.cgs: New testcase. - * sim/fr30/ldm1.cgs: New testcase. - * sim/fr30/stm0.cgs: New testcase. - * sim/fr30/stm1.cgs: New testcase. - -Thu Dec 3 14:20:03 1998 Dave Brolley - - * sim/fr30/ld.cgs: Implement more loads. - * sim/fr30/call.cgs: New testcase. - * sim/fr30/testutils.inc (testr_h_dr): New macro. - (set_s_user,set_s_system): New macros. - - * sim/fr30: New Directory. Wed Nov 18 10:50:19 1998 Andrew Cagney * common/bits-gen.c (main): Add BYTE_ORDER so that it matches recent sim/common/sim-basics.h changes. * common/Makefile.in: Update. - + Fri Oct 30 00:37:31 1998 Felix Lee * lib/sim-defs.exp (sim_run): download target program to remote host, if necessary. for unix-driven win32 testing. -Tue Sep 15 14:56:22 1998 Doug Evans - - * sim/m32r/testutils.inc (test_h_gr): Use mvaddr_h_gr. - * sim/m32r/rte.cgs: Test bbpc,bbpsw. - * sim/m32r/trap.cgs: Test bbpc,bbpsw. - Fri Jul 31 17:49:13 1998 Felix Lee * lib/sim-defs.exp (sim_run): remote_spawn, use writeto instead of @@ -172,10 +244,6 @@ Fri Jul 24 09:40:34 1998 Doug Evans * Makefile.in (clean,mostlyclean): Change leading spaces to a tab. -Wed Jul 1 15:57:54 1998 Doug Evans - - * sim/m32r/hw-trap.ms: New testcase. - Tue Jun 16 15:44:01 1998 Jillian Ye * lib/sim-defs.exp: Print out timeout setting info when "-v" is used. @@ -185,15 +253,6 @@ Thu Jun 11 15:24:53 1998 Doug Evans * lib/sim-defs.exp (sim_run): Argument env_vals renamed to options, which is now a list of options controlling the behaviour of sim_run. -Wed Jun 10 10:53:20 1998 Doug Evans - - * sim/m32r/addx.cgs: Add another test. - * sim/m32r/jmp.cgs: Add another test. - -Mon Jun 8 16:08:27 1998 Doug Evans - - * sim/m32r/trap.cgs: Test trap 2. - Mon Jun 1 18:54:22 1998 Frank Ch. Eigler * lib/sim-defs.exp (sim_run): Add possible environment variable @@ -201,8 +260,8 @@ Mon Jun 1 18:54:22 1998 Frank Ch. Eigler Thu May 28 14:59:46 1998 Jillian Ye - * Makefile.in: Take RUNTEST out of FLAG_TO_PASS - so that make check can be invoked recursively. + * Makefile.in: Take RUNTEST out of FLAG_TO_PASS + so that make check can be invoked recursively. Thu May 14 11:48:35 1998 Doug Evans @@ -214,8 +273,8 @@ Thu May 14 11:48:35 1998 Doug Evans Fri May 8 18:10:28 1998 Jillian Ye * Makefile.in: Made "check" the target of two - dependencies (test1, test2) so that test2 get a chance to - run even when test1 failed if "make -k check" is used. + dependencies (test1, test2) so that test2 get a chance to + run even when test1 failed if "make -k check" is used. Fri May 8 14:41:28 1998 Doug Evans @@ -237,92 +296,14 @@ Tue Apr 21 10:49:03 1998 Doug Evans * lib/sim-defs.exp (run_sim_test): Don't exit early if one mach fails, try all machs. - * sim/m32r/addx.cgs: Test (-1)+(-1)+1. - -Fri Apr 17 16:00:52 1998 Doug Evans - - * sim/m32r/mv[ft]achi.cgs: Fix expected result - (sign extension of top 8 bits). - Wed Feb 25 11:01:17 1998 Doug Evans * Makefile.in (RUNTEST): Fix path to runtest. - -Fri Feb 20 11:00:02 1998 Nick Clifton - - * sim/m32r/unlock.cgs: Fixed test. - * sim/m32r/mvfc.cgs: Fixed test. - * sim/m32r/remu.cgs: Fixed test. - - * sim/m32r/bnc24.cgs: Test long BNC instruction. - * sim/m32r/bnc8.cgs: Test short BNC instruction. - * sim/m32r/ld-plus.cgs: Test LD instruction. - * sim/m32r/macwhi.cgs: Test MACWHI instruction. - * sim/m32r/macwlo.cgs: Test MACWLO instruction. - * sim/m32r/mulwhi.cgs: Test MULWHI instruction. - * sim/m32r/mulwlo.cgs: Test MULWLO instruction. - * sim/m32r/mvfachi.cgs: Test MVFACHI instruction. - * sim/m32r/mvfaclo.cgs: Test MVFACLO instruction. - * sim/m32r/mvtaclo.cgs: Test MVTACLO instruction. - * sim/m32r/addv.cgs: Test ADDV instruction. - * sim/m32r/addv3.cgs: Test ADDV3 instruction. - * sim/m32r/addx.cgs: Test ADDX instruction. - * sim/m32r/lock.cgs: Test LOCK instruction. - * sim/m32r/neg.cgs: Test NEG instruction. - * sim/m32r/not.cgs: Test NOT instruction. - * sim/m32r/unlock.cgs: Test UNLOCK instruction. -Thu Feb 19 11:15:45 1998 Nick Clifton - - * sim/m32r/testutils.inc (mvaddr_h_gr): new macro to load an - address into a general register. - - * sim/m32r/or3.cgs: Test OR3 instruction. - * sim/m32r/rach.cgs: Test RACH instruction. - * sim/m32r/rem.cgs: Test REM instruction. - * sim/m32r/sub.cgs: Test SUB instruction. - * sim/m32r/mv.cgs: Test MV instruction. - * sim/m32r/mul.cgs: Test MUL instruction. - * sim/m32r/bl24.cgs: Test long BL instruction. - * sim/m32r/bl8.cgs: Test short BL instruction. - * sim/m32r/blez.cgs: Test BLEZ instruction. - * sim/m32r/bltz.cgs: Test BLTZ instruction. - * sim/m32r/bne.cgs: Test BNE instruction. - * sim/m32r/bnez.cgs: Test BNEZ instruction. - * sim/m32r/bra24.cgs: Test long BRA instruction. - * sim/m32r/bra8.cgs: Test short BRA instruction. - * sim/m32r/jl.cgs: Test JL instruction. - * sim/m32r/or.cgs: Test OR instruction. - * sim/m32r/jmp.cgs: Test JMP instruction. - * sim/m32r/and.cgs: Test AND instruction. - * sim/m32r/and3.cgs: Test AND3 instruction. - * sim/m32r/beq.cgs: Test BEQ instruction. - * sim/m32r/beqz.cgs: Test BEQZ instruction. - * sim/m32r/bgez.cgs: Test BGEZ instruction. - * sim/m32r/bgtz.cgs: Test BGTZ instruction. - * sim/m32r/cmp.cgs: Test CMP instruction. - * sim/m32r/cmpi.cgs: Test CMPI instruction. - * sim/m32r/cmpu.cgs: Test CMPU instruction. - * sim/m32r/cmpui.cgs: Test CMPUI instruction. - * sim/m32r/div.cgs: Test DIV instruction. - * sim/m32r/divu.cgs: Test DIVU instruction. - * sim/m32r/cmpeq.cgs: Test CMPEQ instruction. - * sim/m32r/sll.cgs: Test SLL instruction. - * sim/m32r/sll3.cgs: Test SLL3 instruction. - * sim/m32r/slli.cgs: Test SLLI instruction. - * sim/m32r/sra.cgs: Test SRA instruction. - * sim/m32r/sra3.cgs: Test SRA3 instruction. - * sim/m32r/srai.cgs: Test SRAI instruction. - * sim/m32r/srl.cgs: Test SRL instruction. - * sim/m32r/srl3.cgs: Test SRL3 instruction. - * sim/m32r/srli.cgs: Test SRLI instruction. - * sim/m32r/xor3.cgs: Test XOR3 instruction. - * sim/m32r/xor.cgs: Test XOR instruction. Tue Feb 17 12:46:05 1998 Doug Evans * config/default.exp: New file. * lib/sim-defs.exp: New file. - * sim/m32r/*: m32r dejagnu simulator testsuite. * Makefile.in (build_alias): Define. (arch): Define.