X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=tests%2Fbindings%2Fpython%2Fbt2%2Ftest_port.py;h=17945cb0a5119a3cd01bec6a96cc86a978ad4b57;hb=f5567ea88d172767b34373bc6e402da8bfd85ef8;hp=3ba46cdd1772cc4ae3d72b206c758d62ed89256d;hpb=9675ad631e70525a5038995374ceea935a630def;p=babeltrace.git diff --git a/tests/bindings/python/bt2/test_port.py b/tests/bindings/python/bt2/test_port.py index 3ba46cdd..17945cb0 100644 --- a/tests/bindings/python/bt2/test_port.py +++ b/tests/bindings/python/bt2/test_port.py @@ -1,20 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only # # Copyright (C) 2019 EfficiOS Inc. # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# as published by the Free Software Foundation; only version 2 -# of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -# import unittest import bt2 @@ -27,7 +14,7 @@ class PortTestCase(unittest.TestCase): graph = bt2.Graph() if name is None: - name = 'comp' + name = "comp" return graph.add_component(comp_cls, name) @@ -36,41 +23,104 @@ class PortTestCase(unittest.TestCase): bt2._UserSourceComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port = comp_self._add_output_port('out') - self.assertEqual(port.name, 'out') + port = comp_self._add_output_port("out") + self.assertEqual(port.name, "out") comp = self._create_comp(MySource) self.assertEqual(len(comp.output_ports), 1) - self.assertIs(type(comp.output_ports['out']), bt2_port._OutputPortConst) + self.assertIs(type(comp.output_ports["out"]), bt2_port._OutputPortConst) + + # Test adding output port with duplicate name to source. + def test_src_add_output_port_dup_name_raises(self): + class MySource( + bt2._UserSourceComponent, message_iterator_class=bt2._UserMessageIterator + ): + def __init__(comp_self, config, params, obj): + comp_self._add_output_port("out") + + with self.assertRaisesRegex( + ValueError, + "source component `comp` already contains an output port named `out`", + ): + comp_self._add_output_port("out") + + nonlocal seen + seen = True + + seen = False + self._create_comp(MySource) + self.assertTrue(seen) def test_flt_add_output_port(self): class MyFilter( bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port = comp_self._add_output_port('out') - self.assertEqual(port.name, 'out') + port = comp_self._add_output_port("out") + self.assertEqual(port.name, "out") comp = self._create_comp(MyFilter) self.assertEqual(len(comp.output_ports), 1) + # Test adding output port with duplicate name to filter. + def test_flt_add_output_port_dup_name_raises(self): + class MyFilter( + bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator + ): + def __init__(comp_self, config, params, obj): + comp_self._add_output_port("out") + + with self.assertRaisesRegex( + ValueError, + "filter component `comp` already contains an output port named `out`", + ): + comp_self._add_output_port("out") + + nonlocal seen + seen = True + + seen = False + self._create_comp(MyFilter) + self.assertTrue(seen) + def test_flt_add_input_port(self): class MyFilter( bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port = comp_self._add_input_port('in') - self.assertEqual(port.name, 'in') + port = comp_self._add_input_port("in") + self.assertEqual(port.name, "in") comp = self._create_comp(MyFilter) self.assertEqual(len(comp.input_ports), 1) - self.assertIs(type(comp.input_ports['in']), bt2_port._InputPortConst) + self.assertIs(type(comp.input_ports["in"]), bt2_port._InputPortConst) + + # Test adding input port with duplicate name to filter. + def test_flt_add_input_port_dup_name_raises(self): + class MyFilter( + bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator + ): + def __init__(comp_self, config, params, obj): + comp_self._add_input_port("in") + + with self.assertRaisesRegex( + ValueError, + "filter component `comp` already contains an input port named `in`", + ): + comp_self._add_input_port("in") + + nonlocal seen + seen = True + + seen = False + self._create_comp(MyFilter) + self.assertTrue(seen) def test_sink_add_input_port(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - port = comp_self._add_input_port('in') - self.assertEqual(port.name, 'in') + port = comp_self._add_input_port("in") + self.assertEqual(port.name, "in") def _user_consume(self): pass @@ -78,17 +128,39 @@ class PortTestCase(unittest.TestCase): comp = self._create_comp(MySink) self.assertEqual(len(comp.input_ports), 1) + # Test adding input port with duplicate name to sink. + def test_sink_add_input_port_dup_name_raises(self): + class MySink(bt2._UserSinkComponent): + def __init__(comp_self, config, params, obj): + comp_self._add_input_port("in") + + with self.assertRaisesRegex( + ValueError, + "sink component `comp` already contains an input port named `in`", + ): + comp_self._add_input_port("in") + + nonlocal seen + seen = True + + def _user_consume(self): + pass + + seen = False + self._create_comp(MySink) + self.assertTrue(seen) + def test_user_src_output_ports_getitem(self): class MySource( bt2._UserSourceComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port1 = comp_self._add_output_port('clear') - port2 = comp_self._add_output_port('print') - port3 = comp_self._add_output_port('insert') - self.assertEqual(port3.addr, comp_self._output_ports['insert'].addr) - self.assertEqual(port2.addr, comp_self._output_ports['print'].addr) - self.assertEqual(port1.addr, comp_self._output_ports['clear'].addr) + port1 = comp_self._add_output_port("clear") + port2 = comp_self._add_output_port("print") + port3 = comp_self._add_output_port("insert") + self.assertEqual(port3.addr, comp_self._output_ports["insert"].addr) + self.assertEqual(port2.addr, comp_self._output_ports["print"].addr) + self.assertEqual(port1.addr, comp_self._output_ports["clear"].addr) self._create_comp(MySource) @@ -97,12 +169,12 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port1 = comp_self._add_output_port('clear') - port2 = comp_self._add_output_port('print') - port3 = comp_self._add_output_port('insert') - self.assertEqual(port3.addr, comp_self._output_ports['insert'].addr) - self.assertEqual(port2.addr, comp_self._output_ports['print'].addr) - self.assertEqual(port1.addr, comp_self._output_ports['clear'].addr) + port1 = comp_self._add_output_port("clear") + port2 = comp_self._add_output_port("print") + port3 = comp_self._add_output_port("insert") + self.assertEqual(port3.addr, comp_self._output_ports["insert"].addr) + self.assertEqual(port2.addr, comp_self._output_ports["print"].addr) + self.assertEqual(port1.addr, comp_self._output_ports["clear"].addr) self._create_comp(MyFilter) @@ -111,24 +183,24 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port1 = comp_self._add_input_port('clear') - port2 = comp_self._add_input_port('print') - port3 = comp_self._add_input_port('insert') - self.assertEqual(port3.addr, comp_self._input_ports['insert'].addr) - self.assertEqual(port2.addr, comp_self._input_ports['print'].addr) - self.assertEqual(port1.addr, comp_self._input_ports['clear'].addr) + port1 = comp_self._add_input_port("clear") + port2 = comp_self._add_input_port("print") + port3 = comp_self._add_input_port("insert") + self.assertEqual(port3.addr, comp_self._input_ports["insert"].addr) + self.assertEqual(port2.addr, comp_self._input_ports["print"].addr) + self.assertEqual(port1.addr, comp_self._input_ports["clear"].addr) self._create_comp(MyFilter) def test_user_sink_input_ports_getitem(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - port1 = comp_self._add_input_port('clear') - port2 = comp_self._add_input_port('print') - port3 = comp_self._add_input_port('insert') - self.assertEqual(port3.addr, comp_self._input_ports['insert'].addr) - self.assertEqual(port2.addr, comp_self._input_ports['print'].addr) - self.assertEqual(port1.addr, comp_self._input_ports['clear'].addr) + port1 = comp_self._add_input_port("clear") + port2 = comp_self._add_input_port("print") + port3 = comp_self._add_input_port("insert") + self.assertEqual(port3.addr, comp_self._input_ports["insert"].addr) + self.assertEqual(port2.addr, comp_self._input_ports["print"].addr) + self.assertEqual(port1.addr, comp_self._input_ports["clear"].addr) def _user_consume(self): pass @@ -140,12 +212,12 @@ class PortTestCase(unittest.TestCase): bt2._UserSourceComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_output_port('clear') - comp_self._add_output_port('print') - comp_self._add_output_port('insert') + comp_self._add_output_port("clear") + comp_self._add_output_port("print") + comp_self._add_output_port("insert") with self.assertRaises(KeyError): - comp_self._output_ports['hello'] + comp_self._output_ports["hello"] self._create_comp(MySource) @@ -154,12 +226,12 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_output_port('clear') - comp_self._add_output_port('print') - comp_self._add_output_port('insert') + comp_self._add_output_port("clear") + comp_self._add_output_port("print") + comp_self._add_output_port("insert") with self.assertRaises(KeyError): - comp_self._output_ports['hello'] + comp_self._output_ports["hello"] self._create_comp(MyFilter) @@ -168,24 +240,24 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') - comp_self._add_input_port('print') - comp_self._add_input_port('insert') + comp_self._add_input_port("clear") + comp_self._add_input_port("print") + comp_self._add_input_port("insert") with self.assertRaises(KeyError): - comp_self._input_ports['hello'] + comp_self._input_ports["hello"] self._create_comp(MyFilter) def test_user_sink_input_ports_getitem_invalid_key(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') - comp_self._add_input_port('print') - comp_self._add_input_port('insert') + comp_self._add_input_port("clear") + comp_self._add_input_port("print") + comp_self._add_input_port("insert") with self.assertRaises(KeyError): - comp_self._input_ports['hello'] + comp_self._input_ports["hello"] def _user_consume(self): pass @@ -197,9 +269,9 @@ class PortTestCase(unittest.TestCase): bt2._UserSourceComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_output_port('clear') - comp_self._add_output_port('print') - comp_self._add_output_port('insert') + comp_self._add_output_port("clear") + comp_self._add_output_port("print") + comp_self._add_output_port("insert") self.assertEqual(len(comp_self._output_ports), 3) self._create_comp(MySource) @@ -209,9 +281,9 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_output_port('clear') - comp_self._add_output_port('print') - comp_self._add_output_port('insert') + comp_self._add_output_port("clear") + comp_self._add_output_port("print") + comp_self._add_output_port("insert") self.assertEqual(len(comp_self._output_ports), 3) self._create_comp(MyFilter) @@ -221,9 +293,9 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') - comp_self._add_input_port('print') - comp_self._add_input_port('insert') + comp_self._add_input_port("clear") + comp_self._add_input_port("print") + comp_self._add_input_port("insert") self.assertEqual(len(comp_self._input_ports), 3) self._create_comp(MyFilter) @@ -231,9 +303,9 @@ class PortTestCase(unittest.TestCase): def test_user_sink_input_ports_len(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') - comp_self._add_input_port('print') - comp_self._add_input_port('insert') + comp_self._add_input_port("clear") + comp_self._add_input_port("print") + comp_self._add_input_port("insert") self.assertEqual(len(comp_self._input_ports), 3) def _user_consume(self): @@ -246,19 +318,19 @@ class PortTestCase(unittest.TestCase): bt2._UserSourceComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port1 = comp_self._add_output_port('clear') - port2 = comp_self._add_output_port('print') - port3 = comp_self._add_output_port('insert') + port1 = comp_self._add_output_port("clear") + port2 = comp_self._add_output_port("print") + port3 = comp_self._add_output_port("insert") ports = [] for port_name, port in comp_self._output_ports.items(): ports.append((port_name, port)) - self.assertEqual(ports[0][0], 'clear') + self.assertEqual(ports[0][0], "clear") self.assertEqual(ports[0][1].addr, port1.addr) - self.assertEqual(ports[1][0], 'print') + self.assertEqual(ports[1][0], "print") self.assertEqual(ports[1][1].addr, port2.addr) - self.assertEqual(ports[2][0], 'insert') + self.assertEqual(ports[2][0], "insert") self.assertEqual(ports[2][1].addr, port3.addr) self._create_comp(MySource) @@ -268,19 +340,19 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port1 = comp_self._add_output_port('clear') - port2 = comp_self._add_output_port('print') - port3 = comp_self._add_output_port('insert') + port1 = comp_self._add_output_port("clear") + port2 = comp_self._add_output_port("print") + port3 = comp_self._add_output_port("insert") ports = [] for port_name, port in comp_self._output_ports.items(): ports.append((port_name, port)) - self.assertEqual(ports[0][0], 'clear') + self.assertEqual(ports[0][0], "clear") self.assertEqual(ports[0][1].addr, port1.addr) - self.assertEqual(ports[1][0], 'print') + self.assertEqual(ports[1][0], "print") self.assertEqual(ports[1][1].addr, port2.addr) - self.assertEqual(ports[2][0], 'insert') + self.assertEqual(ports[2][0], "insert") self.assertEqual(ports[2][1].addr, port3.addr) self._create_comp(MyFilter) @@ -290,19 +362,19 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - port1 = comp_self._add_input_port('clear') - port2 = comp_self._add_input_port('print') - port3 = comp_self._add_input_port('insert') + port1 = comp_self._add_input_port("clear") + port2 = comp_self._add_input_port("print") + port3 = comp_self._add_input_port("insert") ports = [] for port_name, port in comp_self._input_ports.items(): ports.append((port_name, port)) - self.assertEqual(ports[0][0], 'clear') + self.assertEqual(ports[0][0], "clear") self.assertEqual(ports[0][1].addr, port1.addr) - self.assertEqual(ports[1][0], 'print') + self.assertEqual(ports[1][0], "print") self.assertEqual(ports[1][1].addr, port2.addr) - self.assertEqual(ports[2][0], 'insert') + self.assertEqual(ports[2][0], "insert") self.assertEqual(ports[2][1].addr, port3.addr) self._create_comp(MyFilter) @@ -310,19 +382,19 @@ class PortTestCase(unittest.TestCase): def test_user_sink_input_ports_iter(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - port1 = comp_self._add_input_port('clear') - port2 = comp_self._add_input_port('print') - port3 = comp_self._add_input_port('insert') + port1 = comp_self._add_input_port("clear") + port2 = comp_self._add_input_port("print") + port3 = comp_self._add_input_port("insert") ports = [] for port_name, port in comp_self._input_ports.items(): ports.append((port_name, port)) - self.assertEqual(ports[0][0], 'clear') + self.assertEqual(ports[0][0], "clear") self.assertEqual(ports[0][1].addr, port1.addr) - self.assertEqual(ports[1][0], 'print') + self.assertEqual(ports[1][0], "print") self.assertEqual(ports[1][1].addr, port2.addr) - self.assertEqual(ports[2][0], 'insert') + self.assertEqual(ports[2][0], "insert") self.assertEqual(ports[2][1].addr, port3.addr) def _user_consume(self): @@ -340,14 +412,14 @@ class PortTestCase(unittest.TestCase): ): def __init__(comp_self, config, params, obj): nonlocal port1, port2, port3 - port1 = comp_self._add_output_port('clear') - port2 = comp_self._add_output_port('print') - port3 = comp_self._add_output_port('insert') + port1 = comp_self._add_output_port("clear") + port2 = comp_self._add_output_port("print") + port3 = comp_self._add_output_port("insert") comp = self._create_comp(MySource) - self.assertEqual(port3.addr, comp.output_ports['insert'].addr) - self.assertEqual(port2.addr, comp.output_ports['print'].addr) - self.assertEqual(port1.addr, comp.output_ports['clear'].addr) + self.assertEqual(port3.addr, comp.output_ports["insert"].addr) + self.assertEqual(port2.addr, comp.output_ports["print"].addr) + self.assertEqual(port1.addr, comp.output_ports["clear"].addr) del port1 del port2 del port3 @@ -362,14 +434,14 @@ class PortTestCase(unittest.TestCase): ): def __init__(comp_self, config, params, obj): nonlocal port1, port2, port3 - port1 = comp_self._add_output_port('clear') - port2 = comp_self._add_output_port('print') - port3 = comp_self._add_output_port('insert') + port1 = comp_self._add_output_port("clear") + port2 = comp_self._add_output_port("print") + port3 = comp_self._add_output_port("insert") comp = self._create_comp(MyFilter) - self.assertEqual(port3.addr, comp.output_ports['insert'].addr) - self.assertEqual(port2.addr, comp.output_ports['print'].addr) - self.assertEqual(port1.addr, comp.output_ports['clear'].addr) + self.assertEqual(port3.addr, comp.output_ports["insert"].addr) + self.assertEqual(port2.addr, comp.output_ports["print"].addr) + self.assertEqual(port1.addr, comp.output_ports["clear"].addr) del port1 del port2 del port3 @@ -384,14 +456,14 @@ class PortTestCase(unittest.TestCase): ): def __init__(comp_self, config, params, obj): nonlocal port1, port2, port3 - port1 = comp_self._add_input_port('clear') - port2 = comp_self._add_input_port('print') - port3 = comp_self._add_input_port('insert') + port1 = comp_self._add_input_port("clear") + port2 = comp_self._add_input_port("print") + port3 = comp_self._add_input_port("insert") comp = self._create_comp(MyFilter) - self.assertEqual(port3.addr, comp.input_ports['insert'].addr) - self.assertEqual(port2.addr, comp.input_ports['print'].addr) - self.assertEqual(port1.addr, comp.input_ports['clear'].addr) + self.assertEqual(port3.addr, comp.input_ports["insert"].addr) + self.assertEqual(port2.addr, comp.input_ports["print"].addr) + self.assertEqual(port1.addr, comp.input_ports["clear"].addr) del port1 del port2 del port3 @@ -404,17 +476,17 @@ class PortTestCase(unittest.TestCase): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): nonlocal port1, port2, port3 - port1 = comp_self._add_input_port('clear') - port2 = comp_self._add_input_port('print') - port3 = comp_self._add_input_port('insert') + port1 = comp_self._add_input_port("clear") + port2 = comp_self._add_input_port("print") + port3 = comp_self._add_input_port("insert") def _user_consume(self): pass comp = self._create_comp(MySink) - self.assertEqual(port3.addr, comp.input_ports['insert'].addr) - self.assertEqual(port2.addr, comp.input_ports['print'].addr) - self.assertEqual(port1.addr, comp.input_ports['clear'].addr) + self.assertEqual(port3.addr, comp.input_ports["insert"].addr) + self.assertEqual(port2.addr, comp.input_ports["print"].addr) + self.assertEqual(port1.addr, comp.input_ports["clear"].addr) del port1 del port2 del port3 @@ -424,52 +496,52 @@ class PortTestCase(unittest.TestCase): bt2._UserSourceComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_output_port('clear') - comp_self._add_output_port('print') - comp_self._add_output_port('insert') + comp_self._add_output_port("clear") + comp_self._add_output_port("print") + comp_self._add_output_port("insert") comp = self._create_comp(MySource) with self.assertRaises(KeyError): - comp.output_ports['hello'] + comp.output_ports["hello"] def test_gen_flt_output_ports_getitem_invalid_key(self): class MyFilter( bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_output_port('clear') - comp_self._add_output_port('print') - comp_self._add_output_port('insert') + comp_self._add_output_port("clear") + comp_self._add_output_port("print") + comp_self._add_output_port("insert") comp = self._create_comp(MyFilter) with self.assertRaises(KeyError): - comp.output_ports['hello'] + comp.output_ports["hello"] def test_gen_flt_input_ports_getitem_invalid_key(self): class MyFilter( bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') - comp_self._add_input_port('print') - comp_self._add_input_port('insert') + comp_self._add_input_port("clear") + comp_self._add_input_port("print") + comp_self._add_input_port("insert") comp = self._create_comp(MyFilter) with self.assertRaises(KeyError): - comp.input_ports['hello'] + comp.input_ports["hello"] def test_gen_sink_input_ports_getitem_invalid_key(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') - comp_self._add_input_port('print') - comp_self._add_input_port('insert') + comp_self._add_input_port("clear") + comp_self._add_input_port("print") + comp_self._add_input_port("insert") with self.assertRaises(KeyError): - comp_self._input_ports['hello'] + comp_self._input_ports["hello"] def _user_consume(self): pass @@ -477,16 +549,16 @@ class PortTestCase(unittest.TestCase): comp = self._create_comp(MySink) with self.assertRaises(KeyError): - comp.input_ports['hello'] + comp.input_ports["hello"] def test_gen_src_output_ports_len(self): class MySource( bt2._UserSourceComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_output_port('clear') - comp_self._add_output_port('print') - comp_self._add_output_port('insert') + comp_self._add_output_port("clear") + comp_self._add_output_port("print") + comp_self._add_output_port("insert") comp = self._create_comp(MySource) self.assertEqual(len(comp.output_ports), 3) @@ -496,9 +568,9 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_output_port('clear') - comp_self._add_output_port('print') - comp_self._add_output_port('insert') + comp_self._add_output_port("clear") + comp_self._add_output_port("print") + comp_self._add_output_port("insert") comp = self._create_comp(MyFilter) self.assertEqual(len(comp.output_ports), 3) @@ -508,9 +580,9 @@ class PortTestCase(unittest.TestCase): bt2._UserFilterComponent, message_iterator_class=bt2._UserMessageIterator ): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') - comp_self._add_input_port('print') - comp_self._add_input_port('insert') + comp_self._add_input_port("clear") + comp_self._add_input_port("print") + comp_self._add_input_port("insert") comp = self._create_comp(MyFilter) self.assertEqual(len(comp.input_ports), 3) @@ -518,9 +590,9 @@ class PortTestCase(unittest.TestCase): def test_gen_sink_input_ports_len(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') - comp_self._add_input_port('print') - comp_self._add_input_port('insert') + comp_self._add_input_port("clear") + comp_self._add_input_port("print") + comp_self._add_input_port("insert") def _user_consume(self): pass @@ -538,9 +610,9 @@ class PortTestCase(unittest.TestCase): ): def __init__(comp_self, config, params, obj): nonlocal port1, port2, port3 - port1 = comp_self._add_output_port('clear') - port2 = comp_self._add_output_port('print') - port3 = comp_self._add_output_port('insert') + port1 = comp_self._add_output_port("clear") + port2 = comp_self._add_output_port("print") + port3 = comp_self._add_output_port("insert") comp = self._create_comp(MySource) ports = [] @@ -548,11 +620,11 @@ class PortTestCase(unittest.TestCase): for port_name, port in comp.output_ports.items(): ports.append((port_name, port)) - self.assertEqual(ports[0][0], 'clear') + self.assertEqual(ports[0][0], "clear") self.assertEqual(ports[0][1].addr, port1.addr) - self.assertEqual(ports[1][0], 'print') + self.assertEqual(ports[1][0], "print") self.assertEqual(ports[1][1].addr, port2.addr) - self.assertEqual(ports[2][0], 'insert') + self.assertEqual(ports[2][0], "insert") self.assertEqual(ports[2][1].addr, port3.addr) del port1 del port2 @@ -568,9 +640,9 @@ class PortTestCase(unittest.TestCase): ): def __init__(comp_self, config, params, obj): nonlocal port1, port2, port3 - port1 = comp_self._add_output_port('clear') - port2 = comp_self._add_output_port('print') - port3 = comp_self._add_output_port('insert') + port1 = comp_self._add_output_port("clear") + port2 = comp_self._add_output_port("print") + port3 = comp_self._add_output_port("insert") comp = self._create_comp(MyFilter) ports = [] @@ -578,11 +650,11 @@ class PortTestCase(unittest.TestCase): for port_name, port in comp.output_ports.items(): ports.append((port_name, port)) - self.assertEqual(ports[0][0], 'clear') + self.assertEqual(ports[0][0], "clear") self.assertEqual(ports[0][1].addr, port1.addr) - self.assertEqual(ports[1][0], 'print') + self.assertEqual(ports[1][0], "print") self.assertEqual(ports[1][1].addr, port2.addr) - self.assertEqual(ports[2][0], 'insert') + self.assertEqual(ports[2][0], "insert") self.assertEqual(ports[2][1].addr, port3.addr) del port1 del port2 @@ -598,9 +670,9 @@ class PortTestCase(unittest.TestCase): ): def __init__(comp_self, config, params, obj): nonlocal port1, port2, port3 - port1 = comp_self._add_input_port('clear') - port2 = comp_self._add_input_port('print') - port3 = comp_self._add_input_port('insert') + port1 = comp_self._add_input_port("clear") + port2 = comp_self._add_input_port("print") + port3 = comp_self._add_input_port("insert") comp = self._create_comp(MyFilter) ports = [] @@ -608,11 +680,11 @@ class PortTestCase(unittest.TestCase): for port_name, port in comp.input_ports.items(): ports.append((port_name, port)) - self.assertEqual(ports[0][0], 'clear') + self.assertEqual(ports[0][0], "clear") self.assertEqual(ports[0][1].addr, port1.addr) - self.assertEqual(ports[1][0], 'print') + self.assertEqual(ports[1][0], "print") self.assertEqual(ports[1][1].addr, port2.addr) - self.assertEqual(ports[2][0], 'insert') + self.assertEqual(ports[2][0], "insert") self.assertEqual(ports[2][1].addr, port3.addr) del port1 del port2 @@ -626,9 +698,9 @@ class PortTestCase(unittest.TestCase): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): nonlocal port1, port2, port3 - port1 = comp_self._add_input_port('clear') - port2 = comp_self._add_input_port('print') - port3 = comp_self._add_input_port('insert') + port1 = comp_self._add_input_port("clear") + port2 = comp_self._add_input_port("print") + port3 = comp_self._add_input_port("insert") def _user_consume(self): pass @@ -639,11 +711,11 @@ class PortTestCase(unittest.TestCase): for port_name, port in comp.input_ports.items(): ports.append((port_name, port)) - self.assertEqual(ports[0][0], 'clear') + self.assertEqual(ports[0][0], "clear") self.assertEqual(ports[0][1].addr, port1.addr) - self.assertEqual(ports[1][0], 'print') + self.assertEqual(ports[1][0], "print") self.assertEqual(ports[1][1].addr, port2.addr) - self.assertEqual(ports[2][0], 'insert') + self.assertEqual(ports[2][0], "insert") self.assertEqual(ports[2][1].addr, port3.addr) del port1 del port2 @@ -652,41 +724,41 @@ class PortTestCase(unittest.TestCase): def test_name(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') + comp_self._add_input_port("clear") def _user_consume(self): pass comp = self._create_comp(MySink) - self.assertEqual(comp.input_ports['clear'].name, 'clear') + self.assertEqual(comp.input_ports["clear"].name, "clear") def test_connection_none(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') + comp_self._add_input_port("clear") def _user_consume(self): pass comp = self._create_comp(MySink) - self.assertIsNone(comp.input_ports['clear'].connection) + self.assertIsNone(comp.input_ports["clear"].connection) def test_is_connected_false(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - comp_self._add_input_port('clear') + comp_self._add_input_port("clear") def _user_consume(self): pass comp = self._create_comp(MySink) - self.assertFalse(comp.input_ports['clear'].is_connected) + self.assertFalse(comp.input_ports["clear"].is_connected) def test_self_name(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - port = comp_self._add_input_port('clear') - self.assertEqual(port.name, 'clear') + port = comp_self._add_input_port("clear") + self.assertEqual(port.name, "clear") def _user_consume(self): pass @@ -696,7 +768,7 @@ class PortTestCase(unittest.TestCase): def test_self_connection_none(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - port = comp_self._add_input_port('clear') + port = comp_self._add_input_port("clear") self.assertIsNone(port.connection) def _user_consume(self): @@ -707,7 +779,7 @@ class PortTestCase(unittest.TestCase): def test_self_is_connected_false(self): class MySink(bt2._UserSinkComponent): def __init__(comp_self, config, params, obj): - port = comp_self._add_input_port('clear') + port = comp_self._add_input_port("clear") self.assertFalse(port.is_connected) def _user_consume(self): @@ -727,11 +799,11 @@ class PortTestCase(unittest.TestCase): def __init__(comp_self, config, params, obj): nonlocal user_datas - p = comp_self._add_output_port('port1') + p = comp_self._add_output_port("port1") user_datas.append(p.user_data) - p = comp_self._add_output_port('port2', 2) + p = comp_self._add_output_port("port2", 2) user_datas.append(p.user_data) - p = comp_self._add_output_port('port3', MyUserData()) + p = comp_self._add_output_port("port3", MyUserData()) user_datas.append(p.user_data) user_datas = [] @@ -761,18 +833,18 @@ class PortTestCase(unittest.TestCase): def __init__(comp_self, config, params, obj): nonlocal user_datas - p = comp_self._add_output_port('port1') + p = comp_self._add_output_port("port1") user_datas.append(p.user_data) - p = comp_self._add_output_port('port2', 'user data string') + p = comp_self._add_output_port("port2", "user data string") user_datas.append(p.user_data) - p = comp_self._add_output_port('port3', MyUserData()) + p = comp_self._add_output_port("port3", MyUserData()) user_datas.append(p.user_data) - p = comp_self._add_input_port('port4') + p = comp_self._add_input_port("port4") user_datas.append(p.user_data) - p = comp_self._add_input_port('port5', user_data={'user data': 'dict'}) + p = comp_self._add_input_port("port5", user_data={"user data": "dict"}) user_datas.append(p.user_data) - p = comp_self._add_input_port('port6', MyUserData()) + p = comp_self._add_input_port("port6", MyUserData()) user_datas.append(p.user_data) user_datas = [] @@ -781,10 +853,10 @@ class PortTestCase(unittest.TestCase): comp = self._create_comp(MyFilter) self.assertEqual(len(user_datas), 6) self.assertIs(user_datas[0], None) - self.assertEqual(user_datas[1], 'user data string') + self.assertEqual(user_datas[1], "user data string") self.assertIs(type(user_datas[2]), MyUserData) self.assertIs(user_datas[3], None) - self.assertEqual(user_datas[4], {'user data': 'dict'}) + self.assertEqual(user_datas[4], {"user data": "dict"}) self.assertIs(type(user_datas[5]), MyUserData) # Verify that the user data gets freed. @@ -803,9 +875,9 @@ class PortTestCase(unittest.TestCase): def __init__(comp_self, config, params, obj): nonlocal user_datas - p = comp_self._add_input_port('port1') + p = comp_self._add_input_port("port1") user_datas.append(p.user_data) - p = comp_self._add_input_port('port2', MyUserData()) + p = comp_self._add_input_port("port2", MyUserData()) user_datas.append(p.user_data) def _user_consume(self): @@ -826,5 +898,5 @@ class PortTestCase(unittest.TestCase): self.assertEqual(objects_deleted, 1) -if __name__ == '__main__': +if __name__ == "__main__": unittest.main()