x86: mpx: Give bndX registers actual names
authorDave Hansen <dave.hansen@linux.intel.com>
Fri, 31 Oct 2014 21:58:20 +0000 (14:58 -0700)
committerThomas Gleixner <tglx@linutronix.de>
Mon, 17 Nov 2014 23:58:52 +0000 (00:58 +0100)
commitc04e051cccd2446d9ca373628d14b7e732462f5d
treefe900bd3094f0e6d8574cde4e238cefc86278191
parent6ba48ff46f764414f979d2eacb23c4e6296bcc95
x86: mpx: Give bndX registers actual names

Consider the bndX MPX registers.  There 4 registers each
containing a 64-bit lower and a 64-bit upper bound.  That's 8*64
bits and we declare it thusly:

struct bndregs_struct {
u64 bndregs[8];
}

Let's say you want to read the upper bound from the MPX register
bnd2 out of the xsave buf.  You do:

bndregno = 2;
upper_bound = xsave_buf->bndregs.bndregs[2*bndregno+1];

That kinda sucks.  Every time you access it, you need to know:
1. Each bndX register is two entries wide in "bndregs"
2. The lower comes first followed by upper.  We do the +1 to get
   upper vs. lower.

This replaces the old definition.  You can now access them
indexed by the register number directly, and with a meaningful
name for the lower and upper bound:

bndregno = 2;
xsave_buf->bndreg[bndregno].upper_bound;

It's now *VERY* clear that there are 4 registers.  The programmer
now doesn't have to care what order the lower and upper bounds
are in, and it's harder to get it wrong.

[ tglx: Changed ub/lb to upper_bound/lower_bound and renamed struct
bndreg_struct to struct bndreg ]

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: x86@kernel.org
Cc: "H. Peter Anvin" <hpa@linux.intel.com>
Cc: Qiaowei Ren <qiaowei.ren@intel.com>
Cc: "Yu, Fenghua" <fenghua.yu@intel.com>
Cc: Dave Hansen <dave@sr71.net>
Link: http://lkml.kernel.org/r/20141031215820.5EA5E0EC@viggo.jf.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/x86/include/asm/processor.h
This page took 0.027437 seconds and 5 git commands to generate.