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author	Lucas Stach <dev@lynxeye.de>
	Tue, 22 Jan 2013 21:46:07 +0000 (22:46 +0100)
committer	Stephen Warren <swarren@nvidia.com>
	Mon, 28 Jan 2013 18:24:09 +0000 (11:24 -0700)
commit	ab343e91aa00d6cc1047e8209d610c384ee824b9
tree	d8e4ba8a829d4c1b6922ac511de9df27521ccb22	tree \| snapshot
parent	c0967ce0a7388fa8818f5529897140f4f7ec8543	commit \| diff

ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi

No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

Linux kernel - Deliverables

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arch/arm/boot/dts/tegra20-harmony.dts		diff \| blob \| blame \| history
arch/arm/boot/dts/tegra20-paz00.dts		diff \| blob \| blame \| history
arch/arm/boot/dts/tegra20-seaboard.dts		diff \| blob \| blame \| history
arch/arm/boot/dts/tegra20-tamonten.dtsi		diff \| blob \| blame \| history
arch/arm/boot/dts/tegra20-trimslice.dts		diff \| blob \| blame \| history
arch/arm/boot/dts/tegra20-ventana.dts		diff \| blob \| blame \| history
arch/arm/boot/dts/tegra20-whistler.dts		diff \| blob \| blame \| history
arch/arm/boot/dts/tegra20.dtsi		diff \| blob \| blame \| history