PR binutils/15241

	* lm32.cpu (Control and status registers): Add CFG2, PSW,
	TLBVADDR, TLBPADDR and TLBBADVADDR.

	* lm32-desc.c: Regenerate.

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index ee902521e9e7de4dba9e4e57a0faafab4604e09f..e5a83617c37a72d5fd2fce39ee5ef95188a49c0a 100644 (file)
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,9 @@
+2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
+
+       PR binutils/15241
+       * lm32.cpu (Control and status registers): Add CFG2, PSW,
+       TLBVADDR, TLBPADDR and TLBBADVADDR.
+

 2012-11-30  Oleg Raikhman  <oleg@adapteva.com>
            Joern Rennecke  <joern.rennecke@embecosm.com>
 
 2012-11-30  Oleg Raikhman  <oleg@adapteva.com>
            Joern Rennecke  <joern.rennecke@embecosm.com>
 

diff --git a/cpu/lm32.cpu b/cpu/lm32.cpu
index 31b943d79eba79fde1d9e1235ed00cc6dbb16add..83c839f3392f857bca6f062ef07413a0ac594b31 100644 (file)
--- a/cpu/lm32.cpu
+++ b/cpu/lm32.cpu
@@ -1,5 +1,5 @@
 ; Lattice Mico32 CPU description.  -*- Scheme -*-
 ; Lattice Mico32 CPU description.  -*- Scheme -*-

-; Copyright 2008, 2009  Free Software Foundation, Inc.
+; Copyright 2008-2013  Free Software Foundation, Inc.

 ; Contributed by Jon Beniston <jon@beniston.com>
 ;
 ; This file is part of the GNU Binutils.
 ; Contributed by Jon Beniston <jon@beniston.com>
 ;
 ; This file is part of the GNU Binutils.


@@ -101,9 +101,11 @@
                (EBA 7)
                (DC 8)
                (DEBA 9)
                (EBA 7)
                (DC 8)
                (DEBA 9)

+              (CFG2 10)

                (JTX 14) (JRX 15)          
                (BP0 16) (BP1 17) (BP2 18) (BP3 19)
                (WP0 24) (WP1 25) (WP2 26) (WP3 27)     
                (JTX 14) (JRX 15)          
                (BP0 16) (BP1 17) (BP2 18) (BP3 19)
                (WP0 24) (WP1 25) (WP2 26) (WP3 27)     

+               (PSW 29) (TLBVADDR 30) (TLBPADDR 31) (TLBBADVADDR 31)

               )
   )
   () ()
               )
   )
   () ()

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8ec6e82f6fbfd15ff8cc9fed611b7788caf41df9..f311e1dedfdbbc26136d72ccd989d202f3e33d34 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
+
+       * lm32-desc.c: Regenerate.
+

 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-reg.tbl (riz): Add RegRex64.
 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-reg.tbl (riz): Add RegRex64.

diff --git a/opcodes/lm32-desc.c b/opcodes/lm32-desc.c
index b7420ebf881e52a2aef566df8a0b600eeca9a3a4..3f6adabc1651b45128643e1846e745d871b3c0cb 100644 (file)
--- a/opcodes/lm32-desc.c
+++ b/opcodes/lm32-desc.c
@@ -185,6 +185,7 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
   { "EBA", 7, {0, {{{0, 0}}}}, 0, 0 },
   { "DC", 8, {0, {{{0, 0}}}}, 0, 0 },
   { "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 },
   { "EBA", 7, {0, {{{0, 0}}}}, 0, 0 },
   { "DC", 8, {0, {{{0, 0}}}}, 0, 0 },
   { "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 },

+  { "CFG2", 10, {0, {{{0, 0}}}}, 0, 0 },

   { "JTX", 14, {0, {{{0, 0}}}}, 0, 0 },
   { "JRX", 15, {0, {{{0, 0}}}}, 0, 0 },
   { "BP0", 16, {0, {{{0, 0}}}}, 0, 0 },
   { "JTX", 14, {0, {{{0, 0}}}}, 0, 0 },
   { "JRX", 15, {0, {{{0, 0}}}}, 0, 0 },
   { "BP0", 16, {0, {{{0, 0}}}}, 0, 0 },


@@ -194,13 +195,17 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
   { "WP0", 24, {0, {{{0, 0}}}}, 0, 0 },
   { "WP1", 25, {0, {{{0, 0}}}}, 0, 0 },
   { "WP2", 26, {0, {{{0, 0}}}}, 0, 0 },
   { "WP0", 24, {0, {{{0, 0}}}}, 0, 0 },
   { "WP1", 25, {0, {{{0, 0}}}}, 0, 0 },
   { "WP2", 26, {0, {{{0, 0}}}}, 0, 0 },

-  { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 }
+  { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "PSW", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "TLBVADDR", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "TLBPADDR", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "TLBBADVADDR", 31, {0, {{{0, 0}}}}, 0, 0 }

 };
 
 CGEN_KEYWORD lm32_cgen_opval_h_csr =
 {
   & lm32_cgen_opval_h_csr_entries[0],
 };
 
 CGEN_KEYWORD lm32_cgen_opval_h_csr =
 {
   & lm32_cgen_opval_h_csr_entries[0],

-  20,
+  25,

   0, 0, 0, 0, ""
 };
 
   0, 0, 0, 0, ""
 };