- /*
- * Zero length is only allowed if all these requirements are met:
- * - flow controller is peripheral.
- * - src.addr is aligned to src.width
- * - dst.addr is aligned to dst.width
- *
- * sg_len == 1 should be true, as there can be two cases here:
- * - Memory addresses are contiguous and are not scattered. Here, Only
- * one sg will be passed by user driver, with memory address and zero
- * length. We pass this to controller and after the transfer it will
- * receive the last burst request from peripheral and so transfer
- * finishes.
- *
- * - Memory addresses are scattered and are not contiguous. Here,
- * Obviously as DMA controller doesn't know when a lli's transfer gets
- * over, it can't load next lli. So in this case, there has to be an
- * assumption that only one lli is supported. Thus, we can't have
- * scattered addresses.
- */
- if (!bd.remainder) {
- u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
- PL080_CONFIG_FLOW_CONTROL_SHIFT;
- if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
+ /*
+ * Zero length is only allowed if all these requirements are
+ * met:
+ * - flow controller is peripheral.
+ * - src.addr is aligned to src.width
+ * - dst.addr is aligned to dst.width
+ *
+ * sg_len == 1 should be true, as there can be two cases here:
+ *
+ * - Memory addresses are contiguous and are not scattered.
+ * Here, Only one sg will be passed by user driver, with
+ * memory address and zero length. We pass this to controller
+ * and after the transfer it will receive the last burst
+ * request from peripheral and so transfer finishes.
+ *
+ * - Memory addresses are scattered and are not contiguous.
+ * Here, Obviously as DMA controller doesn't know when a lli's
+ * transfer gets over, it can't load next lli. So in this
+ * case, there has to be an assumption that only one lli is
+ * supported. Thus, we can't have scattered addresses.
+ */
+ if (!bd.remainder) {
+ u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
+ PL080_CONFIG_FLOW_CONTROL_SHIFT;
+ if (!((fc >= PL080_FLOW_SRC2DST_DST) &&