=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in the linker.
=== Patch description ===
This patch is composed of 3 changes:
1) The main change is the addition of the logic for merging a file whose
Tag_CPU_arch build attribute is 15 (ARMv8-R). Namely, all pre-ARMv8 are
merged into ARMv8-R as well as ARMv8-R itself. ARMv8-A (14) merges into
ARMv8-A. ARMv8-M Baseline (16) and Mainline (17) are not allowed to
merge merge with ARMv8-R. Note that merging only occurs if the two
profiles are identical or one is S (Application or Realtime) and the
other is R.
2) using_thumb_only, using_thumb2_bl, using_thumb2 and arch_has_arm_nop
are updated according to capabilities of ARMv8-R and their BFD_ASSERT
updated to reflect that the logic is valid for ARMv8-R.
3) 2 build attribute merging tests are added to test the first change.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (using_thumb_only): Update list of architectures in
BFD_ASSERT for which the logic is valid.
(using_thumb2_bl): Likewise.
(using_thumb2): Likewise and return true for ARMv8-R.
(arch_has_arm_nop): Likewise.
(tag_cpu_arch_combine): New v8r table for ARMv8-R Tag_CPU_arch
merging logic. Update commentis for value 15 of v8m_baseline,
v8m_mainline and v4t_plus_v6_m arrays. Use v8r array to decide
merging of value 15 of Tag_CPU_arch.
ld/
* testsuite/ld-arm/arm-elf.exp (EABI attribute merging 11): New test.
(EABI attribute merging 12): Likewise.
* testsuite/ld-arm/attr-merge-11a.s: New file.
* testsuite/ld-arm/attr-merge-11b.s: New file.
* testsuite/ld-arm/attr-merge-11.attr: New file.
* testsuite/ld-arm/attr-merge-12a.s: New file.
* testsuite/ld-arm/attr-merge-12b.s: New file.
* testsuite/ld-arm/attr-merge-12.attr: New file.
+2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * elf32-arm.c (using_thumb_only): Update list of architectures in
+ BFD_ASSERT for which the logic is valid.
+ (using_thumb2_bl): Likewise.
+ (using_thumb2): Likewise and return true for ARMv8-R.
+ (arch_has_arm_nop): Likewise.
+ (tag_cpu_arch_combine): New v8r table for ARMv8-R Tag_CPU_arch
+ merging logic. Update commentis for value 15 of v8m_baseline,
+ v8m_mainline and v4t_plus_v6_m arrays. Use v8r array to decide
+ merging of value 15 of Tag_CPU_arch.
+
2017-06-23 Jiong Wang <jiong.wang@arm.com>
* reloc.c (BFD_RELOC_AARCH64_ADR_GOTPAGE): Rename to
2017-06-23 Jiong Wang <jiong.wang@arm.com>
* reloc.c (BFD_RELOC_AARCH64_ADR_GOTPAGE): Rename to
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
- || arch == TAG_CPU_ARCH_V8M_BASE
- || arch == TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
if (arch == TAG_CPU_ARCH_V6_M
|| arch == TAG_CPU_ARCH_V6S_M
if (arch == TAG_CPU_ARCH_V6_M
|| arch == TAG_CPU_ARCH_V6S_M
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
- || arch == TAG_CPU_ARCH_V8M_BASE
- || arch == TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V7
|| arch == TAG_CPU_ARCH_V7E_M
|| arch == TAG_CPU_ARCH_V8
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V7
|| arch == TAG_CPU_ARCH_V7E_M
|| arch == TAG_CPU_ARCH_V8
+ || arch == TAG_CPU_ARCH_V8R
|| arch == TAG_CPU_ARCH_V8M_MAIN);
}
|| arch == TAG_CPU_ARCH_V8M_MAIN);
}
bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
- || arch == TAG_CPU_ARCH_V8M_BASE
- || arch == TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
/* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
return (arch == TAG_CPU_ARCH_V6T2
/* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
return (arch == TAG_CPU_ARCH_V6T2
Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
Tag_CPU_arch);
/* Force return logic to be reviewed for each new architecture. */
- BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
- || arch == TAG_CPU_ARCH_V8M_BASE
- || arch == TAG_CPU_ARCH_V8M_MAIN);
+ BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V6K
|| arch == TAG_CPU_ARCH_V7
return (arch == TAG_CPU_ARCH_V6T2
|| arch == TAG_CPU_ARCH_V6K
|| arch == TAG_CPU_ARCH_V7
- || arch == TAG_CPU_ARCH_V8);
+ || arch == TAG_CPU_ARCH_V8
+ || arch == TAG_CPU_ARCH_V8R);
T(V8), /* V7E_M. */
T(V8) /* V8. */
};
T(V8), /* V7E_M. */
T(V8) /* V8. */
};
+ const int v8r[] =
+ {
+ T(V8R), /* PRE_V4. */
+ T(V8R), /* V4. */
+ T(V8R), /* V4T. */
+ T(V8R), /* V5T. */
+ T(V8R), /* V5TE. */
+ T(V8R), /* V5TEJ. */
+ T(V8R), /* V6. */
+ T(V8R), /* V6KZ. */
+ T(V8R), /* V6T2. */
+ T(V8R), /* V6K. */
+ T(V8R), /* V7. */
+ T(V8R), /* V6_M. */
+ T(V8R), /* V6S_M. */
+ T(V8R), /* V7E_M. */
+ T(V8), /* V8. */
+ T(V8R), /* V8R. */
+ };
const int v8m_baseline[] =
{
-1, /* PRE_V4. */
const int v8m_baseline[] =
{
-1, /* PRE_V4. */
T(V8M_BASE), /* V6S_M. */
-1, /* V7E_M. */
-1, /* V8. */
T(V8M_BASE), /* V6S_M. */
-1, /* V7E_M. */
-1, /* V8. */
T(V8M_BASE) /* V8-M BASELINE. */
};
const int v8m_mainline[] =
T(V8M_BASE) /* V8-M BASELINE. */
};
const int v8m_mainline[] =
T(V8M_MAIN), /* V6S_M. */
T(V8M_MAIN), /* V7E_M. */
-1, /* V8. */
T(V8M_MAIN), /* V6S_M. */
T(V8M_MAIN), /* V7E_M. */
-1, /* V8. */
T(V8M_MAIN), /* V8-M BASELINE. */
T(V8M_MAIN) /* V8-M MAINLINE. */
};
T(V8M_MAIN), /* V8-M BASELINE. */
T(V8M_MAIN) /* V8-M MAINLINE. */
};
T(V6S_M), /* V6S_M. */
T(V7E_M), /* V7E_M. */
T(V8), /* V8. */
T(V6S_M), /* V6S_M. */
T(V7E_M), /* V7E_M. */
T(V8), /* V8. */
T(V8M_BASE), /* V8-M BASELINE. */
T(V8M_MAIN), /* V8-M MAINLINE. */
T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
T(V8M_BASE), /* V8-M BASELINE. */
T(V8M_MAIN), /* V8-M MAINLINE. */
T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
v8m_baseline,
v8m_mainline,
/* Pseudo-architecture. */
v8m_baseline,
v8m_mainline,
/* Pseudo-architecture. */
+2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * testsuite/ld-arm/arm-elf.exp (EABI attribute merging 11): New test.
+ (EABI attribute merging 12): Likewise.
+ * testsuite/ld-arm/attr-merge-11a.s: New file.
+ * testsuite/ld-arm/attr-merge-11b.s: New file.
+ * testsuite/ld-arm/attr-merge-11.attr: New file.
+ * testsuite/ld-arm/attr-merge-12a.s: New file.
+ * testsuite/ld-arm/attr-merge-12b.s: New file.
+ * testsuite/ld-arm/attr-merge-12.attr: New file.
+
2017-06-22 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/ld-i386/i386.exp: Run weakundef1 tests.
2017-06-22 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/ld-i386/i386.exp: Run weakundef1 tests.
{"EABI attribute merging 10" "-r" "" "" {attr-merge-10a.s attr-merge-10b.s}
{{readelf -A attr-merge-10.attr}}
"attr-merge-10"}
{"EABI attribute merging 10" "-r" "" "" {attr-merge-10a.s attr-merge-10b.s}
{{readelf -A attr-merge-10.attr}}
"attr-merge-10"}
+ {"EABI attribute merging 11" "-r" "" "" {attr-merge-11a.s attr-merge-11b.s}
+ {{readelf -A attr-merge-11.attr}}
+ "attr-merge-11"}
+ {"EABI attribute merging 12" "-r" "" "" {attr-merge-12a.s attr-merge-12b.s}
+ {{readelf -A attr-merge-12.attr}}
+ "attr-merge-12"}
{"EABI attribute merging 10 (DSP)" "-r" "" "" {attr-merge-10a.s attr-merge-10b-dsp.s}
{{readelf -A attr-merge-10-dsp.attr}}
"attr-merge-10-dsp"}
{"EABI attribute merging 10 (DSP)" "-r" "" "" {attr-merge-10a.s attr-merge-10b-dsp.s}
{{readelf -A attr-merge-10-dsp.attr}}
"attr-merge-10-dsp"}
--- /dev/null
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8-A"
+ Tag_CPU_arch: v8
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+ .arch armv8-a
+
+ @ Tag_CPU_arch & Tag_CPU_arch_profile = v8 || v8-R
+ .eabi_attribute Tag_CPU_arch, 14
+ .eabi_attribute Tag_CPU_arch_profile, 'S'
--- /dev/null
+ .arch armv8-r
+
+ @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-R
+ .eabi_attribute Tag_CPU_arch, 15
+ .eabi_attribute Tag_CPU_arch_profile, 'R'
--- /dev/null
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_name: "8-R"
+ Tag_CPU_arch: v8-R
+ Tag_CPU_arch_profile: Realtime
+ Tag_ARM_ISA_use: Yes
+ Tag_THUMB_ISA_use: Thumb-2
+ Tag_MPextension_use: Allowed
+ Tag_Virtualization_use: TrustZone and Virtualization Extensions
--- /dev/null
+ .arch armv8-r
+
+ @ Tag_CPU_arch & Tag_CPU_arch_profile = v7-R
+ .eabi_attribute Tag_CPU_arch, 10
+ .eabi_attribute Tag_CPU_arch_profile, 'R'
--- /dev/null
+ .arch armv8-r
+
+ @ Tag_CPU_arch & Tag_CPU_arch_profile = v8-R
+ .eabi_attribute Tag_CPU_arch, 15
+ .eabi_attribute Tag_CPU_arch_profile, 'R'