- {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
- {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), FMT_SI, {ROTATE, ENDMASK, REG_22, REG_DEST} },
-
- {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
- {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), FMT_REG, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"rotr", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"extu", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sr.dz", OP_SI(0x8) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sr.dm", OP_SI(0x9) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"exts", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sr.ds", OP_SI(0xA) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"srl", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sr.ez", OP_SI(0xB) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sr.em", OP_SI(0xC) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sra", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sr.es", OP_SI(0xD) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sr.iz", OP_SI(0xE) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+ {"sr.im", OP_SI(0xF) | i(0) | n(1), MASK_SI | i(1) | n(1), 0, {ROTATE, ENDMASK, REG_22, REG_DEST} },
+
+ {"rotr", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"extu", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sr.dz", OP_REG(0x310) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sr.dm", OP_REG(0x312) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"exts", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sr.ds", OP_REG(0x314) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"srl", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sr.ez", OP_REG(0x316) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sr.em", OP_REG(0x318) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sra", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sr.es", OP_REG(0x31A) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sr.iz", OP_REG(0x31C) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },
+ {"sr.im", OP_REG(0x31E) | i(0) | n(1), MASK_REG | i(1) | n(1), 0, {REG_0, ENDMASK, REG_22, REG_DEST} },