Add stack high register and stack low register for MicroBlaze

hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow

binutils/opcodes
          * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
          * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
binutils/gas
          * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
binutils/gas
          * gas/microblaze/allinsn.s: Test use of SHR, SLR
          * gas/microblaze/allinsn.d: Likewise

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c9c0e3633f9f43c2afcd004d933c614500d3da2f..184d3060922c441d0eab9a693f665f6460a44a64 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2012-11-21  Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+       * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
+
 2012-11-20  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/14859

diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index b71383bd88bb2d7fdb862fdf1da54db6407cbfeb..5a427a0740c3f0760daaab19192264dc348f8468 100644 (file)
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -531,6 +531,17 @@ parse_reg (char * s, unsigned * reg)
        }
       return s;
     }
+  /* Stack protection registers.  */
+  else if (strncasecmp (s, "rshr", 4) == 0)
+    {
+      *reg = REG_SHR;
+      return s + 4;
+    }
+  else if (strncasecmp (s, "rslr", 4) == 0)
+    {
+      *reg = REG_SLR;
+      return s + 4;
+    }
   else
     {
       if (TOLOWER (s[0]) == 'r')
@@ -760,6 +771,7 @@ check_spl_reg (unsigned * reg)
       || (*reg == REG_PID)   || (*reg == REG_ZPR)
       || (*reg == REG_TLBX)  || (*reg == REG_TLBLO)
       || (*reg == REG_TLBHI) || (*reg == REG_TLBSX)
+      || (*reg == REG_SHR)   || (*reg == REG_SLR)
       || (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM))
     return TRUE;
 
@@ -1280,6 +1292,10 @@ md_assemble (char * str)
         immed = opcode->immval_mask | REG_TLBLO_MASK;
       else if (reg2 == REG_TLBHI)
         immed = opcode->immval_mask | REG_TLBHI_MASK;
+      else if (reg2 == REG_SHR)
+        immed = opcode->immval_mask | REG_SHR_MASK;
+      else if (reg2 == REG_SLR)
+        immed = opcode->immval_mask | REG_SLR_MASK;
       else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM))
        immed = opcode->immval_mask | REG_PVR_MASK | reg2;
       else
@@ -1331,6 +1347,10 @@ md_assemble (char * str)
         immed = opcode->immval_mask | REG_TLBHI_MASK;
       else if (reg1 == REG_TLBSX)
         immed = opcode->immval_mask | REG_TLBSX_MASK;
+      else if (reg1 == REG_SHR)
+        immed = opcode->immval_mask | REG_SHR_MASK;
+      else if (reg1 == REG_SLR)
+        immed = opcode->immval_mask | REG_SLR_MASK;
       else
         as_fatal (_("invalid value for special purpose register"));
       inst |= (reg2 << RA_LOW) & RA_MASK;

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index b05f2816059c0c0ef6f53b016da1e8f02529e3f1..f460b47041e203afd01c7ceadd67d503e5b421fd 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2012-11-21  David Holsgrove  <david.holsgrove@xilinx.com>
+
+       * gas/microblaze/allinsn.s: Test use of SHR, SLR
+       * gas/microblaze/allinsn.d: Likewise
+
 2012-11-20  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
        * gas/s390/zarch-z9-109.d: Fix srstu opcode.

diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d
index ec140201548ce80d61a15beecc905ff45a8e4f25..4a033404a875a5443f2025d946983000cc327124 100644 (file)
--- a/gas/testsuite/gas/microblaze/allinsn.d
+++ b/gas/testsuite/gas/microblaze/allinsn.d
@@ -31,3 +31,13 @@ Disassembly of section .text:
 
 00000020 <sleep>:
   20:  ba020004        sleep
+
+00000024 <regslr>:
+  24:  b0000000        imm     0
+  28:  31600000        addik   r11, r0, 0
+  2c:  940bc800        mts     rslr, r11
+
+00000030 <regshr>:
+  30:  b0000000        imm     0
+  34:  31600000        addik   r11, r0, 0
+  38:  940bc802        mts     rshr, r11

diff --git a/gas/testsuite/gas/microblaze/allinsn.s b/gas/testsuite/gas/microblaze/allinsn.s
index 582da1767313aa12170913a9b3b81dc5a0aaf3ce..437444f9644738283ab50eb2fe962c5b72a04915 100644 (file)
--- a/gas/testsuite/gas/microblaze/allinsn.s
+++ b/gas/testsuite/gas/microblaze/allinsn.s
@@ -36,4 +36,14 @@ mbar:
     .global sleep
 sleep:
     sleep
+    .text
+    .global regslr
+regslr:
+    la r11,r0,r0
+    mts rslr,r11
+    .text
+    .global regshr
+regshr:
+    la r11,r0,r0
+    mts rshr,r11
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2540f4dbc17c0db36625f517725a9cfe4e66fefc..e5d08b0d223d7872945e654d0f064d8ece9563dd 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2012-11-21  Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+       * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
+       * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
+
 2012-11-20  Kirill Yukhin  <kirill.yukhin@intel.com>
            H.J. Lu  <hongjiu.lu@intel.com>
 

diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index e204e36310db34650bf9b3bd662c6c74b94f193a..7e3a546ff8d6876964cfe9190b430fb93a93418d 100644 (file)
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -139,6 +139,12 @@ get_field_special (long instr, struct op_code_struct * op)
     case REG_TLBSX_MASK :
       strcpy (spr, "tlbsx");
       break;
+    case REG_SHR_MASK :
+      strcpy (spr, "shr");
+      break;
+    case REG_SLR_MASK :
+      strcpy (spr, "slr");
+      break;
     default :
       if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
           == REG_PVR_MASK)

diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 867263e3968edac30dd98777321399af5cbeb708..a2a42d0b9dd9118c7a545e9b8f6b6d8cfa24dc20 100644 (file)
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -79,6 +79,8 @@ enum microblaze_instr_type
 #define REG_BTR_MASK 0x800b
 #define REG_EDR_MASK 0x800d
 #define REG_PVR_MASK 0xa000
+#define REG_SLR_MASK 0x8800
+#define REG_SHR_MASK 0x8802
 
 #define REG_PID_MASK   0x9000
 #define REG_ZPR_MASK   0x9001
@@ -100,6 +102,8 @@ enum microblaze_instr_type
 #define REG_FSR 39 /* FPU Status reg.  */
 #define REG_BTR 43 /* Branch Target reg.  */
 #define REG_EDR 45 /* Exception reg.  */
+#define REG_SHR 50 /* Stack High reg.  */
+#define REG_SLR 51 /* Stack Low reg.  */
 #define REG_PVR 40960 /* Program Verification reg.  */
 
 #define REG_PID   36864 /* MMU: Process ID reg.  */